realtek: dts: declare RTL8264 SerDes lane polarity on Hasivo S1100W-8XGT-SE
The rtl826x PHY driver programs the system-side SerDes lane polarity of the RTL8264 from the "rx-polarity"/"tx-polarity" devicetree properties, defaulting to normal polarity when they are absent. The Hasivo S1100W-8XGT-SE routes half of its high-speed lanes with inverted polarity, which the vendor bootloader compensates for by setting HSI_INV/HSO_INV (VEND1 0xC1 bits 6/7) per PHY. Without the properties the driver clears those bits on every PHY (re-)initialization, which kills the USXGMII link of every port: egress frames never reach the wire while the port MAC MIB keeps counting them, and ingress dies with it (issue #24359 for this board). Declare the polarity for all eight PHYs, matching the values the bootloader programs (read back on hardware in the U-Boot state: alternating HSO_INV/HSI_INV per port pair). The already-supported S1300WP declares these properties the same way. Verified on hardware: on a pristine build both traffic directions are dead; with only this devicetree change, ingress runs at full rate, egress passes traffic, and the link now survives netifd restarts and renegotiation. 10GBase-T ports also negotiate 10G instead of falling back to 5G. Assisted-by: Claude:claude-fable-5 Signed-off-by: Gennaro Cimmino <gcimmino@rayonra.net> Link: https://github.com/openwrt/openwrt/pull/24393 Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/phy/phy.h>
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/ {
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compatible = "hasivo,s1100w-8xgt-se", "realtek,rtl930x-soc";
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@ -171,3 +172,12 @@
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};
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};
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};
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&phy0 { tx-polarity = <PHY_POL_INVERT>; };
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&phy8 { rx-polarity = <PHY_POL_INVERT>; };
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&phy16 { tx-polarity = <PHY_POL_INVERT>; };
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&phy20 { rx-polarity = <PHY_POL_INVERT>; };
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&phy24 { tx-polarity = <PHY_POL_INVERT>; };
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&phy25 { rx-polarity = <PHY_POL_INVERT>; };
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&phy26 { tx-polarity = <PHY_POL_INVERT>; };
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&phy27 { rx-polarity = <PHY_POL_INVERT>; };
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