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uboot-rockchip: update to v2026.07

Browse source 
Drop upstreamed patches.

Delete device trees in `106-board-rockchip-add-HINLINK-H66K-H68K.patch` that have been added to
U-Boot from upstream Linux.

Rebase `108-07-WIP-rockchip-mkimage-Add-rk3576-align-and-sd-card-wo.patch`

Refresh all other patches.

Signed-off-by: Ryan Leung <untilscour@protonmail.com>
Link: https://github.com/openwrt/openwrt/pull/24118
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
This commit is contained in:
Ryan Leung 2026-07-07 10:19:37 +08:00 committed by Jonas Jelonek
parent 0e178e1542
commit ec146e7c9c
No known key found for this signature in database
14 changed files with 37 additions and 1816 deletions
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4
package/boot/uboot-rockchip/Makefile
View file

@ -5,9 +5,9 @@
include $(TOPDIR)/rules.mk
include $(INCLUDE_DIR)/kernel.mk
PKG_VERSION:=2026.01
PKG_VERSION:=2026.07
PKG_RELEASE:=1
PKG_HASH:=b60d5865cefdbc75da8da4156c56c458e00de75a49b80c1a2e58a96e30ad0d54
PKG_HASH:=78e8bfc382fe388f9b55aa1daf8c563522a037779b5d4c349d1415e381f1243e
PKG_MAINTAINER:=Sarah Maedel <openwrt@tbspace.de>

245
package/boot/uboot-rockchip/patches/102-rockchip-Add-initial-RK3582-support.patch
View file

@ -1,245 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 10 Aug 2025 22:26:29 +0000
Subject: rockchip: Add initial RK3582 support
The RK3582 SoC is a variant of the RK3588S with some IP blocks disabled.
What blocks are disabled/non-working is indicated by ip-state in OTP.
This add initial support for RK3582 by using ft_system_setup() to mark
any cpu and/or vdec/venc node with status=fail as indicated by ip-state.
This apply same policy as vendor U-Boot for RK3582, i.e. two big cpu
cores and one vdec/venc core is always failed/disabled.
Enable Kconfig option OF_SYSTEM_SETUP in board defconfig to make use of
the required DT fixups for RK3582 board variants.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
--- a/arch/arm/mach-rockchip/rk3588/rk3588.c
+++ b/arch/arm/mach-rockchip/rk3588/rk3588.c
@@ -7,6 +7,7 @@
#define LOG_CATEGORY LOGC_ARCH
#include <dm.h>
+#include <fdt_support.h>
#include <misc.h>
#include <spl.h>
#include <asm/armv8/mmu.h>
@@ -213,6 +214,15 @@ int arch_cpu_init(void)
#define RK3588_OTP_CPU_CODE_OFFSET 0x02
#define RK3588_OTP_SPECIFICATION_OFFSET 0x06
+#define RK3588_OTP_IP_STATE_OFFSET 0x1d
+
+#define FAIL_CPU_CLUSTER0 GENMASK(3, 0)
+#define FAIL_CPU_CLUSTER1 GENMASK(5, 4)
+#define FAIL_CPU_CLUSTER2 GENMASK(7, 6)
+#define FAIL_RKVDEC0 BIT(6)
+#define FAIL_RKVDEC1 BIT(7)
+#define FAIL_RKVENC0 BIT(0)
+#define FAIL_RKVENC1 BIT(2)
int checkboard(void)
{
@@ -258,3 +268,199 @@ int checkboard(void)
return 0;
}
+
+static int fdt_path_del_node(void *fdt, const char *path)
+{
+ int nodeoffset;
+
+ nodeoffset = fdt_path_offset(fdt, path);
+ if (nodeoffset < 0)
+ return nodeoffset;
+
+ return fdt_del_node(fdt, nodeoffset);
+}
+
+static int fdt_path_set_name(void *fdt, const char *path, const char *name)
+{
+ int nodeoffset;
+
+ nodeoffset = fdt_path_offset(fdt, path);
+ if (nodeoffset < 0)
+ return nodeoffset;
+
+ return fdt_set_name(fdt, nodeoffset, name);
+}
+
+/*
+ * RK3582 is a variant of the RK3588S with some IP blocks disabled. What blocks
+ * are disabled/non-working is indicated by ip-state in OTP. ft_system_setup()
+ * is used to mark any cpu and/or vdec/venc node with status=fail as indicated
+ * by ip-state. Apply same policy as vendor U-Boot for RK3582, i.e. two big cpu
+ * cores and one vdec/venc core is always failed. Enable OF_SYSTEM_SETUP to make
+ * use of the required DT fixups for RK3582 board variants.
+ */
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+ static const char * const cpu_node_names[] = {
+ "cpu@0", "cpu@100", "cpu@200", "cpu@300",
+ "cpu@400", "cpu@500", "cpu@600", "cpu@700",
+ };
+ int parent, node, i, comp_len, len, ret;
+ bool cluster1_removed = false;
+ u8 cpu_code[2], ip_state[3];
+ struct udevice *dev;
+ char soc_comp[16];
+ const char *comp;
+ void *data;
+
+ if (!IS_ENABLED(CONFIG_OF_SYSTEM_SETUP))
+ return 0;
+
+ if (!IS_ENABLED(CONFIG_ROCKCHIP_OTP) || !CONFIG_IS_ENABLED(MISC))
+ return -ENOSYS;
+
+ ret = uclass_get_device_by_driver(UCLASS_MISC,
+ DM_DRIVER_GET(rockchip_otp), &dev);
+ if (ret) {
+ log_debug("Could not find otp device, ret=%d\n", ret);
+ return ret;
+ }
+
+ /* cpu-code: SoC model, e.g. 0x35 0x82 or 0x35 0x88 */
+ ret = misc_read(dev, RK3588_OTP_CPU_CODE_OFFSET, cpu_code, 2);
+ if (ret < 0) {
+ log_debug("Could not read cpu-code, ret=%d\n", ret);
+ return ret;
+ }
+
+ log_debug("cpu-code: %02x %02x\n", cpu_code[0], cpu_code[1]);
+
+ /* only fail cores on rk3582/rk3583 */
+ if (!(cpu_code[0] == 0x35 && cpu_code[1] == 0x82) &&
+ !(cpu_code[0] == 0x35 && cpu_code[1] == 0x83))
+ return 0;
+
+ ret = misc_read(dev, RK3588_OTP_IP_STATE_OFFSET, &ip_state, 3);
+ if (ret < 0) {
+ log_err("Could not read ip-state, ret=%d\n", ret);
+ return ret;
+ }
+
+ log_debug("ip-state: %02x %02x %02x (otp)\n",
+ ip_state[0], ip_state[1], ip_state[2]);
+
+ /* policy: fail entire big core cluster when one or more core is bad */
+ if (ip_state[0] & FAIL_CPU_CLUSTER1)
+ ip_state[0] |= FAIL_CPU_CLUSTER1;
+ if (ip_state[0] & FAIL_CPU_CLUSTER2)
+ ip_state[0] |= FAIL_CPU_CLUSTER2;
+
+ /* policy: always fail one big core cluster on rk3582/rk3583 */
+ if (!(ip_state[0] & (FAIL_CPU_CLUSTER1 | FAIL_CPU_CLUSTER2)))
+ ip_state[0] |= FAIL_CPU_CLUSTER2;
+
+ /* policy: always fail one rkvdec core on rk3582/rk3583 */
+ if (!(ip_state[1] & (FAIL_RKVDEC0 | FAIL_RKVDEC1)))
+ ip_state[1] |= FAIL_RKVDEC1;
+
+ /* policy: always fail one rkvenc core on rk3582/rk3583 */
+ if (!(ip_state[2] & (FAIL_RKVENC0 | FAIL_RKVENC1)))
+ ip_state[2] |= FAIL_RKVENC1;
+
+ log_debug("ip-state: %02x %02x %02x (policy)\n",
+ ip_state[0], ip_state[1], ip_state[2]);
+
+ /* cpu cluster1: ip_state[0]: bit4~5 */
+ if ((ip_state[0] & FAIL_CPU_CLUSTER1) == FAIL_CPU_CLUSTER1) {
+ log_debug("remove cpu-map cluster1\n");
+ fdt_path_del_node(blob, "/cpus/cpu-map/cluster1");
+ cluster1_removed = true;
+ }
+
+ /* cpu cluster2: ip_state[0]: bit6~7 */
+ if ((ip_state[0] & FAIL_CPU_CLUSTER2) == FAIL_CPU_CLUSTER2) {
+ log_debug("remove cpu-map cluster2\n");
+ fdt_path_del_node(blob, "/cpus/cpu-map/cluster2");
+ } else if (cluster1_removed) {
+ /* cluster nodes must be named in a continuous series */
+ log_debug("rename cpu-map cluster2\n");
+ fdt_path_set_name(blob, "/cpus/cpu-map/cluster2", "cluster1");
+ }
+
+ /* rkvdec: ip_state[1]: bit6,7 */
+ if (ip_state[1] & FAIL_RKVDEC0) {
+ log_debug("fail rkvdec0\n");
+ fdt_status_fail_by_pathf(blob, "/video-codec@fdc38100");
+ fdt_status_fail_by_pathf(blob, "/iommu@fdc38700");
+ }
+ if (ip_state[1] & FAIL_RKVDEC1) {
+ log_debug("fail rkvdec1\n");
+ fdt_status_fail_by_pathf(blob, "/video-codec@fdc40100");
+ fdt_status_fail_by_pathf(blob, "/iommu@fdc40700");
+ }
+
+ /* rkvenc: ip_state[2]: bit0,2 */
+ if (ip_state[2] & FAIL_RKVENC0) {
+ log_debug("fail rkvenc0\n");
+ fdt_status_fail_by_pathf(blob, "/video-codec@fdbd0000");
+ fdt_status_fail_by_pathf(blob, "/iommu@fdbdf000");
+ }
+ if (ip_state[2] & FAIL_RKVENC1) {
+ log_debug("fail rkvenc1\n");
+ fdt_status_fail_by_pathf(blob, "/video-codec@fdbe0000");
+ fdt_status_fail_by_pathf(blob, "/iommu@fdbef000");
+ }
+
+ parent = fdt_path_offset(blob, "/cpus");
+ if (parent < 0) {
+ log_err("Could not find /cpus, parent=%d\n", parent);
+ return parent;
+ }
+
+ /* cpu: ip_state[0]: bit0~7 */
+ for (i = 0; i < 8; i++) {
+ /* fail any bad cpu core */
+ if (!(ip_state[0] & BIT(i)))
+ continue;
+
+ node = fdt_subnode_offset(blob, parent, cpu_node_names[i]);
+ if (node >= 0) {
+ log_debug("fail cpu %s\n", cpu_node_names[i]);
+ fdt_status_fail(blob, node);
+ } else {
+ log_err("Could not find %s, node=%d\n",
+ cpu_node_names[i], node);
+ return node;
+ }
+ }
+
+ node = fdt_path_offset(blob, "/");
+ if (node < 0) {
+ log_err("Could not find /, node=%d\n", node);
+ return node;
+ }
+
+ snprintf(soc_comp, sizeof(soc_comp), "rockchip,rk35%x", cpu_code[1]);
+
+ for (i = 0, comp_len = 0;
+ (comp = fdt_stringlist_get(blob, node, "compatible", i, &len));
+ i++) {
+ /* stop at soc compatible */
+ if (!strcmp(comp, soc_comp) ||
+ !strcmp(comp, "rockchip,rk3588s") ||
+ !strcmp(comp, "rockchip,rk3588"))
+ break;
+
+ log_debug("compatible[%d]: %s\n", i, comp);
+ comp_len += len + 1;
+ }
+
+ /* truncate to only include board compatible */
+ fdt_setprop_placeholder(blob, node, "compatible", comp_len, &data);
+
+ /* append soc compatible */
+ fdt_appendprop_string(blob, node, "compatible", soc_comp);
+ fdt_appendprop_string(blob, node, "compatible", "rockchip,rk3588s");
+
+ return 0;
+}

72
package/boot/uboot-rockchip/patches/103-rockchip-rk3588-generic-Enable-support-for-RK3582.patch
View file

@ -1,72 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 10 Aug 2025 22:26:30 +0000
Subject: rockchip: rk3588-generic: Enable support for RK3582
Add Kconfig option OF_SYSTEM_SETUP=y to support booting boards with a
RK3582 SoC. CPU and GPU cores are failed based on ip-state and policy.
Tested on a ROCK 5C Lite v1.1:
cpu-code: 35 82
ip-state: 10 00 00 (otp)
ip-state: 30 80 04 (policy)
remove cpu-map cluster1
rename cpu-map cluster2
fail rkvdec1
fail rkvenc1
fail cpu cpu@400
fail cpu cpu@500
and on a Radxa E52C:
cpu-code: 35 82
ip-state: 00 04 00 (otp)
ip-state: c0 84 04 (policy)
remove cpu-map cluster2
fail rkvdec1
fail rkvenc1
fail cpu cpu@600
fail cpu cpu@700
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
--- a/arch/arm/dts/rk3588-generic.dts
+++ b/arch/arm/dts/rk3588-generic.dts
@@ -1,13 +1,13 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Minimal generic DT for RK3588S/RK3588 with eMMC, SD-card and USB OTG enabled
+ * Minimal generic DT for RK3582/RK3588S/RK3588 with eMMC, SD-card and USB OTG enabled
*/
/dts-v1/;
#include "rk3588s.dtsi"
/ {
- model = "Generic RK3588S/RK3588";
+ model = "Generic RK3582/RK3588S/RK3588";
compatible = "rockchip,rk3588";
aliases {
--- a/configs/generic-rk3588_defconfig
+++ b/configs/generic-rk3588_defconfig
@@ -16,6 +16,7 @@ CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
# CONFIG_BOOTMETH_VBE is not set
CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-generic.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0x40000
--- a/doc/board/rockchip/rockchip.rst
+++ b/doc/board/rockchip/rockchip.rst
@@ -154,7 +154,7 @@ List of mainline supported Rockchip boar
- FriendlyElec NanoPi R6C (nanopi-r6c-rk3588s)
- FriendlyElec NanoPi R6S (nanopi-r6s-rk3588s)
- GameForce Ace (gameforce-ace-rk3588s)
- - Generic RK3588S/RK3588 (generic-rk3588)
+ - Generic RK3582/RK3588S/RK3588 (generic-rk3588)
- Hardkernel ODROID-M2 (odroid-m2-rk3588s)
- Indiedroid Nova (nova-rk3588s)
- Khadas Edge2 (khadas-edge2-rk3588s)

32
package/boot/uboot-rockchip/patches/104-rockchip-rk3588s-rock-5c-Add-support-for-ROCK-5C-Lit.patch
View file

@ -1,32 +0,0 @@
From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Jonas Karlman <jonas@kwiboo.se>
Date: Sun, 10 Aug 2025 22:26:31 +0000
Subject: rockchip: rk3588s-rock-5c: Add support for ROCK 5C Lite variant
Add Kconfig option OF_SYSTEM_SETUP=y to support booting ROCK 5C Lite
boards with a RK3582 SoC. CPU and GPU cores are failed based on ip-state
and policy.
Tested on a ROCK 5C Lite v1.1:
cpu-code: 35 82
ip-state: 00 80 00 (otp)
ip-state: c0 80 04 (policy)
remove cpu-map cluster2
fail rkvdec1
fail rkvenc1
fail cpu cpu@600
fail cpu cpu@700
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
--- a/configs/rock-5c-rk3588s_defconfig
+++ b/configs/rock-5c-rk3588s_defconfig
@@ -18,6 +18,7 @@ CONFIG_FIT_VERBOSE=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588s-rock-5c.dtb"
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0x40000

662
package/boot/uboot-rockchip/patches/105-1-arm64-dts-rockchip-add-LinkEase-EasePi-R1.patch
View file

@ -1,662 +0,0 @@
From 63d60b21fd4933080ff22bdc21652f7c2a14bc52 Mon Sep 17 00:00:00 2001
From: Liangbin Lian <jjm2473@gmail.com>
Date: Tue, 14 Oct 2025 13:12:26 +0800
Subject: [PATCH 1/2] arm64: dts: rockchip: add LinkEase EasePi R1
LinkEase EasePi R1 [1] is a high-performance mini router.
Specification:
- Rockchip RK3568
- 2GB/4GB LPDDR4 RAM
- 16GB on-board eMMC
- 1x M.2 key for 2280 NVMe (PCIe 3.0)
- 1x USB 3.0 Type-A
- 1x USB 2.0 Type-C (for USB flashing)
- 2x 1000 Base-T (native, RTL8211F)
- 2x 2500 Base-T (PCIe, RTL8125B)
- 1x HDMI 2.0 Output
- 12v DC Jack
- 1x Power key connected to PMIC
- 2x LEDs (one static power supplied, one GPIO controlled)
[1] https://doc.linkease.com/zh/guide/easepi-r1/hardware.html
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Liangbin Lian <jjm2473@gmail.com>
Link: https://patch.msgid.link/20251014051226.64255-4-jjm2473@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
[ upstream commit: deaefeaf3df433d50935b9a85076041040f06d74 ]
Signed-off-by: Liangbin Lian <jjm2473@gmail.com>
---
.../src/arm64/rockchip/rk3568-easepi-r1.dts | 623 ++++++++++++++++++
1 file changed, 623 insertions(+)
create mode 100644 dts/upstream/src/arm64/rockchip/rk3568-easepi-r1.dts
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3568-easepi-r1.dts
@@ -0,0 +1,623 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+ model = "LinkEase EasePi R1";
+ compatible = "linkease,easepi-r1", "rockchip,rk3568";
+
+ aliases {
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ mmc0 = &sdhci;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <1800000>;
+
+ button-recovery {
+ label = "Recovery";
+ linux,code = <KEY_VENDOR>;
+ press-threshold-microvolt = <1750>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&status_led_pin>;
+
+ status_led: led-status {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ hdmi-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ dc_12v: regulator-dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc5v0_sys: regulator-vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc3v3_sys: regulator-vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_12v>;
+ };
+
+ pcie30_avdd0v9: regulator-pcie30-avdd0v9 {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ pcie30_avdd1v8: regulator-pcie30-avdd1v8 {
+ compatible = "regulator-fixed";
+ regulator-name = "pcie30_avdd1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ regulator-vdd0v95-25glan {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vdd0v95_25glan_en>;
+ regulator-name = "vdd0v95_25glan";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <950000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc3v3_nvme: regulator-vcc3v3-nvme {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc3v3_nvme_en>;
+ regulator-name = "vcc3v3_nvme";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&dc_12v>;
+ };
+
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&combphy2 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gmac0 {
+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
+ assigned-clock-rates = <0>, <125000000>;
+ phy-handle = <&rgmii_phy0>;
+ phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac0_miim
+ &gmac0_tx_bus2
+ &gmac0_rx_bus2
+ &gmac0_rgmii_clk
+ &gmac0_rgmii_bus>;
+ status = "okay";
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
+ assigned-clock-rates = <0>, <125000000>;
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii-id";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m1_miim
+ &gmac1m1_tx_bus2
+ &gmac1m1_rx_bus2
+ &gmac1m1_rgmii_clk
+ &gmac1m1_rgmii_bus>;
+ status = "okay";
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ avdd-0v9-supply = <&vdda0v9_image>;
+ avdd-1v8-supply = <&vcca1v8_image>;
+ status = "okay";
+};
+
+&hdmi_in {
+ hdmi_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi>;
+ };
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>;
+ system-power-controller;
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+ wakeup-source;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-min-microvolt = <950000>;
+ regulator-max-microvolt = <950000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2s0_8ch {
+ status = "okay";
+};
+
+&mdio0 {
+ rgmii_phy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ pinctrl-0 = <&eth_phy0_reset_pin>;
+ pinctrl-names = "default";
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ pinctrl-0 = <&eth_phy1_reset_pin>;
+ pinctrl-names = "default";
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
+ };
+};
+
+/* ETH3 */
+&pcie2x1 {
+ reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_sys>;
+ status = "okay";
+};
+
+&pcie30phy {
+ data-lanes = <1 2>;
+ status = "okay";
+};
+
+/* ETH2 */
+&pcie3x1 {
+ num-lanes = <1>;
+ reset-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_sys>;
+ status = "okay";
+};
+
+/* M.2 Key for 2280 NVMe */
+&pcie3x2 {
+ num-lanes = <1>;
+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_nvme>;
+ status = "okay";
+};
+
+&pinctrl {
+ gmac0 {
+ eth_phy0_reset_pin: eth-phy0-reset-pin {
+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ gmac1 {
+ eth_phy1_reset_pin: eth-phy1-reset-pin {
+ rockchip,pins = <2 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ gpio-leds {
+ status_led_pin: status-led-pin {
+ rockchip,pins = <2 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ nvme {
+ vcc3v3_nvme_en: vcc3v3-nvme-en {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie-nic {
+ vdd0v95_25glan_en: vdd0v95-25glan-en {
+ rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic-int {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+/* OTG Only USB2.0, Only device mode */
+&usb_host0_xhci {
+ dr_mode = "peripheral";
+ extcon = <&usb2phy0>;
+ maximum-speed = "high-speed";
+ phys = <&usb2phy0_otg>;
+ phy-names = "usb2-phy";
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_sys>;
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ status = "okay";
+};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi_in_vp0>;
+ };
+};

0
package/boot/uboot-rockchip/patches/105-2-board-rockchip-add-LinkEase-EasePi-R1.patch → package/boot/uboot-rockchip/patches/105-board-rockchip-add-LinkEase-EasePi-R1.patch
View file

768
package/boot/uboot-rockchip/patches/106-board-rockchip-add-HINLINK-H66K-H68K.patch
View file

@ -206,771 +206,3 @@ Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_USB_FUNCTION_ROCKUSB=y
+CONFIG_ERRNO_STR=y
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3568-hinlink-h66k.dts
@@ -0,0 +1,10 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3568-hinlink-opc.dtsi"
+
+/ {
+ model = "HINLINK H66K";
+ compatible = "hinlink,h66k", "rockchip,rk3568";
+};
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3568-hinlink-h68k.dts
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3568-hinlink-opc.dtsi"
+
+/ {
+ model = "HINLINK H68K";
+ compatible = "hinlink,h68k", "rockchip,rk3568";
+
+ aliases {
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ };
+};
+
+&gmac0 {
+ assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+ assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
+ assigned-clock-rates = <0>, <125000000>;
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy0>;
+ phy-mode = "rgmii-id";
+ phy-supply = <&vcc3v3_sys>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac0_miim
+ &gmac0_tx_bus2
+ &gmac0_rx_bus2
+ &gmac0_rgmii_clk
+ &gmac0_rgmii_bus
+ &gmac0_rstn>;
+ status = "okay";
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
+ assigned-clock-rates = <0>, <125000000>;
+ clock_in_out = "output";
+ phy-handle = <&rgmii_phy1>;
+ phy-mode = "rgmii-id";
+ phy-supply = <&vcc3v3_sys>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m1_miim
+ &gmac1m1_tx_bus2
+ &gmac1m1_rx_bus2
+ &gmac1m1_rgmii_clk
+ &gmac1m1_rgmii_bus
+ &gmac1_rstn>;
+ status = "okay";
+};
+
+&mdio0 {
+ rgmii_phy0: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ reset-assert-us = <20000>;
+ reset-deassert-us = <100000>;
+ reset-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&pinctrl {
+ gmac {
+ gmac0_rstn: gmac0-rstn {
+ rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ gmac1_rstn: gmac1-rstn {
+ rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
--- /dev/null
+++ b/dts/upstream/src/arm64/rockchip/rk3568-hinlink-opc.dtsi
@@ -0,0 +1,666 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+ aliases {
+ mmc0 = &sdhci;
+ mmc1 = &sdmmc0;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ hdmi-con {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
+ ir-receiver {
+ compatible = "gpio-ir-receiver";
+ gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm3_ir_m0>;
+ };
+
+ keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&factory>;
+
+ button-factory {
+ label = "factory";
+ linux,code = <KEY_RESTART>;
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
+ debounce-interval = <50>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&green_led>, <&red_led>, <&work_led>;
+
+ led-0 {
+ color = <LED_COLOR_ID_BLUE>;
+ function = LED_FUNCTION_WAN;
+ gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "netdev";
+ };
+
+ led-1 {
+ color = <LED_COLOR_ID_AMBER>;
+ function = LED_FUNCTION_DISK;
+ gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
+ };
+
+ led-2 {
+ color = <LED_COLOR_ID_GREEN>;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+ };
+
+ vcc0v9_2g5: regulator-0v9-vcc-2g5 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc0v9_2g5";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc12v_dcinp: regulator-12v-vcc-dcinp {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcinp";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ vcc3v3_pi6c_05: regulator-3v3-vcc-pi6c-05 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lan_power_en>;
+ regulator-name = "vcc3v3_pi6c_05";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc3v3_sd: regulator-3v3-vcc-sd {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sd_pwren>;
+ regulator-name = "vcc3v3_sd";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc3v3_sys>;
+ };
+
+ vcc3v3_sys: regulator-3v3-vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_sys: regulator-5v0-vcc-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcinp>;
+ };
+
+ vcc5v0_usb30_otg0: regulator-5v0-vcc-usb30-otg0 {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&usb_power_en>;
+ regulator-name = "vcc5v0_usb30_otg0";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&combphy0 {
+ status = "okay";
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&combphy2 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gpu {
+ mali-supply = <&vdd_gpu>;
+ status = "okay";
+};
+
+&hdmi {
+ avdd-0v9-supply = <&vdda0v9_image>;
+ avdd-1v8-supply = <&vcca1v8_image>;
+ status = "okay";
+};
+
+&hdmi_in {
+ hdmi_in_vp0: endpoint {
+ remote-endpoint = <&vp0_out_hdmi>;
+ };
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
+&hdmi_sound {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ #clock-cells = <1>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>;
+ system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-initial-mode = <0x2>;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-always-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3: SWITCH_REG2 {
+ regulator-name = "vcc3v3";
+ regulator-always-on;
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+ };
+ };
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2m1_xfer>;
+ status = "okay";
+};
+
+&i2s0_8ch {
+ status = "okay";
+};
+
+&pcie2x1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_perstn>;
+ reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pi6c_05>;
+ status = "okay";
+};
+
+&pcie30phy {
+ data-lanes = <1 2>;
+ status = "okay";
+};
+
+&pcie3x1 {
+ num-lanes = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lan_resetb>;
+ reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pi6c_05>;
+ status = "okay";
+};
+
+&pcie3x2 {
+ num-lanes = <1>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&lan_reseta>;
+ reset-gpios = <&gpio2 RK_PD0 GPIO_ACTIVE_HIGH>;
+ vpcie3v3-supply = <&vcc3v3_pi6c_05>;
+ status = "okay";
+};
+
+&pinctrl {
+ keys {
+ factory: factory {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ leds {
+ green_led: green-led {
+ rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ red_led: red-led {
+ rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ work_led: work-led {
+ rockchip,pins = <3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ ir {
+ pwm3_ir_m0: pwm3-ir-m0 {
+ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ mmc {
+ sd_pwren: sd-pwren {
+ rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pcie {
+ lan_power_en: lan-power-en {
+ rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ lan_reseta: lan-reseta {
+ rockchip,pins = <2 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ lan_resetb: lan-resetb {
+ rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ wifi_perstn: wifi-perstn {
+ rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic-int {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ usb {
+ usb_power_en: usb-power-en {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio2-supply = <&vcc_1v8>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+&pwm0 {
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
+/* Via Type-C adapter */
+&sata0 {
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ max-frequency = <200000000>;
+ mmc-hs200-1_8v;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ sd-uhs-sdr50;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&tsadc {
+ rockchip,hw-tshut-mode = <1>;
+ rockchip,hw-tshut-polarity = <0>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
+
+&usb_host1_ehci {
+ status = "okay";
+};
+
+&usb_host1_ohci {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_usb30_otg0>;
+ status = "okay";
+};
+
+&usb2phy1 {
+ status = "okay";
+};
+
+&usb2phy1_host {
+ phy-supply = <&vcc5v0_usb30_otg0>;
+ status = "okay";
+};
+
+&usb2phy1_otg {
+ phy-supply = <&vcc5v0_usb30_otg0>;
+ status = "okay";
+};
+
+&vop {
+ assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+ status = "okay";
+};
+
+&vop_mmu {
+ status = "okay";
+};
+
+&vp0 {
+ vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+ reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+ remote-endpoint = <&hdmi_in_vp0>;
+ };
+};

8
package/boot/uboot-rockchip/patches/108-01-rockchip-mkimage-Split-size_and_off-and-size_and_nim.patch
View file

@ -60,7 +60,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
uint32_t boot_flag;
uint8_t reserved1[104];
struct image_entry images[4];
@@ -350,17 +352,18 @@ static void rkcommon_set_header0_v2(void
@@ -351,17 +353,18 @@ static void rkcommon_set_header0_v2(void
printf("Image Type: Rockchip %s boot image\n",
rkcommon_get_spl_hdr(params));
memset(buf, '\0', RK_INIT_OFFSET * RK_BLK_SIZE);
@ -83,7 +83,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
hdr->images[i].address = 0xFFFFFFFF;
hdr->images[i].counter = cpu_to_le32(i + 1);
image_ptr = buf + sector_offset * RK_BLK_SIZE;
@@ -369,6 +372,8 @@ static void rkcommon_set_header0_v2(void
@@ -370,6 +373,8 @@ static void rkcommon_set_header0_v2(void
sector_offset = sector_offset + image_sector_count;
}
@ -92,7 +92,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
do_sha256_hash(buf, (void *)hdr->hash - buf, hdr->hash);
}
@@ -515,10 +520,8 @@ void rkcommon_print_header(const void *b
@@ -516,10 +521,8 @@ void rkcommon_print_header(const void *b
return;
}
@ -105,7 +105,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
} else {
ret = rkcommon_parse_header(buf, &header0, &spl_info);
@@ -532,8 +535,9 @@ void rkcommon_print_header(const void *b
@@ -533,8 +536,9 @@ void rkcommon_print_header(const void *b
}
image_type = ret;

8
package/boot/uboot-rockchip/patches/108-02-rockchip-mkimage-Print-image-information-for-all-emb.patch
View file

@ -32,7 +32,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -349,8 +349,6 @@ static void rkcommon_set_header0_v2(void
@@ -350,8 +350,6 @@ static void rkcommon_set_header0_v2(void
uint8_t *image_ptr = NULL;
int i;
@ -41,7 +41,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
memset(buf, '\0', RK_INIT_OFFSET * RK_BLK_SIZE);
hdr->magic = cpu_to_le32(RK_MAGIC_V2);
hdr->boot_flag = cpu_to_le32(HASH_SHA256);
@@ -504,6 +502,29 @@ int rkcommon_verify_header(unsigned char
@@ -505,6 +503,29 @@ int rkcommon_verify_header(unsigned char
return -ENOENT;
}
@ -71,7 +71,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
void rkcommon_print_header(const void *buf, struct image_tool_params *params)
{
struct header0_info header0;
@@ -520,8 +541,7 @@ void rkcommon_print_header(const void *b
@@ -521,8 +542,7 @@ void rkcommon_print_header(const void *b
return;
}
@ -81,7 +81,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
} else {
ret = rkcommon_parse_header(buf, &header0, &spl_info);
@@ -539,15 +559,16 @@ void rkcommon_print_header(const void *b
@@ -540,15 +560,16 @@ void rkcommon_print_header(const void *b
boot_size = le16_to_cpu(header0.init_boot_size) * RK_BLK_SIZE -
init_size;

2
package/boot/uboot-rockchip/patches/108-03-rockchip-mkimage-Print-boot0-and-boot1-parameters.patch
View file

@ -47,7 +47,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
struct image_entry images[4];
uint8_t reserved2[1064];
uint8_t hash[512];
@@ -509,6 +513,18 @@ static void rkcommon_print_header_v2(con
@@ -510,6 +514,18 @@ static void rkcommon_print_header_v2(con
printf("Rockchip Boot Image (v2)\n");

20
package/boot/uboot-rockchip/patches/108-04-rockchip-mkimage-Add-option-to-change-image-offset-a.patch
View file

@ -27,7 +27,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
};
static struct spl_info spl_infos[] = {
@@ -199,14 +200,19 @@ static struct spl_info *rkcommon_get_spl
@@ -200,14 +201,19 @@ static struct spl_info *rkcommon_get_spl
return NULL;
}
@ -53,7 +53,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
/*
* Pad to a 2KB alignment, as required for init/boot size by the ROM
@@ -215,6 +221,27 @@ static int rkcommon_get_aligned_size(str
@@ -216,6 +222,27 @@ static int rkcommon_get_aligned_size(str
return ROUND(size, RK_SIZE_ALIGN);
}
@ -81,7 +81,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
int rkcommon_check_params(struct image_tool_params *params)
{
int i, size;
@@ -237,14 +264,14 @@ int rkcommon_check_params(struct image_t
@@ -238,14 +265,14 @@ int rkcommon_check_params(struct image_t
spl_params.boot_file += 1;
}
@ -98,7 +98,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
if (size < 0)
return EXIT_FAILURE;
spl_params.boot_size = size;
@@ -301,13 +328,6 @@ bool rkcommon_need_rc4_spl(struct image_
@@ -302,13 +329,6 @@ bool rkcommon_need_rc4_spl(struct image_
return info->spl_rc4;
}
@ -112,7 +112,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
static void do_sha256_hash(uint8_t *buf, uint32_t size, uint8_t *out)
{
sha256_context ctx;
@@ -320,12 +340,13 @@ static void do_sha256_hash(uint8_t *buf,
@@ -321,12 +341,13 @@ static void do_sha256_hash(uint8_t *buf,
static void rkcommon_set_header0(void *buf, struct image_tool_params *params)
{
struct header0_info *hdr = buf;
@ -129,7 +129,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
hdr->init_size = cpu_to_le16(spl_params.init_size / RK_BLK_SIZE);
/*
@@ -353,10 +374,10 @@ static void rkcommon_set_header0_v2(void
@@ -354,10 +375,10 @@ static void rkcommon_set_header0_v2(void
uint8_t *image_ptr = NULL;
int i;
@ -142,7 +142,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
image_size_array[0] = spl_params.init_size;
image_size_array[1] = spl_params.boot_size;
@@ -382,11 +403,12 @@ static void rkcommon_set_header0_v2(void
@@ -383,11 +404,12 @@ static void rkcommon_set_header0_v2(void
void rkcommon_set_header(void *buf, struct stat *sbuf, int ifd,
struct image_tool_params *params)
{
@ -157,7 +157,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
rkcommon_set_header0(buf, params);
/* Set up the SPL name (i.e. copy spl_hdr over) */
@@ -394,12 +416,12 @@ void rkcommon_set_header(void *buf, str
@@ -395,12 +417,12 @@ void rkcommon_set_header(void *buf, str
memcpy(&hdr->magic, rkcommon_get_spl_hdr(params), RK_SPL_HDR_SIZE);
if (rkcommon_need_rc4_spl(params))
@ -172,7 +172,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
spl_params.init_size,
spl_params.boot_size);
}
@@ -624,7 +646,7 @@ int rkcommon_vrec_header(struct image_to
@@ -625,7 +647,7 @@ int rkcommon_vrec_header(struct image_to
* 4 bytes of these images can safely be overwritten using the
* boot magic.
*/
@ -181,7 +181,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
/* Allocate, clear and install the header */
tparams->hdr = malloc(tparams->header_size);
@@ -642,7 +664,8 @@ int rkcommon_vrec_header(struct image_to
@@ -643,7 +665,8 @@ int rkcommon_vrec_header(struct image_to
params->orig_file_size = tparams->header_size +
spl_params.init_size + spl_params.boot_size;

18
package/boot/uboot-rockchip/patches/108-05-rockchip-mkimage-Add-support-for-up-to-4-input-files.patch
View file

@ -17,7 +17,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -166,17 +166,15 @@ static struct spl_info spl_infos[] = {
@@ -167,17 +167,15 @@ static struct spl_info spl_infos[] = {
/**
* struct spl_params - spl params parsed in check_params()
*
@ -41,7 +41,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
};
static struct spl_params spl_params = { 0 };
@@ -256,31 +254,32 @@ int rkcommon_check_params(struct image_t
@@ -257,31 +255,32 @@ int rkcommon_check_params(struct image_t
if (!rkcommon_get_spl_info(params->imagename))
goto err_spl_info;
@ -89,7 +89,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
return EXIT_FAILURE;
}
@@ -347,7 +346,7 @@ static void rkcommon_set_header0(void *b
@@ -348,7 +347,7 @@ static void rkcommon_set_header0(void *b
hdr->magic = cpu_to_le32(RK_MAGIC);
hdr->disable_rc4 = cpu_to_le32(!rkcommon_need_rc4_spl(params));
hdr->init_offset = cpu_to_le16(init_offset);
@ -98,7 +98,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
/*
* init_boot_size needs to be set, as it is read by the BootROM
@@ -357,10 +356,11 @@ static void rkcommon_set_header0(void *b
@@ -358,10 +357,11 @@ static void rkcommon_set_header0(void *b
* see https://lists.denx.de/pipermail/u-boot/2017-May/293267.html
* for a more detailed explanation by Andy Yan
*/
@ -113,7 +113,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
hdr->init_boot_size = cpu_to_le16(init_boot_size / RK_BLK_SIZE);
rc4_encode(buf, RK_BLK_SIZE, rc4_key);
@@ -370,7 +370,6 @@ static void rkcommon_set_header0_v2(void
@@ -371,7 +371,6 @@ static void rkcommon_set_header0_v2(void
{
struct header0_info_v2 *hdr = buf;
uint32_t sector_offset, image_sector_count;
@ -121,7 +121,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
uint8_t *image_ptr = NULL;
int i;
@@ -378,19 +377,17 @@ static void rkcommon_set_header0_v2(void
@@ -379,19 +378,17 @@ static void rkcommon_set_header0_v2(void
memset(buf, '\0', sector_offset * RK_BLK_SIZE);
hdr->magic = cpu_to_le32(RK_MAGIC_V2);
hdr->boot_flag = cpu_to_le32(HASH_SHA256);
@ -145,7 +145,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
hdr->images[i].hash);
sector_offset = sector_offset + image_sector_count;
}
@@ -417,13 +414,13 @@ void rkcommon_set_header(void *buf, str
@@ -418,13 +415,13 @@ void rkcommon_set_header(void *buf, str
if (rkcommon_need_rc4_spl(params))
rkcommon_rc4_encode_spl(buf, header_size,
@ -163,7 +163,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
}
}
}
@@ -661,8 +658,9 @@ int rkcommon_vrec_header(struct image_to
@@ -662,8 +659,9 @@ int rkcommon_vrec_header(struct image_to
* We need to store the original file-size (i.e. before padding), as
* imagetool does not set this during its adjustment of file_size.
*/
@ -175,7 +175,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
params->file_size = rkcommon_get_aligned_size(params,
params->orig_file_size);
@@ -749,16 +747,13 @@ err_close:
@@ -750,16 +748,13 @@ err_close:
int rockchip_copy_image(int ifd, struct image_tool_params *params)
{

4
package/boot/uboot-rockchip/patches/108-06-rockchip-mkimage-Add-option-for-image-load-address-a.patch
View file

@ -18,7 +18,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -168,12 +168,16 @@ static struct spl_info spl_infos[] = {
@@ -169,12 +169,16 @@ static struct spl_info spl_infos[] = {
*
* @file: image file path
* @size: aligned size of image in bytes
@ -35,7 +35,7 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
} images[4];
};
@@ -384,7 +388,8 @@ static void rkcommon_set_header0_v2(void
@@ -385,7 +389,8 @@ static void rkcommon_set_header0_v2(void
image_sector_count = spl_params.images[i].size / RK_BLK_SIZE;
hdr->images[i].offset = cpu_to_le16(sector_offset);
hdr->images[i].size = cpu_to_le16(image_sector_count);

10
package/boot/uboot-rockchip/patches/108-07-WIP-rockchip-mkimage-Add-rk3576-align-and-sd-card-wo.patch
View file

@ -72,16 +72,16 @@ Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+*/
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -159,7 +159,7 @@ static struct spl_info spl_infos[] = {
{ "rv1126", "110B", 0x10000 - 0x1000, false, RK_HEADER_V1 },
@@ -158,7 +158,7 @@ static struct spl_info spl_infos[] = {
{ "rk3506", "RK35", 0xC000 - 0x1000, false, RK_HEADER_V2 },
{ "rk3528", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 },
{ "rk3568", "RK35", 0x10000 - 0x1000, false, RK_HEADER_V2 },
- { "rk3576", "RK35", 0x80000 - 0x1000, false, RK_HEADER_V2 },
+ { "rk3576", "RK35", 0x80000 - 0x1000, false, RK_HEADER_V2, 8 },
{ "rk3588", "RK35", 0x100000 - 0x1000, false, RK_HEADER_V2 },
};
@@ -287,6 +287,22 @@ int rkcommon_check_params(struct image_t
{ "rv1108", "RK11", 0x1800, false, RK_HEADER_V1 },
{ "rv1126", "110B", 0x10000 - 0x1000, false, RK_HEADER_V1 },
@@ -288,6 +288,22 @@ int rkcommon_check_params(struct image_t
return EXIT_FAILURE;
}