6e1fdb9ea1
Commit ce120be361 ("kernel: disable qualcomm crypto") dropped the
CRYPTO_DEV_QCE kernel configs, so crypto@73a000 and its BAM no longer
have a driver. Unlike ipq8074, mainline ipq9574.dtsi ships both nodes
enabled by default, and gcc-ipq9574 registers its interconnect provider
with icc_sync_state; an enabled consumer that can never probe defers
that callback forever, so every boot logs
sync_state() pending due to 73a000.crypto
and the interconnect bandwidth votes are never allowed to drop from
their boot-time maximum. Disable both nodes explicitly in the board
device tree.
Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de>
Link: https://github.com/openwrt/openwrt/pull/24379
Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
464 lines
8.6 KiB
Text
464 lines
8.6 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "ipq9574.dtsi"
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/ {
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model = "8devices Kiwi-DVK";
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compatible = "8devices,kiwi-dvk", "qcom,ipq9574";
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aliases {
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serial0 = &blsp1_uart2;
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ethernet0 = &xgmac1;
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ethernet1 = &xgmac5;
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ethernet2 = &xgmac6;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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regulator_fixed_3p3: s3300 {
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compatible = "regulator-fixed";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-name = "fixed_3p3";
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};
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regulator_fixed_0p925: s0925 {
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compatible = "regulator-fixed";
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regulator-min-microvolt = <925000>;
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regulator-max-microvolt = <925000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-name = "fixed_0p925";
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};
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sfp0: sfp-0 {
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compatible = "sff,sfp";
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pinctrl-0 = <&sfp0_default>;
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pinctrl-names = "default";
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i2c-bus = <&blsp1_i2c1>;
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los-gpios = <&tlmm 46 GPIO_ACTIVE_HIGH>;
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tx-disable-gpios = <&tlmm 47 GPIO_ACTIVE_HIGH>;
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};
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};
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&blsp1_i2c1 {
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pinctrl-0 = <&i2c1_default>;
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pinctrl-names = "default";
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status = "okay";
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};
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&blsp1_spi0 {
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pinctrl-0 = <&spi_0_default>;
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pinctrl-names = "default";
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <50000000>;
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};
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};
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&blsp1_uart2 {
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pinctrl-0 = <&uart2_pins>;
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pinctrl-names = "default";
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status = "okay";
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};
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&crypto {
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status = "disabled";
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};
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&cryptobam {
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status = "disabled";
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};
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&qcom_ppe {
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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xgmac1: port@1 {
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reg = <1>;
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phy-mode = "10gbase-r";
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managed = "in-band-status";
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label = "wan";
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sfp = <&sfp0>;
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pcs-handle = <&pcs0_ch0>;
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local-mac-address = [00 00 00 00 00 00];
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clocks = <&nsscc NSS_CC_PORT1_MAC_CLK>,
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<&nsscc NSS_CC_PORT1_RX_CLK>,
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<&nsscc NSS_CC_PORT1_TX_CLK>;
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clock-names = "mac",
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"rx",
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"tx";
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resets = <&nsscc PORT1_MAC_ARES>,
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<&nsscc PORT1_RX_ARES>,
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<&nsscc PORT1_TX_ARES>;
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reset-names = "mac",
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"rx",
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"tx";
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};
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xgmac5: port@5 {
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reg = <5>;
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phy-mode = "2500base-x";
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label = "lan1";
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phy-handle = <&phy0>;
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pcs-handle = <&pcs1_ch0>;
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local-mac-address = [00 00 00 00 00 00];
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clocks = <&nsscc NSS_CC_PORT5_MAC_CLK>,
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<&nsscc NSS_CC_PORT5_RX_CLK>,
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<&nsscc NSS_CC_PORT5_TX_CLK>;
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clock-names = "mac",
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"rx",
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"tx";
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resets = <&nsscc PORT5_MAC_ARES>,
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<&nsscc PORT5_RX_ARES>,
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<&nsscc PORT5_TX_ARES>;
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reset-names = "mac",
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"rx",
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"tx";
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};
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xgmac6: port@6 {
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reg = <6>;
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phy-mode = "usxgmii";
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managed = "in-band-status";
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label = "lan2";
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phy-handle = <&phy1>;
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pcs-handle = <&pcs2_ch0>;
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local-mac-address = [00 00 00 00 00 00];
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clocks = <&nsscc NSS_CC_PORT6_MAC_CLK>,
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<&nsscc NSS_CC_PORT6_RX_CLK>,
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<&nsscc NSS_CC_PORT6_TX_CLK>;
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clock-names = "mac",
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"rx",
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"tx";
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resets = <&nsscc PORT6_MAC_ARES>,
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<&nsscc PORT6_RX_ARES>,
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<&nsscc PORT6_TX_ARES>;
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reset-names = "mac",
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"rx",
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"tx";
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};
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};
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};
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&mdio {
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status = "okay";
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pinctrl-0 = <&mdio_pins>;
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pinctrl-names = "default";
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phy0: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <1>;
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reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
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};
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phy1: ethernet-phy@28 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <28>;
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reset-assert-us = <40>;
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reset-deassert-us = <150000>;
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reset-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
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};
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};
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&pcie0 {
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pinctrl-0 = <&pcie0_default>;
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pinctrl-names = "default";
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perst-gpios = <&tlmm 23 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 24 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&pcie0_phy {
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status = "okay";
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};
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&pcie1 {
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pinctrl-0 = <&pcie1_default>;
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pinctrl-names = "default";
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perst-gpios = <&tlmm 26 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 27 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&pcie1_phy {
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status = "okay";
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};
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&pcie2 {
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pinctrl-0 = <&pcie2_default>;
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pinctrl-names = "default";
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perst-gpios = <&tlmm 29 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 30 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&pcie2_phy {
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status = "okay";
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};
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&pcie3 {
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pinctrl-0 = <&pcie3_default>;
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pinctrl-names = "default";
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perst-gpios = <&tlmm 32 GPIO_ACTIVE_LOW>;
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wake-gpios = <&tlmm 33 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&pcie3_phy {
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status = "okay";
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};
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&rpm_requests {
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regulators {
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compatible = "qcom,rpm-mp5496-regulators";
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ipq9574_s1: s1 {
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/*
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* During kernel bootup, the SoC runs at 800MHz with 875mV set by the bootloaders.
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* During regulator registration, kernel not knowing the initial voltage,
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* considers it as zero and brings up the regulators with minimum supported voltage.
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* Update the regulator-min-microvolt with SVS voltage of 725mV so that
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* the regulators are brought up with 725mV which is sufficient for all the
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* corner parts to operate at 800MHz
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*/
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regulator-min-microvolt = <725000>;
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regulator-max-microvolt = <1075000>;
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};
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mp5496_l5: l5 {
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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regulator-always-on;
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regulator-boot-on;
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};
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};
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};
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&sdhc_1 {
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bus-width = <8>;
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max-frequency = <384000000>;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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mmc-hs400-1_8v;
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mmc-hs400-enhanced-strobe;
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pinctrl-0 = <&sdc_default_state>;
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pinctrl-names = "default";
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status = "okay";
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};
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&sleep_clk {
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clock-frequency = <32000>;
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};
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&tlmm {
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sdc_default_state: sdc-default-state {
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clk-pins {
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pins = "gpio5";
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function = "sdc_clk";
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drive-strength = <8>;
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bias-disable;
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};
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cmd-pins {
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pins = "gpio4";
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function = "sdc_cmd";
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drive-strength = <8>;
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bias-pull-up;
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};
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data-pins {
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pins = "gpio0", "gpio1", "gpio2",
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"gpio3", "gpio6", "gpio7",
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"gpio8", "gpio9";
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function = "sdc_data";
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drive-strength = <8>;
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bias-pull-up;
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};
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rclk-pins {
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pins = "gpio10";
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function = "sdc_rclk";
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drive-strength = <8>;
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bias-pull-down;
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};
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};
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spi_0_default: spi-0-default-state {
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pins = "gpio11", "gpio12", "gpio13", "gpio14";
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function = "blsp0_spi";
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drive-strength = <8>;
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bias-disable;
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};
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pcie0_default: pcie0-default-state {
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clkreq-n-pins {
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pins = "gpio22";
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function = "pcie0_clk";
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drive-strength = <6>;
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bias-pull-up;
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};
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perst-n-pins {
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pins = "gpio23";
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function = "gpio";
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drive-strength = <8>;
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bias-pull-down;
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output-low;
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};
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wake-n-pins {
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pins = "gpio24";
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function = "pcie0_wake";
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drive-strength = <6>;
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bias-pull-up;
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};
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};
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pcie1_default: pcie1-default-state {
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clkreq-n-pins {
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pins = "gpio25";
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function = "pcie1_clk";
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drive-strength = <6>;
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bias-pull-up;
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};
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perst-n-pins {
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pins = "gpio26";
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function = "gpio";
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drive-strength = <8>;
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bias-pull-down;
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output-low;
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};
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wake-n-pins {
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pins = "gpio27";
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function = "pcie1_wake";
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drive-strength = <6>;
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bias-pull-up;
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};
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};
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pcie2_default: pcie2-default-state {
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clkreq-n-pins {
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pins = "gpio28";
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function = "pcie2_clk";
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drive-strength = <6>;
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bias-pull-up;
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};
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perst-n-pins {
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pins = "gpio29";
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function = "gpio";
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drive-strength = <8>;
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bias-pull-down;
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output-low;
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};
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wake-n-pins {
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pins = "gpio30";
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function = "pcie2_wake";
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drive-strength = <6>;
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bias-pull-up;
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};
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};
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pcie3_default: pcie3-default-state {
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clkreq-n-pins {
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pins = "gpio31";
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function = "pcie3_clk";
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drive-strength = <6>;
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bias-pull-up;
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};
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perst-n-pins {
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pins = "gpio32";
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function = "gpio";
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drive-strength = <8>;
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bias-pull-up;
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output-low;
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};
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wake-n-pins {
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pins = "gpio33";
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function = "pcie3_wake";
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drive-strength = <6>;
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bias-pull-up;
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};
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};
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i2c1_default: i2c1-default-state {
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pins = "gpio36", "gpio37";
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function = "blsp1_i2c";
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drive-strength = <8>;
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bias-pull-up;
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};
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sfp0_default: sfp0-default-state {
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pins = "gpio46", "gpio47";
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function = "gpio";
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drive-strength = <8>;
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bias-pull-down;
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};
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};
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&usb_0_dwc3 {
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dr_mode = "host";
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};
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&usb_0_qmpphy {
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vdda-pll-supply = <&mp5496_l5>;
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vdda-phy-supply = <®ulator_fixed_0p925>;
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status = "okay";
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};
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&usb_0_qusbphy {
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vdd-supply = <®ulator_fixed_0p925>;
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vdda-pll-supply = <&mp5496_l5>;
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vdda-phy-dpdm-supply = <®ulator_fixed_3p3>;
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status = "okay";
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};
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&usb3 {
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status = "okay";
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};
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/*
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* The bootstrap pins for the board select the XO clock frequency,
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* which automatically enables the right dividers to ensure the
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* reference clock output from WiFi is 48 MHZ.
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*/
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&ref_48mhz_clk {
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clock-div = <1>;
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clock-mult = <1>;
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};
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/*
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* The frequency of xo_board_clk is fixed to 24 MHZ, which is routed
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* from WiFi output clock 48 MHZ divided by 2.
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*/
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&xo_board_clk {
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clock-div = <2>;
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clock-mult = <1>;
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};
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&xo_clk {
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clock-frequency = <48000000>;
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};
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