9f2dec7ef9
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de> Link: https://github.com/openwrt/openwrt/pull/24031 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
240 lines
5.2 KiB
Diff
240 lines
5.2 KiB
Diff
From 450a80623e3b8bb5dae59e0d56046fc3d0a88f3b Mon Sep 17 00:00:00 2001
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From: Sricharan Ramabadhran <quic_srichara@quicinc.com>
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Date: Thu, 12 Jun 2025 10:46:14 +0400
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Subject: arm64: dts: qcom: ipq5018: Add tsens node
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IPQ5018 has tsens V1.0 IP with 5 sensors, though 4 are in use.
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There is no RPM, so tsens has to be manually enabled. Adding the tsens
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and nvmem nodes and adding 4 thermal sensors (zones). The critical trip
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temperature is set to 120'C with an action to reboot.
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In addition, adding a cooling device to the CPU thermal zone which uses
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CPU frequency scaling.
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Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
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[bjorn: Added tsens-v1 fallback compatible, per binding]
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Link: https://lore.kernel.org/r/20250612-ipq5018-tsens-v13-2-a210f3683240@outlook.com
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---
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arch/arm64/boot/dts/qcom/ipq5018.dtsi | 178 ++++++++++++++++++++++++++++++++++
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1 file changed, 178 insertions(+)
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(limited to 'arch/arm64/boot/dts/qcom/ipq5018.dtsi')
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--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@@ -9,6 +9,7 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
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#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
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+#include <dt-bindings/thermal/thermal.h>
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/ {
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interrupt-parent = <&intc>;
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@@ -39,6 +40,7 @@
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next-level-cache = <&l2_0>;
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clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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operating-points-v2 = <&cpu_opp_table>;
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+ #cooling-cells = <2>;
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};
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cpu1: cpu@1 {
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@@ -49,6 +51,7 @@
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next-level-cache = <&l2_0>;
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clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>;
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operating-points-v2 = <&cpu_opp_table>;
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+ #cooling-cells = <2>;
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};
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l2_0: l2-cache {
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@@ -182,6 +185,117 @@
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status = "disabled";
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};
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+ qfprom: qfprom@a0000 {
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+ compatible = "qcom,ipq5018-qfprom", "qcom,qfprom";
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+ reg = <0x000a0000 0x1000>;
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+
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+ tsens_mode: mode@249 {
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+ reg = <0x249 0x1>;
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+ bits = <0 3>;
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+ };
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+
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+ tsens_base1: base1@249 {
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+ reg = <0x249 0x2>;
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+ bits = <3 8>;
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+ };
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+
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+ tsens_base2: base2@24a {
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+ reg = <0x24a 0x2>;
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+ bits = <3 8>;
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+ };
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+
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+ tsens_s0_p1: s0-p1@24b {
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+ reg = <0x24b 0x2>;
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+ bits = <2 6>;
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+ };
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+
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+ tsens_s0_p2: s0-p2@24c {
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+ reg = <0x24c 0x1>;
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+ bits = <1 6>;
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+ };
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+
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+ tsens_s1_p1: s1-p1@24c {
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+ reg = <0x24c 0x2>;
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+ bits = <7 6>;
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+ };
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+
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+ tsens_s1_p2: s1-p2@24d {
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+ reg = <0x24d 0x2>;
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+ bits = <5 6>;
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+ };
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+
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+ tsens_s2_p1: s2-p1@24e {
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+ reg = <0x24e 0x2>;
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+ bits = <3 6>;
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+ };
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+
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+ tsens_s2_p2: s2-p2@24f {
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+ reg = <0x24f 0x1>;
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+ bits = <1 6>;
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+ };
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+
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+ tsens_s3_p1: s3-p1@24f {
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+ reg = <0x24f 0x2>;
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+ bits = <7 6>;
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+ };
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+
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+ tsens_s3_p2: s3-p2@250 {
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+ reg = <0x250 0x2>;
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+ bits = <5 6>;
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+ };
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+
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+ tsens_s4_p1: s4-p1@251 {
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+ reg = <0x251 0x2>;
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+ bits = <3 6>;
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+ };
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+
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+ tsens_s4_p2: s4-p2@254 {
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+ reg = <0x254 0x1>;
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+ bits = <0 6>;
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+ };
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+ };
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+
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+ tsens: thermal-sensor@4a9000 {
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+ compatible = "qcom,ipq5018-tsens", "qcom,tsens-v1";
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+ reg = <0x004a9000 0x1000>,
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+ <0x004a8000 0x1000>;
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+
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+ nvmem-cells = <&tsens_mode>,
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+ <&tsens_base1>,
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+ <&tsens_base2>,
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+ <&tsens_s0_p1>,
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+ <&tsens_s0_p2>,
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+ <&tsens_s1_p1>,
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+ <&tsens_s1_p2>,
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+ <&tsens_s2_p1>,
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+ <&tsens_s2_p2>,
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+ <&tsens_s3_p1>,
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+ <&tsens_s3_p2>,
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+ <&tsens_s4_p1>,
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+ <&tsens_s4_p2>;
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+
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+ nvmem-cell-names = "mode",
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+ "base1",
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+ "base2",
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+ "s0_p1",
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+ "s0_p2",
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+ "s1_p1",
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+ "s1_p2",
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+ "s2_p1",
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+ "s2_p2",
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+ "s3_p1",
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+ "s3_p2",
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+ "s4_p1",
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+ "s4_p2";
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+
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+ interrupts = <GIC_SPI 184 IRQ_TYPE_EDGE_RISING>;
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+ interrupt-names = "uplow";
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+ #qcom,sensors = <5>;
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+ #thermal-sensor-cells = <1>;
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+ };
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+
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tlmm: pinctrl@1000000 {
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compatible = "qcom,ipq5018-tlmm";
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reg = <0x01000000 0x300000>;
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@@ -630,6 +744,70 @@
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};
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};
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};
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+
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+ thermal-zones {
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+ cpu-thermal {
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+ thermal-sensors = <&tsens 2>;
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+
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+ trips {
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+ cpu-critical {
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+ temperature = <120000>;
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+ hysteresis = <1000>;
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+ type = "critical";
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+ };
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+
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+ cpu_alert: cpu-passive {
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+ temperature = <100000>;
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+ hysteresis = <1000>;
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+ type = "passive";
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+ };
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+ };
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+
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+ cooling-maps {
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+ map0 {
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+ trip = <&cpu_alert>;
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+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
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+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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+ };
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+ };
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+ };
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+
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+ gephy-thermal {
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+ thermal-sensors = <&tsens 4>;
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+
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+ trips {
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+ gephy-critical {
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+ temperature = <120000>;
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+ hysteresis = <1000>;
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+ type = "critical";
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+ };
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+ };
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+ };
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+
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+ top-glue-thermal {
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+ thermal-sensors = <&tsens 3>;
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+
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+ trips {
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+ top-glue-critical {
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+ temperature = <120000>;
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+ hysteresis = <1000>;
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+ type = "critical";
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+ };
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+ };
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+ };
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+
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+ ubi32-thermal {
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+ thermal-sensors = <&tsens 1>;
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+
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+ trips {
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+ ubi32-critical {
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+ temperature = <120000>;
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+ hysteresis = <1000>;
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+ type = "critical";
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+ };
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+ };
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+ };
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+ };
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timer {
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compatible = "arm,armv8-timer";
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