9f2dec7ef9
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de> Link: https://github.com/openwrt/openwrt/pull/24031 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
243 lines
8.7 KiB
Diff
243 lines
8.7 KiB
Diff
From d46502279a11b48ede1d8bf65a229c8231bf0602 Mon Sep 17 00:00:00 2001
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From: George Moussalem <george.moussalem@outlook.com>
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Date: Fri, 13 Jun 2025 05:55:08 +0400
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Subject: net: phy: qcom: at803x: Add Qualcomm IPQ5018 Internal PHY support
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The IPQ5018 SoC contains a single internal Gigabit Ethernet PHY which
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provides an MDI interface directly to an RJ45 connector or an external
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switch over a PHY to PHY link.
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The PHY supports 10BASE-T/100BASE-TX/1000BASE-T link modes in SGMII
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interface mode, CDT, auto-negotiation and 802.3az EEE.
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Let's add support for this PHY in the at803x driver as it falls within
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the Qualcomm Atheros OUI.
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Reviewed-by: Andrew Lunn <andrew@lunn.ch>
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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Link: https://patch.msgid.link/20250613-ipq5018-ge-phy-v5-2-9af06e34ea6b@outlook.com
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/phy/qcom/at803x.c | 167 ++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 167 insertions(+)
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(limited to 'drivers/net/phy/qcom/at803x.c')
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--- a/drivers/net/phy/qcom/at803x.c
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+++ b/drivers/net/phy/qcom/at803x.c
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@@ -19,6 +19,7 @@
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#include <linux/regulator/consumer.h>
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#include <linux/of.h>
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#include <linux/phylink.h>
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+#include <linux/reset.h>
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#include <linux/sfp.h>
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#include <dt-bindings/net/qca-ar803x.h>
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@@ -93,6 +94,8 @@
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#define ATH8035_PHY_ID 0x004dd072
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#define AT8030_PHY_ID_MASK 0xffffffef
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+#define IPQ5018_PHY_ID 0x004dd0c0
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+
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#define QCA9561_PHY_ID 0x004dd042
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#define AT803X_PAGE_FIBER 0
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@@ -105,6 +108,48 @@
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/* disable hibernation mode */
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#define AT803X_DISABLE_HIBERNATION_MODE BIT(2)
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+#define IPQ5018_PHY_FIFO_CONTROL 0x19
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+#define IPQ5018_PHY_FIFO_RESET GENMASK(1, 0)
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+
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+#define IPQ5018_PHY_DEBUG_EDAC 0x4380
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+#define IPQ5018_PHY_MMD1_MDAC 0x8100
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+#define IPQ5018_PHY_DAC_MASK GENMASK(15, 8)
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+
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+/* MDAC and EDAC values for short cable length */
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+#define IPQ5018_PHY_DEBUG_EDAC_VAL 0x10
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+#define IPQ5018_PHY_MMD1_MDAC_VAL 0x10
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+
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+#define IPQ5018_PHY_MMD1_MSE_THRESH1 0x1000
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+#define IPQ5018_PHY_MMD1_MSE_THRESH2 0x1001
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+#define IPQ5018_PHY_PCS_EEE_TX_TIMER 0x8008
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+#define IPQ5018_PHY_PCS_EEE_RX_TIMER 0x8009
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+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL3 0x8074
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+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL4 0x8075
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+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL5 0x8076
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+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL6 0x8077
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+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL7 0x8078
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+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL9 0x807a
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+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL13 0x807e
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+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL14 0x807f
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+
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+#define IPQ5018_PHY_MMD1_MSE_THRESH1_VAL 0xf1
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+#define IPQ5018_PHY_MMD1_MSE_THRESH2_VAL 0x1f6
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+#define IPQ5018_PHY_PCS_EEE_TX_TIMER_VAL 0x7880
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+#define IPQ5018_PHY_PCS_EEE_RX_TIMER_VAL 0xc8
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+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL3_VAL 0xc040
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+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL4_VAL 0xa060
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+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL5_VAL 0xc040
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+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL6_VAL 0xa060
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+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL7_VAL 0xc24c
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+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL9_VAL 0xc060
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+#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL13_VAL 0xb060
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+#define IPQ5018_PHY_PCS_NEAR_ECHO_THRESH_VAL 0x90b0
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+
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+#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE 0x1
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+#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK GENMASK(7, 4)
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+#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT 0x50
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+#define IPQ5018_PHY_DEBUG_ANA_DAC_FILTER 0xa080
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+
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MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver");
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MODULE_AUTHOR("Matus Ujhelyi");
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MODULE_LICENSE("GPL");
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@@ -130,6 +175,11 @@ struct at803x_context {
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u16 led_control;
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};
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+struct ipq5018_priv {
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+ struct reset_control *rst;
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+ bool set_short_cable_dac;
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+};
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+
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static int at803x_write_page(struct phy_device *phydev, int page)
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{
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int mask;
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@@ -960,6 +1010,109 @@ static int at8035_probe(struct phy_devic
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return at8035_parse_dt(phydev);
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}
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+static int ipq5018_cable_test_start(struct phy_device *phydev)
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+{
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+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL3,
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+ IPQ5018_PHY_PCS_CDT_THRESH_CTRL3_VAL);
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+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL4,
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+ IPQ5018_PHY_PCS_CDT_THRESH_CTRL4_VAL);
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+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL5,
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+ IPQ5018_PHY_PCS_CDT_THRESH_CTRL5_VAL);
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+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL6,
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+ IPQ5018_PHY_PCS_CDT_THRESH_CTRL6_VAL);
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+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL7,
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+ IPQ5018_PHY_PCS_CDT_THRESH_CTRL7_VAL);
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+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL9,
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+ IPQ5018_PHY_PCS_CDT_THRESH_CTRL9_VAL);
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+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL13,
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+ IPQ5018_PHY_PCS_CDT_THRESH_CTRL13_VAL);
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+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL3,
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+ IPQ5018_PHY_PCS_NEAR_ECHO_THRESH_VAL);
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+
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+ /* we do all the (time consuming) work later */
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+ return 0;
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+}
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+
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+static int ipq5018_config_init(struct phy_device *phydev)
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+{
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+ struct ipq5018_priv *priv = phydev->priv;
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+ u16 val;
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+
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+ /*
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+ * set LDO efuse: first temporarily store ANA_DAC_FILTER value from
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+ * debug register as it will be reset once the ANA_LDO_EFUSE register
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+ * is written to
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+ */
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+ val = at803x_debug_reg_read(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER);
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+ at803x_debug_reg_mask(phydev, IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE,
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+ IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK,
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+ IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT);
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+ at803x_debug_reg_write(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER, val);
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+
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+ /* set 8023AZ EEE TX and RX timer values */
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+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_EEE_TX_TIMER,
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+ IPQ5018_PHY_PCS_EEE_TX_TIMER_VAL);
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+ phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_EEE_RX_TIMER,
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+ IPQ5018_PHY_PCS_EEE_RX_TIMER_VAL);
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+
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+ /* set MSE threshold values */
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+ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MSE_THRESH1,
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+ IPQ5018_PHY_MMD1_MSE_THRESH1_VAL);
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+ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MSE_THRESH2,
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+ IPQ5018_PHY_MMD1_MSE_THRESH2_VAL);
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+
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+ /* PHY DAC values are optional and only set in a PHY to PHY link architecture */
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+ if (priv->set_short_cable_dac) {
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+ /* setting MDAC (Multi-level Digital-to-Analog Converter) in MMD1 */
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+ phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MDAC,
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+ IPQ5018_PHY_DAC_MASK, IPQ5018_PHY_MMD1_MDAC_VAL);
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+
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+ /* setting EDAC (Error-detection and Correction) in debug register */
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+ at803x_debug_reg_mask(phydev, IPQ5018_PHY_DEBUG_EDAC,
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+ IPQ5018_PHY_DAC_MASK, IPQ5018_PHY_DEBUG_EDAC_VAL);
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+ }
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+
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+ return 0;
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+}
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+
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+static void ipq5018_link_change_notify(struct phy_device *phydev)
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+{
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+ /*
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+ * Reset the FIFO buffer upon link disconnects to clear any residual data
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+ * which may cause issues with the FIFO which it cannot recover from.
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+ */
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+ mdiobus_modify_changed(phydev->mdio.bus, phydev->mdio.addr,
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+ IPQ5018_PHY_FIFO_CONTROL, IPQ5018_PHY_FIFO_RESET,
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+ phydev->link ? IPQ5018_PHY_FIFO_RESET : 0);
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+}
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+
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+static int ipq5018_probe(struct phy_device *phydev)
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+{
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+ struct device *dev = &phydev->mdio.dev;
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+ struct ipq5018_priv *priv;
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+ int ret;
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+
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+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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+ if (!priv)
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+ return -ENOMEM;
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+
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+ priv->set_short_cable_dac = of_property_read_bool(dev->of_node,
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+ "qcom,dac-preset-short-cable");
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+
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+ priv->rst = devm_reset_control_array_get_exclusive(dev);
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+ if (IS_ERR(priv->rst))
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+ return dev_err_probe(dev, PTR_ERR(priv->rst),
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+ "failed to acquire reset\n");
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+
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+ ret = reset_control_reset(priv->rst);
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+ if (ret)
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+ return dev_err_probe(dev, ret, "failed to reset\n");
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+
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+ phydev->priv = priv;
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+
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+ return 0;
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+}
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+
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static struct phy_driver at803x_driver[] = {
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{
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/* Qualcomm Atheros AR8035 */
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@@ -1052,6 +1205,19 @@ static struct phy_driver at803x_driver[]
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.soft_reset = genphy_soft_reset,
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.config_aneg = at803x_config_aneg,
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}, {
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+ PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID),
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+ .name = "Qualcomm Atheros IPQ5018 internal PHY",
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+ .flags = PHY_IS_INTERNAL | PHY_POLL_CABLE_TEST,
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+ .probe = ipq5018_probe,
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+ .config_init = ipq5018_config_init,
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+ .link_change_notify = ipq5018_link_change_notify,
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+ .read_status = at803x_read_status,
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+ .config_intr = at803x_config_intr,
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+ .handle_interrupt = at803x_handle_interrupt,
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+ .cable_test_start = ipq5018_cable_test_start,
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+ .cable_test_get_status = qca808x_cable_test_get_status,
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+ .soft_reset = genphy_soft_reset,
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+}, {
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/* Qualcomm Atheros QCA9561 */
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PHY_ID_MATCH_EXACT(QCA9561_PHY_ID),
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.name = "Qualcomm Atheros QCA9561 built-in PHY",
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@@ -1077,6 +1243,7 @@ static const struct mdio_device_id __may
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{ PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
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{ PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
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{ PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
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+ { PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID) },
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{ PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
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{ }
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};
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