9f2dec7ef9
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de> Link: https://github.com/openwrt/openwrt/pull/24031 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
82 lines
2.3 KiB
Diff
82 lines
2.3 KiB
Diff
From f5f2b835e316df29b89e28ed7e467df473932e8d Mon Sep 17 00:00:00 2001
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From: George Moussalem <george.moussalem@outlook.com>
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Date: Mon, 30 Jun 2025 16:35:02 +0400
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Subject: arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus
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The IPQ5018 SoC contains an internal GE PHY, always at phy address 7.
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As such, let's add the GE PHY node to the SoC dtsi.
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The LDO controller found in the SoC must be enabled to provide constant
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low voltages to the PHY. The mdio-ipq4019 driver already has support
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for this, so adding the appropriate TCSR register offset.
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In addition, the GE PHY outputs both the RX and TX clocks to the GCC
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which gate controls them and routes them back to the PHY itself.
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So let's create two DT fixed clocks and register them in the GCC node.
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Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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Link: https://lore.kernel.org/r/20250630-ipq5018-ge-phy-v6-3-01be06378c15@outlook.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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arch/arm64/boot/dts/qcom/ipq5018.dtsi | 26 +++++++++++++++++++++++---
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1 file changed, 23 insertions(+), 3 deletions(-)
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(limited to 'arch/arm64/boot/dts/qcom/ipq5018.dtsi')
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--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@@ -17,6 +17,18 @@
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#size-cells = <2>;
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clocks {
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+ gephy_rx_clk: gephy-rx-clk {
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+ compatible = "fixed-clock";
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+ clock-frequency = <125000000>;
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+ #clock-cells = <0>;
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+ };
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+
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+ gephy_tx_clk: gephy-tx-clk {
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+ compatible = "fixed-clock";
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+ clock-frequency = <125000000>;
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+ #clock-cells = <0>;
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+ };
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+
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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@@ -187,7 +199,8 @@
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mdio0: mdio@88000 {
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compatible = "qcom,ipq5018-mdio";
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- reg = <0x00088000 0x64>;
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+ reg = <0x00088000 0x64>,
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+ <0x019475c4 0x4>;
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#address-cells = <1>;
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#size-cells = <0>;
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@@ -195,6 +208,13 @@
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clock-names = "gcc_mdio_ahb_clk";
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status = "disabled";
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+
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+ ge_phy: ethernet-phy@7 {
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+ compatible = "ethernet-phy-id004d.d0c0";
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+ reg = <7>;
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+
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+ resets = <&gcc GCC_GEPHY_MISC_ARES>;
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+ };
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};
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mdio1: mdio@90000 {
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@@ -346,8 +366,8 @@
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<&pcie0_phy>,
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<&pcie1_phy>,
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<0>,
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- <0>,
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- <0>,
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+ <&gephy_rx_clk>,
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+ <&gephy_tx_clk>,
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<0>,
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<0>;
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#clock-cells = <1>;
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