9f2dec7ef9
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de> Link: https://github.com/openwrt/openwrt/pull/24031 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
57 lines
2 KiB
Diff
57 lines
2 KiB
Diff
From 0c25ae62f5dc6a438b563536b5fe7fb6da3612b8 Mon Sep 17 00:00:00 2001
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From: Luo Jie <quic_luoj@quicinc.com>
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Date: Tue, 10 Jun 2025 18:35:18 +0800
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Subject: [PATCH] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5424 SoC
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The CMN PLL block in the IPQ5424 SoC takes 48 MHZ as the reference
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input clock. The output clocks are the same as IPQ9574 SoC, except
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for the clock rate of output clocks to PPE and NSS.
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Also, add the new header file to export the CMN PLL output clock
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specifiers for IPQ5424 SoC.
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Acked-by: Rob Herring (Arm) <robh@kernel.org>
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Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
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Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-1-ceada8165645@quicinc.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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.../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 +
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.../dt-bindings/clock/qcom,ipq5424-cmn-pll.h | 22 +++++++++++++++++++
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2 files changed, 23 insertions(+)
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create mode 100644 include/dt-bindings/clock/qcom,ipq5424-cmn-pll.h
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--- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
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+++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
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@@ -24,6 +24,7 @@ description:
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properties:
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compatible:
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enum:
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+ - qcom,ipq5424-cmn-pll
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- qcom,ipq9574-cmn-pll
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reg:
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--- /dev/null
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+++ b/include/dt-bindings/clock/qcom,ipq5424-cmn-pll.h
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@@ -0,0 +1,22 @@
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+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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+/*
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+ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
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+ */
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+
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+#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5424_CMN_PLL_H
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+#define _DT_BINDINGS_CLK_QCOM_IPQ5424_CMN_PLL_H
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+
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+/* CMN PLL core clock. */
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+#define IPQ5424_CMN_PLL_CLK 0
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+
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+/* The output clocks from CMN PLL of IPQ5424. */
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+#define IPQ5424_XO_24MHZ_CLK 1
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+#define IPQ5424_SLEEP_32KHZ_CLK 2
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+#define IPQ5424_PCS_31P25MHZ_CLK 3
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+#define IPQ5424_NSS_300MHZ_CLK 4
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+#define IPQ5424_PPE_375MHZ_CLK 5
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+#define IPQ5424_ETH0_50MHZ_CLK 6
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+#define IPQ5424_ETH1_50MHZ_CLK 7
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+#define IPQ5424_ETH2_50MHZ_CLK 8
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+#define IPQ5424_ETH_25MHZ_CLK 9
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+#endif
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