9f2dec7ef9
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de> Link: https://github.com/openwrt/openwrt/pull/24031 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
104 lines
3.8 KiB
Diff
104 lines
3.8 KiB
Diff
From a2afa4c33f0a7f7f70d54a1bc5110e326753f982 Mon Sep 17 00:00:00 2001
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From: Luo Jie <quic_luoj@quicinc.com>
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Date: Tue, 10 Jun 2025 18:35:19 +0800
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Subject: clk: qcom: cmnpll: Add IPQ5424 SoC support
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The CMN PLL in IPQ5424 SoC supplies the fixed clock to NSS at 300 MHZ
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and to PPE at 375 MHZ. Other output clocks from CMN PLL on this SoC,
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and their rates are same as IPQ9574.
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Acked-by: Stephen Boyd <sboyd@kernel.org>
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Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
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Link: https://lore.kernel.org/r/20250610-qcom_ipq5424_cmnpll-v3-2-ceada8165645@quicinc.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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drivers/clk/qcom/ipq-cmn-pll.c | 35 ++++++++++++++++++++++++++++++-----
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1 file changed, 30 insertions(+), 5 deletions(-)
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(limited to 'drivers/clk/qcom/ipq-cmn-pll.c')
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--- a/drivers/clk/qcom/ipq-cmn-pll.c
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+++ b/drivers/clk/qcom/ipq-cmn-pll.c
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@@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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- * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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+ * Copyright (c) 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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/*
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@@ -16,6 +16,10 @@
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* are supplied to GCC (24 MHZ as XO and 32 KHZ as sleep clock), and to PCS
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* with 31.25 MHZ.
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*
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+ * On the IPQ5424 SoC, there is an output clock from CMN PLL to PPE at 375 MHZ,
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+ * and an output clock to NSS (network subsystem) at 300 MHZ. The other output
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+ * clocks from CMN PLL on IPQ5424 are the same as IPQ9574.
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+ *
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* +---------+
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* | GCC |
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* +--+---+--+
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@@ -46,6 +50,7 @@
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
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+#include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h>
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#define CMN_PLL_REFCLK_SRC_SELECTION 0x28
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#define CMN_PLL_REFCLK_SRC_DIV GENMASK(9, 8)
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@@ -115,6 +120,20 @@ static const struct cmn_pll_fixed_output
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CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL),
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CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL),
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CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL),
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+ { /* Sentinel */ }
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+};
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+
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+static const struct cmn_pll_fixed_output_clk ipq5424_output_clks[] = {
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+ CLK_PLL_OUTPUT(IPQ5424_XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
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+ CLK_PLL_OUTPUT(IPQ5424_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
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+ CLK_PLL_OUTPUT(IPQ5424_PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL),
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+ CLK_PLL_OUTPUT(IPQ5424_NSS_300MHZ_CLK, "nss-300mhz", 300000000UL),
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+ CLK_PLL_OUTPUT(IPQ5424_PPE_375MHZ_CLK, "ppe-375mhz", 375000000UL),
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+ CLK_PLL_OUTPUT(IPQ5424_ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL),
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+ CLK_PLL_OUTPUT(IPQ5424_ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL),
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+ CLK_PLL_OUTPUT(IPQ5424_ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL),
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+ CLK_PLL_OUTPUT(IPQ5424_ETH_25MHZ_CLK, "eth-25mhz", 25000000UL),
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+ { /* Sentinel */ }
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};
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/*
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@@ -297,7 +316,7 @@ static struct clk_hw *ipq_cmn_pll_clk_hw
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static int ipq_cmn_pll_register_clks(struct platform_device *pdev)
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{
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- const struct cmn_pll_fixed_output_clk *fixed_clk;
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+ const struct cmn_pll_fixed_output_clk *p, *fixed_clk;
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struct clk_hw_onecell_data *hw_data;
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struct device *dev = &pdev->dev;
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struct clk_hw *cmn_pll_hw;
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@@ -305,8 +324,13 @@ static int ipq_cmn_pll_register_clks(str
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struct clk_hw *hw;
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int ret, i;
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- fixed_clk = ipq9574_output_clks;
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- num_clks = ARRAY_SIZE(ipq9574_output_clks);
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+ fixed_clk = device_get_match_data(dev);
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+ if (!fixed_clk)
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+ return -EINVAL;
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+
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+ num_clks = 0;
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+ for (p = fixed_clk; p->name; p++)
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+ num_clks++;
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hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, num_clks + 1),
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GFP_KERNEL);
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@@ -415,7 +439,8 @@ static const struct dev_pm_ops ipq_cmn_p
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};
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static const struct of_device_id ipq_cmn_pll_clk_ids[] = {
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- { .compatible = "qcom,ipq9574-cmn-pll", },
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+ { .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_output_clks },
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+ { .compatible = "qcom,ipq5424-cmn-pll", .data = &ipq5424_output_clks },
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{ }
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};
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MODULE_DEVICE_TABLE(of, ipq_cmn_pll_clk_ids);
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