9f2dec7ef9
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de> Link: https://github.com/openwrt/openwrt/pull/24031 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
102 lines
4 KiB
Diff
102 lines
4 KiB
Diff
From 25d12630561d8d0906f1f5eceb055da3af67c8c9 Mon Sep 17 00:00:00 2001
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From: George Moussalem <george.moussalem@outlook.com>
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Date: Fri, 16 May 2025 16:36:10 +0400
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Subject: clk: qcom: ipq-cmn-pll: Add IPQ5018 SoC support
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The CMN PLL in IPQ5018 SoC supplies fixed clocks to XO, sleep, and the
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ethernet block.
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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Link: https://lore.kernel.org/r/20250516-ipq5018-cmn-pll-v4-3-389a6b30e504@outlook.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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drivers/clk/qcom/ipq-cmn-pll.c | 37 +++++++++++++++++++++++--------------
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1 file changed, 23 insertions(+), 14 deletions(-)
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(limited to 'drivers/clk/qcom/ipq-cmn-pll.c')
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--- a/drivers/clk/qcom/ipq-cmn-pll.c
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+++ b/drivers/clk/qcom/ipq-cmn-pll.c
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@@ -50,6 +50,7 @@
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
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+#include <dt-bindings/clock/qcom,ipq5018-cmn-pll.h>
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#include <dt-bindings/clock/qcom,ipq5424-cmn-pll.h>
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#define CMN_PLL_REFCLK_SRC_SELECTION 0x28
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@@ -110,16 +111,10 @@ static const struct regmap_config ipq_cm
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.fast_io = true,
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};
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-static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = {
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- CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
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- CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
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- CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL),
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- CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL),
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- CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL),
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- CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL),
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- CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL),
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- CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL),
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- CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL),
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+static const struct cmn_pll_fixed_output_clk ipq5018_output_clks[] = {
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+ CLK_PLL_OUTPUT(IPQ5018_XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
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+ CLK_PLL_OUTPUT(IPQ5018_SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
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+ CLK_PLL_OUTPUT(IPQ5018_ETH_50MHZ_CLK, "eth-50mhz", 50000000UL),
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{ /* Sentinel */ }
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};
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@@ -136,6 +131,19 @@ static const struct cmn_pll_fixed_output
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{ /* Sentinel */ }
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};
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+static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = {
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+ CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
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+ CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
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+ CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL),
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+ CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL),
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+ CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL),
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+ CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL),
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+ CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL),
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+ CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL),
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+ CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL),
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+ { /* Sentinel */ }
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+};
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+
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/*
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* CMN PLL has the single parent clock, which supports the several
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* possible parent clock rates, each parent clock rate is reflected
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@@ -399,11 +407,11 @@ static int ipq_cmn_pll_clk_probe(struct
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*/
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ret = pm_clk_add(dev, "ahb");
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if (ret)
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- return dev_err_probe(dev, ret, "Fail to add AHB clock\n");
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+ return dev_err_probe(dev, ret, "Failed to add AHB clock\n");
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ret = pm_clk_add(dev, "sys");
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if (ret)
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- return dev_err_probe(dev, ret, "Fail to add SYS clock\n");
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+ return dev_err_probe(dev, ret, "Failed to add SYS clock\n");
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ret = pm_runtime_resume_and_get(dev);
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if (ret)
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@@ -414,7 +422,7 @@ static int ipq_cmn_pll_clk_probe(struct
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pm_runtime_put(dev);
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if (ret)
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return dev_err_probe(dev, ret,
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- "Fail to register CMN PLL clocks\n");
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+ "Failed to register CMN PLL clocks\n");
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return 0;
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}
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@@ -439,8 +447,9 @@ static const struct dev_pm_ops ipq_cmn_p
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};
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static const struct of_device_id ipq_cmn_pll_clk_ids[] = {
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- { .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_output_clks },
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+ { .compatible = "qcom,ipq5018-cmn-pll", .data = &ipq5018_output_clks },
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{ .compatible = "qcom,ipq5424-cmn-pll", .data = &ipq5424_output_clks },
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+ { .compatible = "qcom,ipq9574-cmn-pll", .data = &ipq9574_output_clks },
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{ }
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};
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MODULE_DEVICE_TABLE(of, ipq_cmn_pll_clk_ids);
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