9f2dec7ef9
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de> Link: https://github.com/openwrt/openwrt/pull/24031 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
89 lines
2.6 KiB
Diff
89 lines
2.6 KiB
Diff
From c006b249c54441dd8a3a493c7c87158f441f8178 Mon Sep 17 00:00:00 2001
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From: George Moussalem <george.moussalem@outlook.com>
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Date: Mon, 21 Jul 2025 10:04:35 +0400
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Subject: arm64: dts: ipq5018: Add CMN PLL node
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Add CMN PLL node for enabling output clocks to the networking
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hardware blocks on IPQ5018 devices.
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The reference clock of CMN PLL is routed from XO to the CMN PLL
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through the internal WiFi block.
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.XO (48 MHZ) --> WiFi (multiplier/divider)--> 96 MHZ to CMN PLL.
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Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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Link: https://lore.kernel.org/r/20250721-ipq5018-cmn-pll-v5-1-4cbf3479af65@outlook.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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arch/arm64/boot/dts/qcom/ipq5018.dtsi | 33 +++++++++++++++++++++++++++++++--
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1 file changed, 31 insertions(+), 2 deletions(-)
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(limited to 'arch/arm64/boot/dts/qcom/ipq5018.dtsi')
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--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@@ -2,12 +2,13 @@
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/*
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* IPQ5018 SoC device tree source
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*
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- * Copyright (c) 2023 The Linux Foundation. All rights reserved.
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+ * Copyright (c) 2023-2025 The Linux Foundation. All rights reserved.
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*/
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#include <dt-bindings/clock/qcom,apss-ipq.h>
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-#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
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+#include <dt-bindings/clock/qcom,ipq5018-cmn-pll.h>
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+#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
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#include <dt-bindings/thermal/thermal.h>
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@@ -29,6 +30,14 @@
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#clock-cells = <0>;
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};
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+ ref_96mhz_clk: ref-96mhz-clk {
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+ compatible = "fixed-factor-clock";
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+ clocks = <&xo_clk>;
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+ #clock-cells = <0>;
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+ clock-div = <1>;
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+ clock-mult = <2>;
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+ };
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+
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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@@ -38,6 +47,12 @@
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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+
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+ xo_clk: xo-clk {
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+ compatible = "fixed-clock";
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+ #clock-cells = <0>;
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+ clock-frequency = <48000000>;
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+ };
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};
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cpus {
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@@ -229,6 +244,20 @@
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status = "disabled";
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};
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+ cmn_pll: clock-controller@9b000 {
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+ compatible = "qcom,ipq5018-cmn-pll";
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+ reg = <0x0009b000 0x800>;
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+ clocks = <&ref_96mhz_clk>,
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+ <&gcc GCC_CMN_BLK_AHB_CLK>,
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+ <&gcc GCC_CMN_BLK_SYS_CLK>;
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+ clock-names = "ref",
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+ "ahb",
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+ "sys";
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+ #clock-cells = <1>;
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+ assigned-clocks = <&cmn_pll IPQ5018_CMN_PLL_CLK>;
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+ assigned-clock-rates-u64 = /bits/ 64 <9600000000>;
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+ };
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+
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qfprom: qfprom@a0000 {
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compatible = "qcom,ipq5018-qfprom", "qcom,qfprom";
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reg = <0x000a0000 0x1000>;
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