9f2dec7ef9
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de> Link: https://github.com/openwrt/openwrt/pull/24031 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
52 lines
1.9 KiB
Diff
52 lines
1.9 KiB
Diff
From 7156c65030006e6930dd99c5b8c5e84e69ca5f0b Mon Sep 17 00:00:00 2001
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From: John Crispin <john@phrozen.org>
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Date: Wed, 11 Mar 2026 19:39:40 +0100
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Subject: [PATCH] dt-bindings: clock: qcom: Add CMN PLL support for IPQ8074
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The CMN PLL block in the IPQ8074 SoC takes 48 MHz as the reference
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input clock. Its output clocks are the bias_pll_cc_clk (300 MHz) and
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bias_pll_nss_noc_clk (416.5 MHz) clocks used by the networking
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subsystem.
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Add the related compatible for IPQ8074 to the ipq9574-cmn-pll
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generic schema.
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Signed-off-by: John Crispin <john@phrozen.org>
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
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Link: https://lore.kernel.org/r/20260311183942.10134-4-ansuelsmth@gmail.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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.../bindings/clock/qcom,ipq9574-cmn-pll.yaml | 1 +
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include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h | 15 +++++++++++++++
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2 files changed, 16 insertions(+)
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create mode 100644 include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h
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--- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
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+++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
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@@ -27,6 +27,7 @@ properties:
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- qcom,ipq5018-cmn-pll
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- qcom,ipq5424-cmn-pll
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- qcom,ipq6018-cmn-pll
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+ - qcom,ipq8074-cmn-pll
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- qcom,ipq9574-cmn-pll
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reg:
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--- /dev/null
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+++ b/include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h
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@@ -0,0 +1,15 @@
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+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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+/*
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+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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+ */
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+
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+#ifndef _DT_BINDINGS_CLK_QCOM_IPQ8074_CMN_PLL_H
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+#define _DT_BINDINGS_CLK_QCOM_IPQ8074_CMN_PLL_H
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+
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+/* CMN PLL core clock. */
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+#define IPQ8074_CMN_PLL_CLK 0
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+
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+/* The output clocks from CMN PLL of IPQ8074. */
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+#define IPQ8074_BIAS_PLL_CC_CLK 1
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+#define IPQ8074_BIAS_PLL_NSS_NOC_CLK 2
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+#endif
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