9f2dec7ef9
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de> Link: https://github.com/openwrt/openwrt/pull/24031 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
56 lines
2.2 KiB
Diff
56 lines
2.2 KiB
Diff
From 88c543fff756450bcd04ec4560c4440be36c9e75 Mon Sep 17 00:00:00 2001
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From: Luo Jie <jie.luo@oss.qualcomm.com>
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Date: Tue, 6 Jan 2026 21:35:10 -0800
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Subject: [PATCH] clk: qcom: cmnpll: Account for reference clock divider
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The clk_cmn_pll_recalc_rate() function must account for the reference clock
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divider programmed in CMN_PLL_REFCLK_CONFIG. Without this fix, platforms
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with a reference divider other than 1 calculate incorrect CMN PLL rates.
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For example, on IPQ5332 where the reference divider is 2, the computed rate
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becomes twice the actual output.
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Read CMN_PLL_REFCLK_DIV and divide the parent rate by this value before
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applying the 2 * FACTOR scaling. This yields the correct rate calculation:
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rate = (parent_rate / ref_div) * 2 * factor.
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Maintain backward compatibility with earlier platforms (e.g. IPQ9574,
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IPQ5424, IPQ5018) that use ref_div = 1.
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Fixes: f81715a4c87c ("clk: qcom: Add CMN PLL clock controller driver for IPQ SoC")
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Signed-off-by: Luo Jie <jie.luo@oss.qualcomm.com>
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Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
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Tested-by: George Moussalem <george.moussalem@outlook.com>
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Link: https://lore.kernel.org/r/20260106-qcom_ipq5332_cmnpll-v2-1-f9f7e4efbd79@oss.qualcomm.com
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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---
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drivers/clk/qcom/ipq-cmn-pll.c | 11 +++++++++--
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1 file changed, 9 insertions(+), 2 deletions(-)
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--- a/drivers/clk/qcom/ipq-cmn-pll.c
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+++ b/drivers/clk/qcom/ipq-cmn-pll.c
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@@ -200,7 +200,7 @@ static unsigned long clk_cmn_pll_recalc_
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unsigned long parent_rate)
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{
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struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw);
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- u32 val, factor;
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+ u32 val, factor, ref_div;
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/*
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* The value of CMN_PLL_DIVIDER_CTRL_FACTOR is automatically adjusted
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@@ -208,8 +208,15 @@ static unsigned long clk_cmn_pll_recalc_
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*/
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regmap_read(cmn_pll->regmap, CMN_PLL_DIVIDER_CTRL, &val);
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factor = FIELD_GET(CMN_PLL_DIVIDER_CTRL_FACTOR, val);
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+ if (WARN_ON(factor == 0))
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+ factor = 1;
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- return parent_rate * 2 * factor;
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+ regmap_read(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG, &val);
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+ ref_div = FIELD_GET(CMN_PLL_REFCLK_DIV, val);
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+ if (WARN_ON(ref_div == 0))
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+ ref_div = 1;
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+
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+ return div_u64((u64)parent_rate * 2 * factor, ref_div);
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}
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static int clk_cmn_pll_determine_rate(struct clk_hw *hw,
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