9f2dec7ef9
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de> Link: https://github.com/openwrt/openwrt/pull/24031 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
35 lines
1.4 KiB
Diff
35 lines
1.4 KiB
Diff
From 02320d694fa1124b8b77fcb52191141004ef7fbb Mon Sep 17 00:00:00 2001
|
|
From: George Moussalem <george.moussalem@outlook.com>
|
|
Date: Thu, 21 May 2026 11:55:58 +0400
|
|
Subject: arm64: dts: qcom: ipq5018: Correct CMN PLL reference clock rate
|
|
|
|
The correct CMN PLL reference clock rate for IPQ5018 is 4.8 GHz.
|
|
|
|
The CMN PLL driver did not account for the ref clock divider which is 2
|
|
for IPQ5018. Therefore, the computed rate was twice the actual output.
|
|
|
|
With the driver now accounting for the CMN PLL reference clock
|
|
divider (commit: 88c543fff756), set the correct reference clock rate.
|
|
|
|
Fixes: c006b249c544 ("arm64: dts: ipq5018: Add CMN PLL node")
|
|
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
|
|
Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
|
|
Link: https://lore.kernel.org/r/20260521-ipq5018-cmn-pll-rate-fix-v2-1-04b28a92e0f2@outlook.com
|
|
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
|
---
|
|
arch/arm64/boot/dts/qcom/ipq5018.dtsi | 2 +-
|
|
1 file changed, 1 insertion(+), 1 deletion(-)
|
|
|
|
(limited to 'arch/arm64/boot/dts/qcom/ipq5018.dtsi')
|
|
|
|
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
|
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
|
@@ -256,7 +256,7 @@
|
|
"sys";
|
|
#clock-cells = <1>;
|
|
assigned-clocks = <&cmn_pll IPQ5018_CMN_PLL_CLK>;
|
|
- assigned-clock-rates-u64 = /bits/ 64 <9600000000>;
|
|
+ assigned-clock-rates-u64 = /bits/ 64 <4800000000>;
|
|
};
|
|
|
|
qfprom: qfprom@a0000 {
|