9f2dec7ef9
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de> Link: https://github.com/openwrt/openwrt/pull/24031 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
90 lines
3 KiB
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90 lines
3 KiB
Diff
From 82eaf94d69fce20f8859a2b8dae8e7064d9343da Mon Sep 17 00:00:00 2001
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From: George Moussalem <george.moussalem@outlook.com>
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Date: Fri, 13 Jun 2025 05:55:07 +0400
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Subject: [PATCH] dt-bindings: net: qca,ar803x: Add IPQ5018 Internal GE PHY
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support
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Document the IPQ5018 Internal Gigabit Ethernet PHY found in the IPQ5018
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SoC. Its output pins provide an MDI interface to either an external
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switch in a PHY to PHY link scenario or is directly attached to an RJ45
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connector.
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The PHY supports 10/100/1000 mbps link modes, CDT, auto-negotiation and
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802.3az EEE.
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For operation, the LDO controller found in the IPQ5018 SoC for which
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there is provision in the mdio-4019 driver.
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Two common archictures across IPQ5018 boards are:
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1. IPQ5018 PHY --> MDI --> RJ45 connector
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2. IPQ5018 PHY --> MDI --> External PHY
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In a phy to phy architecture, the DAC needs to be configured to
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accommodate for the short cable length. As such, add an optional boolean
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property so the driver sets preset DAC register values accordingly.
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Signed-off-by: George Moussalem <george.moussalem@outlook.com>
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Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Link: https://patch.msgid.link/20250613-ipq5018-ge-phy-v5-1-9af06e34ea6b@outlook.com
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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.../devicetree/bindings/net/qca,ar803x.yaml | 43 +++++++++++++++++++
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1 file changed, 43 insertions(+)
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--- a/Documentation/devicetree/bindings/net/qca,ar803x.yaml
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+++ b/Documentation/devicetree/bindings/net/qca,ar803x.yaml
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@@ -16,8 +16,37 @@ description: |
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allOf:
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- $ref: ethernet-phy.yaml#
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+ - if:
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+ properties:
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+ compatible:
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+ contains:
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+ enum:
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+ - ethernet-phy-id004d.d0c0
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+
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+ then:
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+ properties:
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+ reg:
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+ const: 7 # This PHY is always at MDIO address 7 in the IPQ5018 SoC
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+
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+ resets:
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+ items:
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+ - description:
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+ GE PHY MISC reset which triggers a reset across MDC, DSP, RX, and TX lines.
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+
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+ qcom,dac-preset-short-cable:
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+ description:
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+ Set if this phy is connected to another phy to adjust the values for
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+ MDAC and EDAC to adjust amplitude, bias current settings, and error
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+ detection and correction algorithm to accommodate for short cable length.
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+ If not set, DAC values are not modified and it is assumed the MDI output pins
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+ of this PHY are directly connected to an RJ45 connector.
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+ type: boolean
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properties:
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+ compatible:
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+ enum:
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+ - ethernet-phy-id004d.d0c0
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+
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qca,clk-out-frequency:
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description: Clock output frequency in Hertz.
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$ref: /schemas/types.yaml#/definitions/uint32
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@@ -132,3 +161,17 @@ examples:
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};
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};
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};
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+ - |
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+ #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
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+
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+ mdio {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ ge_phy: ethernet-phy@7 {
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+ compatible = "ethernet-phy-id004d.d0c0";
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+ reg = <7>;
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+
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+ resets = <&gcc GCC_GEPHY_MISC_ARES>;
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+ };
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+ };
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