9f2dec7ef9
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de> Link: https://github.com/openwrt/openwrt/pull/24031 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
134 lines
4.9 KiB
Diff
134 lines
4.9 KiB
Diff
From: George Moussalem <george.moussalem@outlook.com>
|
|
Date: Wed, 27 Oct 2024 16:34:11 +0400
|
|
Subject: [PATCH] arm64: dts: qcom: ipq5018: add wifi support
|
|
|
|
The IPQ5018 SoC comes with an internal 2x2 2.4Ghz wifi radio.
|
|
QCN6122 is a PCIe based wifi solution specific to the IPQ5018 platform which
|
|
comes optinally packed with 1 or 2 QCN6122 chips or with an external
|
|
PCIe based wifi solution (such as QCN9074) for 5/6 Ghz support.
|
|
|
|
As such, add wifi nodes for both IPQ5018 and QCN6122.
|
|
|
|
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
|
|
---
|
|
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
|
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
|
|
@@ -739,6 +739,118 @@
|
|
};
|
|
};
|
|
|
|
+ wifi: wifi@c000000 {
|
|
+ compatible = "qcom,ipq5018-wifi";
|
|
+ reg = <0x0c000000 0x1000000>;
|
|
+
|
|
+ interrupts = <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 300 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 301 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 302 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 303 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 304 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 305 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 306 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 308 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 334 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 313 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 316 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 317 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 319 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 320 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 323 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 325 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 326 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 327 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 329 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 331 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 332 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 333 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 312 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 335 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 336 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 337 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 338 IRQ_TYPE_EDGE_RISING>,
|
|
+ <GIC_SPI 339 IRQ_TYPE_EDGE_RISING>;
|
|
+ interrupt-names = "misc-pulse1",
|
|
+ "misc-latch",
|
|
+ "sw-exception",
|
|
+ "watchdog",
|
|
+ "ce0",
|
|
+ "ce1",
|
|
+ "ce2",
|
|
+ "ce3",
|
|
+ "ce4",
|
|
+ "ce5",
|
|
+ "ce6",
|
|
+ "ce7",
|
|
+ "ce8",
|
|
+ "ce9",
|
|
+ "ce10",
|
|
+ "ce11",
|
|
+ "host2wbm-desc-feed",
|
|
+ "host2reo-re-injection",
|
|
+ "host2reo-command",
|
|
+ "host2rxdma-monitor-ring3",
|
|
+ "host2rxdma-monitor-ring2",
|
|
+ "host2rxdma-monitor-ring1",
|
|
+ "reo2ost-exception",
|
|
+ "wbm2host-rx-release",
|
|
+ "reo2host-status",
|
|
+ "reo2host-destination-ring4",
|
|
+ "reo2host-destination-ring3",
|
|
+ "reo2host-destination-ring2",
|
|
+ "reo2host-destination-ring1",
|
|
+ "rxdma2host-monitor-destination-mac3",
|
|
+ "rxdma2host-monitor-destination-mac2",
|
|
+ "rxdma2host-monitor-destination-mac1",
|
|
+ "ppdu-end-interrupts-mac3",
|
|
+ "ppdu-end-interrupts-mac2",
|
|
+ "ppdu-end-interrupts-mac1",
|
|
+ "rxdma2host-monitor-status-ring-mac3",
|
|
+ "rxdma2host-monitor-status-ring-mac2",
|
|
+ "rxdma2host-monitor-status-ring-mac1",
|
|
+ "host2rxdma-host-buf-ring-mac3",
|
|
+ "host2rxdma-host-buf-ring-mac2",
|
|
+ "host2rxdma-host-buf-ring-mac1",
|
|
+ "rxdma2host-destination-ring-mac3",
|
|
+ "rxdma2host-destination-ring-mac2",
|
|
+ "rxdma2host-destination-ring-mac1",
|
|
+ "host2tcl-input-ring4",
|
|
+ "host2tcl-input-ring3",
|
|
+ "host2tcl-input-ring2",
|
|
+ "host2tcl-input-ring1",
|
|
+ "wbm2host-tx-completions-ring3",
|
|
+ "wbm2host-tx-completions-ring2",
|
|
+ "wbm2host-tx-completions-ring1",
|
|
+ "tcl2host-status-ring";
|
|
+
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
q6v5_wcss: remoteproc@cd00000 {
|
|
compatible = "qcom,ipq5018-wcss-sec-pil";
|
|
reg = <0x0cd00000 0x10000>;
|