9f2dec7ef9
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de> Link: https://github.com/openwrt/openwrt/pull/24031 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
51 lines
1.4 KiB
Diff
51 lines
1.4 KiB
Diff
--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
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@@ -9,6 +9,7 @@
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#include <dt-bindings/clock/qcom,gcc-ipq5018.h>
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#include <dt-bindings/clock/qcom,ipq5018-cmn-pll.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/net/qca-uniphy.h>
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#include <dt-bindings/reset/qcom,gcc-ipq5018.h>
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#include <dt-bindings/thermal/thermal.h>
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@@ -258,6 +259,29 @@
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status = "disabled";
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};
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+ uniphy0: ethernet-pcs@98000 {
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+ compatible = "qualcomm,ipq5018-uniphy";
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+ reg = <0x00098000 0x800>;
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+ #clock-cells = <1>;
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+ clocks = <&gcc GCC_UNIPHY_AHB_CLK>,
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+ <&gcc GCC_UNIPHY_SYS_CLK>,
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+ <&gcc GCC_UNIPHY_RX_CLK>,
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+ <&gcc GCC_UNIPHY_TX_CLK>,
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+ <&cmn_pll IPQ5018_ETH_50MHZ_CLK>;
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+ clock-names = "ahb",
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+ "sys",
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+ "port5_rx",
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+ "port5_tx",
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+ "ref";
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+ clock-output-names = "uniphy0_gcc_rx_clk",
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+ "uniphy0_gcc_tx_clk",
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+ "uniphy0_ref_clk";
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+ resets = <&gcc GCC_UNIPHY_SOFT_RESET>;
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+ reset-names = "soft";
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+ #pcs-cells = <0>;
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+ status = "disabled";
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+ };
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+
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cmn_pll: clock-controller@9b000 {
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compatible = "qcom,ipq5018-cmn-pll";
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reg = <0x0009b000 0x800>;
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@@ -449,8 +473,8 @@
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<0>,
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<&gephy_rx_clk>,
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<&gephy_tx_clk>,
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- <0>,
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- <0>;
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+ <&uniphy0 UNIPHY_CLK_RX>,
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+ <&uniphy0 UNIPHY_CLK_TX>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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