dd8f705e85
Wire the two HS104 controllers on the i2c-gpio bus and attach the 8 PoE PHYs via a new PHY_C45_PSE macro. Add the STC8 syscon with its per-port PoE LED triggers, enable LEDS_SYSCON, and pull the PSE and STC8 kmods into the image. Signed-off-by: Carlo Szelinsky <github@szelinsky.de> Link: https://github.com/openwrt/openwrt/pull/22245 Signed-off-by: Jonas Jelonek <jelonek.jonas@gmail.com>
107 lines
2.6 KiB
Text
107 lines
2.6 KiB
Text
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/dts-v1/;
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#define STRINGIZE(s) #s
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#define LAN_LABEL(p, s) STRINGIZE(p ## s)
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#define SWITCH_PORT_LABEL(n) LAN_LABEL(lan, n)
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#define PHY_C22(p, n) \
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phy##p: ethernet-phy@n { \
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reg = <##n>; \
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compatible = "ethernet-phy-ieee802.3-c22"; \
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};
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#define PHY_C22_SFP(p, n, s) \
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phy##p: ethernet-phy@n { \
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reg = <##n>; \
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compatible = "ethernet-phy-ieee802.3-c22"; \
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sfp = <&sfp##s>; \
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};
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#define PHY_C45(p, n) \
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phy##p: ethernet-phy@n { \
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reg = <##n>; \
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compatible = "ethernet-phy-ieee802.3-c45"; \
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};
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#define PHY_C45_PAIR_ORDER(p, n, po) \
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phy##p: ethernet-phy@n { \
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reg = <##n>; \
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compatible = "ethernet-phy-ieee802.3-c45"; \
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enet-phy-pair-order = <##po>; \
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};
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#define PHY_C45_PSE(p, n, pi) \
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phy##p: ethernet-phy@n { \
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reg = <##n>; \
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compatible = "ethernet-phy-ieee802.3-c45"; \
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pses = <&pi>; \
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};
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#define HASH_PSE_CELLS #pse-cells
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#define PSE_PI(p) \
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pse_pi##p: pse-pi@p { \
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reg = <p>; \
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HASH_PSE_CELLS = <0>; \
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};
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#define SWITCH_PORT(p, l, m) \
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port##p: port@##p { \
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reg = <##p>; \
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label = SWITCH_PORT_LABEL(l) ; \
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phy-handle = <&phy##p>; \
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phy-mode = #m ; \
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};
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#define SWITCH_PORT_SDS(p, l, s, i, m) \
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port##p: port@##p { \
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reg = <##p>; \
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label = SWITCH_PORT_LABEL(l) ; \
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pcs-handle = <&serdes##s i>; \
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phy-handle = <&phy##p>; \
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phy-mode = #m ; \
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};
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#define SWITCH_PORT_LED(p, l, s, i, c, m) \
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port##p: port@##p { \
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reg = <##p>; \
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label = SWITCH_PORT_LABEL(l) ; \
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led-set = <##c>; \
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pcs-handle = <&serdes##s i>; \
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phy-handle = <&phy##p>; \
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phy-mode = #m ; \
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};
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#define SWITCH_PORT_SFP(p, l, s, c, g) \
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port##p: port@##p { \
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reg = <##p>; \
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label = SWITCH_PORT_LABEL(l) ; \
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led-set = <##c>; \
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pcs-handle = <&serdes##s 0>; \
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phy-mode = "1000base-x"; \
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sfp = <&sfp##g>; \
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managed = "in-band-status"; \
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};
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/* LED Set mode definitions */
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#define RTL93XX_LED_SET_NONE (0)
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#define RTL93XX_LED_SET_10G (1 << 0)
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#define RTL93XX_LED_SET_5G (1 << 1)
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#define RTL93XX_LED_SET_2P5G (1 << 3)
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#define RTL93XX_LED_SET_1G (1 << 5)
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#define RTL93XX_LED_SET_100M (1 << 7)
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#define RTL93XX_LED_SET_10M (1 << 8)
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#define RTL93XX_LED_SET_LINK (1 << 9)
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#define RTL93XX_LED_SET_LINK_BLINK (1 << 10)
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#define RTL93XX_LED_SET_ACT (1 << 11)
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#define RTL93XX_LED_SET_RX (1 << 12)
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#define RTL93XX_LED_SET_TX (1 << 13)
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#define RTL93XX_LED_SET_COLLISION (1 << 14)
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#define RTL93XX_LED_SET_DUPLEX (1 << 15)
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/* LED Interface modes */
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#define RTL93XX_LED_MODE_SERIAL 1
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#define RTL93XX_LED_MODE_SINGLE_COLOR_SCAN 2
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#define RTL93XX_LED_MODE_BI_COLOR_SCAN 3
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