f4a7ae107e
USXGMII carries the line rate to the MAC in a Clause 37 code word, so the link needs in-band signalling. Without "managed" the port is PHY managed, phylink disables in-band on the PHY, and with the PCS now honouring neg_mode neither end runs autonegotiation, so nothing crosses the system interface. Every USXGMII port in this target was missing the property: ten ports across eight boards, all of them an Aquantia PHY on copper, none of them an SFP cage. ipq8074-rt-ax89x already carried "in-band-status" on its SGMII lan8, which is why a file-level search made it look covered. Only the two ports on ipq8072-301w have been tested on hardware. The remaining eight are the same PHY family behind the same PCS, are broken today for the same reason, and cannot regress from a state where they pass no traffic, but they have not been confirmed on a board. That test ran on the 6.18 testing kernel, where phylink switches the PHY side on through phy_config_inband(). On 6.12 the PHY has no such op and 0760-net-phy-aquantia-enable-USXGMII-MAC-autoneg.patch forces the same bit unconditionally, so the end state matches, but no board has confirmed it there. Tested-by: Rudy Andram <rmandrad@gmail.com> Assisted-by: Claude:claude-opus-5 Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de> Link: https://github.com/openwrt/openwrt/pull/24420 Signed-off-by: Robert Marko <robimarko@gmail.com>
525 lines
9 KiB
Text
525 lines
9 KiB
Text
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/dts-v1/;
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#include "ipq8074.dtsi"
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#include "ipq8074-hk-cpu.dtsi"
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#include "ipq8074-ess.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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/ {
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model = "Linksys MX8500";
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compatible = "linksys,mx8500", "qcom,ipq8074";
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aliases {
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serial0 = &blsp1_uart5;
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serial1 = &blsp1_uart3;
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led-boot = &led_system_blue;
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led-running = &led_system_blue;
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led-failsafe = &led_system_red;
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led-upgrade = &led_system_green;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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bootargs-append = " root=/dev/ubiblock0_0 rootfstype=squashfs ro";
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};
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gpio_export {
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compatible = "gpio-export";
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bt_pwr {
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gpio-export,name = "bt_pwr";
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gpio-export,output = <1>;
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gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>;
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};
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};
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keys {
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compatible = "gpio-keys";
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pinctrl-0 = <&button_pins>;
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pinctrl-names = "default";
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reset-button {
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label = "reset";
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gpios = <&tlmm 67 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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wps-button {
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label = "wps";
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gpios = <&tlmm 64 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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};
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};
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};
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&tlmm {
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button_pins: button-state {
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pins = "gpio64", "gpio67";
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function = "gpio";
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drive-strength = <8>;
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bias-pull-up;
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};
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mdio_pins: mdio-state {
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mdc-pins {
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pins = "gpio68";
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function = "mdc";
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drive-strength = <8>;
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bias-pull-up;
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};
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mdio-pins {
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pins = "gpio69";
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function = "mdio";
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drive-strength = <8>;
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bias-pull-up;
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};
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};
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};
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&blsp1_uart3 {
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status = "okay";
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};
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&blsp1_uart5 {
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status = "okay";
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};
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&prng {
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status = "okay";
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};
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&qpic_bam {
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status = "okay";
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};
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&qpic_nand {
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status = "okay";
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/*
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* Bootloader will find the NAND DT node by the compatible and
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* then "fixup" it by adding the partitions from the SMEM table
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* using the legacy bindings thus making it impossible for us
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* to change the partition table or utilize NVMEM for calibration.
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* So add a dummy partitions node that bootloader will populate
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* and set it as disabled so the kernel ignores it instead of
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* printing warnings due to the broken way bootloader adds the
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* partitions.
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*/
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partitions {
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status = "disabled";
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};
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nand@0 {
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reg = <0>;
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nand-ecc-strength = <4>;
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nand-ecc-step-size = <512>;
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nand-bus-width = <8>;
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#address-cells = <1>;
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#size-cells = <1>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "0:sbl1";
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reg = <0x0 0x100000>;
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read-only;
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};
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partition@100000 {
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label = "0:mibib";
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reg = <0x100000 0x100000>;
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read-only;
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};
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partition@200000 {
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label = "0:bootconfig";
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reg = <0x200000 0x80000>;
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read-only;
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};
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partition@280000 {
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label = "0:bootconfig1";
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reg = <0x280000 0x80000>;
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read-only;
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};
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partition@300000 {
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label = "0:qsee";
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reg = <0x300000 0x300000>;
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read-only;
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};
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partition@600000 {
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label = "0:qsee_1";
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reg = <0x600000 0x300000>;
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read-only;
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};
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partition@900000 {
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label = "0:devcfg";
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reg = <0x900000 0x80000>;
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read-only;
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};
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partition@980000 {
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label = "0:devcfg_1";
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reg = <0x980000 0x80000>;
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read-only;
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};
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partition@a00000 {
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label = "0:apdp";
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reg = <0xa00000 0x80000>;
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read-only;
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};
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partition@a80000 {
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label = "0:apdp_1";
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reg = <0xa80000 0x80000>;
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read-only;
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};
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partition@b00000 {
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label = "0:rpm";
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reg = <0xb00000 0x80000>;
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read-only;
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};
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partition@b80000 {
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label = "0:rpm_1";
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reg = <0xb80000 0x80000>;
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read-only;
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};
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partition@c00000 {
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label = "0:cdt";
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reg = <0xc00000 0x80000>;
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read-only;
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};
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partition@c80000 {
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label = "0:cdt_1";
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reg = <0xc80000 0x80000>;
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read-only;
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};
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partition@d00000 {
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label = "0:appsblenv";
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reg = <0xd00000 0x80000>;
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};
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partition@d80000 {
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label = "0:appsbl";
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reg = <0xd80000 0x100000>;
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read-only;
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};
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partition@e80000 {
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label = "0:appsbl_1";
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reg = <0xe80000 0x100000>;
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read-only;
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};
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partition@f80000 {
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label = "0:art";
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reg = <0xf80000 0x80000>;
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read-only;
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};
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partition@1000000 {
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label = "u_env";
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reg = <0x1000000 0x40000>;
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};
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partition@1040000 {
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label = "s_env";
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reg = <0x1040000 0x20000>;
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};
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partition@1060000 {
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label = "devinfo";
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reg = <0x1060000 0x20000>;
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read-only;
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nvmem-layout {
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compatible = "ascii-eq-delim-env";
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hw_mac_addr: hw_mac_addr {
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compatible = "mac-base";
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#nvmem-cell-cells = <1>;
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};
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};
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};
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partition@1080000 {
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label = "kernel";
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reg = <0x1080000 0x9600000>;
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};
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partition@1680000 {
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label = "rootfs";
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reg = <0x1680000 0x9000000>;
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linux,rootfs;
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};
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partition@a680000 {
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label = "alt_kernel";
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reg = <0xa680000 0x9600000>;
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};
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partition@ac80000 {
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label = "alt_rootfs";
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reg = <0xac80000 0x9000000>;
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};
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partition@13c80000 {
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label = "sysdiag";
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reg = <0x13c80000 0x200000>;
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read-only;
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};
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partition@13e80000 {
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label = "0:ethphyfw";
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reg = <0x13e80000 0x100000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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aqr_fw: firmware@28 {
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/* Skip the QCOM MBN Header of 40 bytes */
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reg = <0x28 0x60002>;
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};
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};
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};
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partition@13f80000 {
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label = "syscfg";
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reg = <0x13f80000 0xb180000>;
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read-only;
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};
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partition@1f100000 {
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label = "app_data";
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reg = <0x1f100000 0x500000>;
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read-only;
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};
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partition@1f600000 {
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label = "0:wififw";
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reg = <0x1f600000 0xa00000>;
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read-only;
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};
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};
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};
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};
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&blsp1_i2c2 {
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status = "okay";
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led-controller@62 {
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compatible = "nxp,pca9633";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x62>;
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nxp,hw-blink;
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led_system_red: led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_RED>;
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function = LED_FUNCTION_STATUS;
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};
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led_system_green: led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_STATUS;
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};
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led_system_blue: led@2 {
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reg = <2>;
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color = <LED_COLOR_ID_BLUE>;
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function = LED_FUNCTION_STATUS;
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};
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};
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};
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&mdio {
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status = "okay";
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pinctrl-0 = <&mdio_pins>;
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pinctrl-names = "default";
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reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
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ethernet-phy-package@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,qca8075-package";
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reg = <0>;
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qcom,package-mode = "qsgmii";
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qca8075_0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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};
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qca8075_1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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qca8075_2: ethernet-phy@2 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <2>;
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};
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qca8075_3: ethernet-phy@3 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <3>;
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};
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};
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aqr114c: ethernet-phy@8 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <8>;
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reset-gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
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firmware-name = "marvell/AQR-G4_v5.6.5-AQR_WNC_SAQA-L2_GT_ID45287_VER24005.cld";
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nvmem-cells = <&aqr_fw>;
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nvmem-cell-names = "firmware";
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};
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};
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&uniphy0 {
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status = "okay";
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};
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&uniphy2 {
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status = "okay";
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};
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&switch {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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ethernet = <&edma>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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swport1: port@1 {
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reg = <1>;
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label = "lan1";
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phy-handle = <&qca8075_0>;
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phy-mode = "qsgmii";
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pcs-handle = <&uniphy0 0>;
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nvmem-cells = <&hw_mac_addr 1>;
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nvmem-cell-names = "mac-address";
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};
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swport2: port@2 {
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reg = <2>;
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label = "lan2";
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phy-handle = <&qca8075_1>;
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phy-mode = "qsgmii";
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pcs-handle = <&uniphy0 1>;
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nvmem-cells = <&hw_mac_addr 1>;
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nvmem-cell-names = "mac-address";
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};
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swport3: port@3 {
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reg = <3>;
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label = "lan3";
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phy-handle = <&qca8075_2>;
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phy-mode = "qsgmii";
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pcs-handle = <&uniphy0 2>;
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nvmem-cells = <&hw_mac_addr 1>;
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nvmem-cell-names = "mac-address";
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};
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swport4: port@4 {
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reg = <4>;
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label = "lan4";
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phy-handle = <&qca8075_3>;
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phy-mode = "qsgmii";
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pcs-handle = <&uniphy0 3>;
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nvmem-cells = <&hw_mac_addr 1>;
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nvmem-cell-names = "mac-address";
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};
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swport6: port@6 {
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reg = <6>;
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label = "wan";
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phy-handle = <&aqr114c>;
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phy-mode = "usxgmii";
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managed = "in-band-status";
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pcs-handle = <&uniphy2 0>;
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nvmem-cells = <&hw_mac_addr 0>;
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nvmem-cell-names = "mac-address";
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};
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};
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};
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&edma {
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status = "okay";
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};
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&ssphy_0 {
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status = "okay";
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};
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&qusb_phy_0 {
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status = "okay";
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};
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&usb_0 {
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status = "okay";
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};
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&pcie_qmp0 {
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status = "okay";
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};
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&pcie0 {
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status = "okay";
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perst-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>;
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pcie@0 {
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wifi@0,0 {
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status = "okay";
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/* ath11k has no DT compatible for PCI cards */
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compatible = "pci17cb,1104";
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reg = <0x00010000 0 0 0 0>;
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qcom,ath11k-calibration-variant = "Linksys-MX8500";
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};
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};
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};
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&wifi {
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status = "okay";
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qcom,ath11k-calibration-variant = "Linksys-MX8500";
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};
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