f4a7ae107e
USXGMII carries the line rate to the MAC in a Clause 37 code word, so the link needs in-band signalling. Without "managed" the port is PHY managed, phylink disables in-band on the PHY, and with the PCS now honouring neg_mode neither end runs autonegotiation, so nothing crosses the system interface. Every USXGMII port in this target was missing the property: ten ports across eight boards, all of them an Aquantia PHY on copper, none of them an SFP cage. ipq8074-rt-ax89x already carried "in-band-status" on its SGMII lan8, which is why a file-level search made it look covered. Only the two ports on ipq8072-301w have been tested on hardware. The remaining eight are the same PHY family behind the same PCS, are broken today for the same reason, and cannot regress from a state where they pass no traffic, but they have not been confirmed on a board. That test ran on the 6.18 testing kernel, where phylink switches the PHY side on through phy_config_inband(). On 6.12 the PHY has no such op and 0760-net-phy-aquantia-enable-USXGMII-MAC-autoneg.patch forces the same bit unconditionally, so the end state matches, but no board has confirmed it there. Tested-by: Rudy Andram <rmandrad@gmail.com> Assisted-by: Claude:claude-opus-5 Signed-off-by: Julius Bairaktaris <julius@bairaktaris.de> Link: https://github.com/openwrt/openwrt/pull/24420 Signed-off-by: Robert Marko <robimarko@gmail.com>
438 lines
7 KiB
Text
438 lines
7 KiB
Text
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/*
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* Copyright (c) 2022, Karol Przybylski <itor@o2.pl>
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* Copyright (c) 2023, Andre Valentin <avalentin@marcant.net>
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*/
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/dts-v1/;
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#include "ipq8074.dtsi"
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#include "ipq8074-hk-cpu.dtsi"
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#include "ipq8074-ess.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/input/input.h>
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/ {
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model = "Zyxel NBG7815";
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compatible = "zyxel,nbg7815", "qcom,ipq8074";
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aliases {
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serial0 = &blsp1_uart5;
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serial1 = &blsp1_uart3;
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label-mac-device = &swport1;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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linux,code = <KEY_RESTART>;
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gpios = <&tlmm 54 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&tlmm {
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mdio_pins: mdio-pins {
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mdc {
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pins = "gpio68";
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function = "mdc";
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drive-strength = <8>;
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bias-pull-up;
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};
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mdio {
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pins = "gpio69";
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function = "mdio";
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drive-strength = <8>;
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bias-pull-up;
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};
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};
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};
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&blsp1_uart3 {
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status = "okay";
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};
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&blsp1_uart5 {
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status = "okay";
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};
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&prng {
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status = "okay";
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};
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&qpic_bam {
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status = "okay";
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};
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&blsp1_spi1 {
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pinctrl-0 = <&spi_0_pins>;
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pinctrl-names = "default";
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status = "okay";
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flash@0 {
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reg = <0>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "0:sbl1";
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reg = <0x0 0x50000>;
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read-only;
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};
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partition@50000 {
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label = "0:mibib";
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reg = <0x50000 0x10000>;
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read-only;
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};
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partition@60000 {
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label = "0:bootconfig";
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reg = <0x60000 0x20000>;
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read-only;
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};
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partition@80000 {
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label = "0:bootconfig1";
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reg = <0x80000 0x20000>;
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read-only;
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};
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partition@a0000 {
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label = "0:qsee";
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reg = <0xa0000 0x180000>;
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read-only;
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};
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partition@220000 {
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label = "0:qsee_1";
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reg = <0x220000 0x180000>;
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read-only;
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};
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partition@3a0000 {
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label = "0:devcfg";
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reg = <0x3a0000 0x10000>;
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read-only;
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};
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partition@3b0000 {
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label = "0:devcfg_1";
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reg = <0x3b0000 0x10000>;
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read-only;
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};
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partition@3c0000 {
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label = "0:apdp";
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reg = <0x3c0000 0x10000>;
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read-only;
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};
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partition@3d0000 {
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label = "0:apdp_1";
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reg = <0x3d0000 0x10000>;
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read-only;
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};
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partition@3e0000 {
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label = "0:rpm";
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reg = <0x3e0000 0x40000>;
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read-only;
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};
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partition@420000 {
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label = "0:rpm_1";
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reg = <0x420000 0x40000>;
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read-only;
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};
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partition@460000 {
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label = "0:cdt";
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reg = <0x460000 0x10000>;
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read-only;
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};
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partition@470000 {
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label = "0:cdt_1";
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reg = <0x470000 0x10000>;
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read-only;
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};
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partition@480000 {
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label = "0:appsbl";
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reg = <0x480000 0xc0000>;
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read-only;
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};
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partition@540000 {
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label = "0:appsbl_1";
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reg = <0x540000 0xc0000>;
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read-only;
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};
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partition@600000 {
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label = "0:appsblenv";
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reg = <0x600000 0x10000>;
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nvmem-layout {
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compatible = "u-boot,env";
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macaddr_lan: ethaddr {
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#nvmem-cell-cells = <1>;
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};
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};
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};
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partition@610000 {
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label = "0:art";
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reg = <0x610000 0x40000>;
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read-only;
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};
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partition@650000 {
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label = "0:ethphyfw";
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reg = <0x650000 0x80000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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aqr_fw: firmware@28 {
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/* Skip the QCOM MBN Header of 40 bytes */
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reg = <0x28 0x5f402>;
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};
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};
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};
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partition@6d0000 {
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label = "0:crt";
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reg = <0x6d0000 0x10000>;
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read-only;
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};
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partition@6e0000 {
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label = "dual_flag";
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reg = <0x6e0000 0x10000>;
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};
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partition@6f0000 {
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label = "reserved";
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reg = <0x6f0000 0x110000>;
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read-only;
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};
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};
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};
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};
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&mdio {
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status = "okay";
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pinctrl-0 = <&mdio_pins>;
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pinctrl-names = "default";
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reset-gpios = <&tlmm 37 GPIO_ACTIVE_LOW>;
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ethernet-phy-package@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,qca8075-package";
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reg = <0>;
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qca8075_0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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};
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qca8075_1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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qca8075_2: ethernet-phy@2 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <2>;
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};
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qca8075_3: ethernet-phy@3 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <3>;
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};
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};
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qca8081: ethernet-phy@28 {
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compatible = "ethernet-phy-id004d.d101";
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reg = <28>;
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reset-deassert-us = <10000>;
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reset-gpios = <&tlmm 31 GPIO_ACTIVE_LOW>;
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};
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aqr113c: ethernet-phy@5 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <8>;
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reset-gpios = <&tlmm 63 GPIO_ACTIVE_LOW>;
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nvmem-cells = <&aqr_fw>;
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nvmem-cell-names = "firmware";
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};
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};
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&uniphy0 {
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status = "okay";
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};
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&uniphy1 {
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status = "okay";
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};
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&uniphy2 {
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status = "okay";
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};
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&switch {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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ethernet = <&edma>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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swport1: port@1 {
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reg = <1>;
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label = "lan1";
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phy-handle = <&qca8075_0>;
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phy-mode = "psgmii";
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pcs-handle = <&uniphy0 0>;
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nvmem-cells = <&macaddr_lan 0>;
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nvmem-cell-names = "mac-address";
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};
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swport2: port@2 {
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reg = <2>;
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label = "lan2";
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phy-handle = <&qca8075_1>;
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phy-mode = "psgmii";
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pcs-handle = <&uniphy0 1>;
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nvmem-cells = <&macaddr_lan 0>;
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nvmem-cell-names = "mac-address";
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};
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swport3: port@3 {
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reg = <3>;
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label = "lan3";
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phy-handle = <&qca8075_2>;
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phy-mode = "psgmii";
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pcs-handle = <&uniphy0 2>;
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nvmem-cells = <&macaddr_lan 0>;
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nvmem-cell-names = "mac-address";
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};
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swport4: port@4 {
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reg = <4>;
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label = "lan4";
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phy-handle = <&qca8075_3>;
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phy-mode = "psgmii";
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pcs-handle = <&uniphy0 3>;
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nvmem-cells = <&macaddr_lan 0>;
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nvmem-cell-names = "mac-address";
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};
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swport5: port@5 {
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reg = <5>;
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label = "wan";
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phy-handle = <&qca8081>;
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phy-mode = "2500base-x";
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pcs-handle = <&uniphy1 0>;
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nvmem-cells = <&macaddr_lan 1>;
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nvmem-cell-names = "mac-address";
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};
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swport6: port@6 {
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reg = <6>;
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label = "10g";
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phy-handle = <&aqr113c>;
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phy-mode = "usxgmii";
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managed = "in-band-status";
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pcs-handle = <&uniphy2 0>;
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nvmem-cells = <&macaddr_lan 0>;
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nvmem-cell-names = "mac-address";
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};
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};
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};
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&edma {
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status = "okay";
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};
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&blsp1_i2c2 {
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pinctrl-0 = <&i2c_0_pins>;
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pinctrl-names = "default";
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status = "okay";
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tmp103@70 {
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compatible = "ti,tmp103";
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reg = <0x70>;
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};
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};
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&sdhc_1 {
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status = "okay";
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/* unstable, problem with the hs400 > h200 speed switch */
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/delete-property/ mmc-hs400-1_8v;
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mmc-hs200-1_8v;
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mmc-ddr-1_8v;
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vqmmc-supply = <&l11>;
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};
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&ssphy_0 {
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status = "okay";
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};
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&qusb_phy_0 {
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status = "okay";
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};
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&ssphy_1 {
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status = "okay";
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};
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&qusb_phy_1 {
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status = "okay";
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};
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&usb_0 {
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status = "okay";
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};
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&usb_1 {
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status = "okay";
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};
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&wifi {
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status = "okay";
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qcom,ath11k-calibration-variant = "Zyxel-NBG7815";
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};
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