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RziL: fix incorrect naming of fabs as fpos (#5955)

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* rzil: fix incorrect output

* update test cases
This commit is contained in:
Ehab-24 2026-02-25 21:04:45 +05:00 committed by GitHub
parent d6b5340cda
commit 09cab090f6
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GPG key ID: B5690EEEBB952194
5 changed files with 28 additions and 28 deletions
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2
librz/il/il_export_string.c
View file

@ -388,7 +388,7 @@ static void il_opdmp_fneg(RzILOpPure *op, RzStrBuf *sb, int pad) {
}
static void il_opdmp_fabs(RzILOpPure *op, RzStrBuf *sb, int pad) {
il_op_param_1("fpos", op->op.fabs, f);
il_op_param_1("fabs", op->op.fabs, f);
}
static void il_opdmp_fcast_int(RzILOpPure *op, RzStrBuf *sb, int pad) {

14
test/db/asm/arm_32
View file

@ -683,11 +683,11 @@ d "vbsl d0, d1, d2" 120111f3 0x0 (set d0 (| (& (var d1) (var d0)) (& (var d2) (~
d "vbsl q0, q1, q2" 540112f3 0x0 (seq (set d0 (cast 64 false (| (& (append (var d3) (var d2)) (append (var d1) (var d0))) (& (append (var d5) (var d4)) (~ (append (var d1) (var d0))))))) (set d1 (cast 64 false (>> (| (& (append (var d3) (var d2)) (append (var d1) (var d0))) (& (append (var d5) (var d4)) (~ (append (var d1) (var d0))))) (bv 8 0x40) false))))
d "vmvn d0, d1" 8105b0f3 0x0 (set d0 (~ (var d1)))
d "vmvn q0, q1" c205b0f3 0x0 (seq (set d0 (cast 64 false (~ (append (var d3) (var d2))))) (set d1 (cast 64 false (>> (~ (append (var d3) (var d2))) (bv 8 0x40) false))))
d "vacge.f32 d0, d1, d2" 120e01f3 0x0 (seq empty (set d0 (<< (cast 64 false (ite (! (<. (fpos (float 0 (cast 32 false (>> (var d1) (bv 8 0x0) false)) )) (fpos (float 0 (cast 32 false (>> (var d2) (bv 8 0x0) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x0) false)) (set d0 (<< (cast 64 false (ite (! (<. (fpos (float 0 (cast 32 false (>> (var d1) (bv 8 0x20) false)) )) (fpos (float 0 (cast 32 false (>> (var d2) (bv 8 0x20) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x20) false)))
d "vacge.f32 d0, d0, d1" 110e00f3 0x0 (seq empty (set d0 (<< (cast 64 false (ite (! (<. (fpos (float 0 (cast 32 false (>> (var d0) (bv 8 0x0) false)) )) (fpos (float 0 (cast 32 false (>> (var d1) (bv 8 0x0) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x0) false)) (set d0 (<< (cast 64 false (ite (! (<. (fpos (float 0 (cast 32 false (>> (var d0) (bv 8 0x20) false)) )) (fpos (float 0 (cast 32 false (>> (var d1) (bv 8 0x20) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x20) false)))
d "vacge.f32 q0, q1, q2" 540e02f3 0x0 (seq empty (set d0 (cast 64 false (<< (cast 128 false (ite (! (<. (fpos (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x0) false)) )) (fpos (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x0) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x0) false))) (set d1 (cast 64 false (>> (<< (cast 128 false (ite (! (<. (fpos (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x0) false)) )) (fpos (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x0) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x0) false) (bv 8 0x40) false))) (set d0 (cast 64 false (<< (cast 128 false (ite (! (<. (fpos (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x20) false)) )) (fpos (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x20) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x20) false))) (set d1 (cast 64 false (>> (<< (cast 128 false (ite (! (<. (fpos (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x20) false)) )) (fpos (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x20) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x20) false) (bv 8 0x40) false))) (set d0 (cast 64 false (<< (cast 128 false (ite (! (<. (fpos (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x40) false)) )) (fpos (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x40) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x40) false))) (set d1 (cast 64 false (>> (<< (cast 128 false (ite (! (<. (fpos (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x40) false)) )) (fpos (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x40) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x40) false) (bv 8 0x40) false))) (set d0 (cast 64 false (<< (cast 128 false (ite (! (<. (fpos (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x60) false)) )) (fpos (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x60) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x60) false))) (set d1 (cast 64 false (>> (<< (cast 128 false (ite (! (<. (fpos (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x60) false)) )) (fpos (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x60) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x60) false) (bv 8 0x40) false))))
d "vacgt.f32 d0, d1, d2" 120e21f3 0x0 (seq empty (set d0 (<< (cast 64 false (ite (<. (fpos (float 0 (cast 32 false (>> (var d2) (bv 8 0x0) false)) )) (fpos (float 0 (cast 32 false (>> (var d1) (bv 8 0x0) false)) ))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x0) false)) (set d0 (<< (cast 64 false (ite (<. (fpos (float 0 (cast 32 false (>> (var d2) (bv 8 0x20) false)) )) (fpos (float 0 (cast 32 false (>> (var d1) (bv 8 0x20) false)) ))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x20) false)))
d "vacgt.f32 q0, q1, q2" 540e22f3 0x0 (seq empty (set d0 (cast 64 false (<< (cast 128 false (ite (<. (fpos (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x0) false)) )) (fpos (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x0) false)) ))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x0) false))) (set d1 (cast 64 false (>> (<< (cast 128 false (ite (<. (fpos (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x0) false)) )) (fpos (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x0) false)) ))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x0) false) (bv 8 0x40) false))) (set d0 (cast 64 false (<< (cast 128 false (ite (<. (fpos (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x20) false)) )) (fpos (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x20) false)) ))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x20) false))) (set d1 (cast 64 false (>> (<< (cast 128 false (ite (<. (fpos (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x20) false)) )) (fpos (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x20) false)) ))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x20) false) (bv 8 0x40) false))) (set d0 (cast 64 false (<< (cast 128 false (ite (<. (fpos (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x40) false)) )) (fpos (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x40) false)) ))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x40) false))) (set d1 (cast 64 false (>> (<< (cast 128 false (ite (<. (fpos (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x40) false)) )) (fpos (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x40) false)) ))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x40) false) (bv 8 0x40) false))) (set d0 (cast 64 false (<< (cast 128 false (ite (<. (fpos (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x60) false)) )) (fpos (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x60) false)) ))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x60) false))) (set d1 (cast 64 false (>> (<< (cast 128 false (ite (<. (fpos (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x60) false)) )) (fpos (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x60) false)) ))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x60) false) (bv 8 0x40) false))))
d "vacge.f32 d0, d1, d2" 120e01f3 0x0 (seq empty (set d0 (<< (cast 64 false (ite (! (<. (fabs (float 0 (cast 32 false (>> (var d1) (bv 8 0x0) false)) )) (fabs (float 0 (cast 32 false (>> (var d2) (bv 8 0x0) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x0) false)) (set d0 (<< (cast 64 false (ite (! (<. (fabs (float 0 (cast 32 false (>> (var d1) (bv 8 0x20) false)) )) (fabs (float 0 (cast 32 false (>> (var d2) (bv 8 0x20) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x20) false)))
d "vacge.f32 d0, d0, d1" 110e00f3 0x0 (seq empty (set d0 (<< (cast 64 false (ite (! (<. (fabs (float 0 (cast 32 false (>> (var d0) (bv 8 0x0) false)) )) (fabs (float 0 (cast 32 false (>> (var d1) (bv 8 0x0) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x0) false)) (set d0 (<< (cast 64 false (ite (! (<. (fabs (float 0 (cast 32 false (>> (var d0) (bv 8 0x20) false)) )) (fabs (float 0 (cast 32 false (>> (var d1) (bv 8 0x20) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x20) false)))
d "vacge.f32 q0, q1, q2" 540e02f3 0x0 (seq empty (set d0 (cast 64 false (<< (cast 128 false (ite (! (<. (fabs (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x0) false)) )) (fabs (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x0) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x0) false))) (set d1 (cast 64 false (>> (<< (cast 128 false (ite (! (<. (fabs (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x0) false)) )) (fabs (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x0) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x0) false) (bv 8 0x40) false))) (set d0 (cast 64 false (<< (cast 128 false (ite (! (<. (fabs (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x20) false)) )) (fabs (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x20) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x20) false))) (set d1 (cast 64 false (>> (<< (cast 128 false (ite (! (<. (fabs (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x20) false)) )) (fabs (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x20) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x20) false) (bv 8 0x40) false))) (set d0 (cast 64 false (<< (cast 128 false (ite (! (<. (fabs (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x40) false)) )) (fabs (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x40) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x40) false))) (set d1 (cast 64 false (>> (<< (cast 128 false (ite (! (<. (fabs (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x40) false)) )) (fabs (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x40) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x40) false) (bv 8 0x40) false))) (set d0 (cast 64 false (<< (cast 128 false (ite (! (<. (fabs (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x60) false)) )) (fabs (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x60) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x60) false))) (set d1 (cast 64 false (>> (<< (cast 128 false (ite (! (<. (fabs (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x60) false)) )) (fabs (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x60) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x60) false) (bv 8 0x40) false))))
d "vacgt.f32 d0, d1, d2" 120e21f3 0x0 (seq empty (set d0 (<< (cast 64 false (ite (<. (fabs (float 0 (cast 32 false (>> (var d2) (bv 8 0x0) false)) )) (fabs (float 0 (cast 32 false (>> (var d1) (bv 8 0x0) false)) ))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x0) false)) (set d0 (<< (cast 64 false (ite (<. (fabs (float 0 (cast 32 false (>> (var d2) (bv 8 0x20) false)) )) (fabs (float 0 (cast 32 false (>> (var d1) (bv 8 0x20) false)) ))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x20) false)))
d "vacgt.f32 q0, q1, q2" 540e22f3 0x0 (seq empty (set d0 (cast 64 false (<< (cast 128 false (ite (<. (fabs (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x0) false)) )) (fabs (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x0) false)) ))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x0) false))) (set d1 (cast 64 false (>> (<< (cast 128 false (ite (<. (fabs (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x0) false)) )) (fabs (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x0) false)) ))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x0) false) (bv 8 0x40) false))) (set d0 (cast 64 false (<< (cast 128 false (ite (<. (fabs (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x20) false)) )) (fabs (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x20) false)) ))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x20) false))) (set d1 (cast 64 false (>> (<< (cast 128 false (ite (<. (fabs (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x20) false)) )) (fabs (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x20) false)) ))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x20) false) (bv 8 0x40) false))) (set d0 (cast 64 false (<< (cast 128 false (ite (<. (fabs (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x40) false)) )) (fabs (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x40) false)) ))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x40) false))) (set d1 (cast 64 false (>> (<< (cast 128 false (ite (<. (fabs (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x40) false)) )) (fabs (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x40) false)) ))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x40) false) (bv 8 0x40) false))) (set d0 (cast 64 false (<< (cast 128 false (ite (<. (fabs (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x60) false)) )) (fabs (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x60) false)) ))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x60) false))) (set d1 (cast 64 false (>> (<< (cast 128 false (ite (<. (fabs (float 0 (cast 32 false (>> (append (var d5) (var d4)) (bv 8 0x60) false)) )) (fabs (float 0 (cast 32 false (>> (append (var d3) (var d2)) (bv 8 0x60) false)) ))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x60) false) (bv 8 0x40) false))))
d "vceq.i8 d0, d1, d2" 120801f3 0x0 (seq empty (set d0 (<< (cast 64 false (ite (== (cast 8 false (>> (var d1) (bv 8 0x0) false)) (cast 8 false (>> (var d2) (bv 8 0x0) false))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x0) false)) (set d0 (<< (cast 64 false (ite (== (cast 8 false (>> (var d1) (bv 8 0x8) false)) (cast 8 false (>> (var d2) (bv 8 0x8) false))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x8) false)) (set d0 (<< (cast 64 false (ite (== (cast 8 false (>> (var d1) (bv 8 0x10) false)) (cast 8 false (>> (var d2) (bv 8 0x10) false))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x10) false)) (set d0 (<< (cast 64 false (ite (== (cast 8 false (>> (var d1) (bv 8 0x18) false)) (cast 8 false (>> (var d2) (bv 8 0x18) false))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x18) false)) (set d0 (<< (cast 64 false (ite (== (cast 8 false (>> (var d1) (bv 8 0x20) false)) (cast 8 false (>> (var d2) (bv 8 0x20) false))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x20) false)) (set d0 (<< (cast 64 false (ite (== (cast 8 false (>> (var d1) (bv 8 0x28) false)) (cast 8 false (>> (var d2) (bv 8 0x28) false))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x28) false)) (set d0 (<< (cast 64 false (ite (== (cast 8 false (>> (var d1) (bv 8 0x30) false)) (cast 8 false (>> (var d2) (bv 8 0x30) false))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x30) false)) (set d0 (<< (cast 64 false (ite (== (cast 8 false (>> (var d1) (bv 8 0x38) false)) (cast 8 false (>> (var d2) (bv 8 0x38) false))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x38) false)))
d "vceq.i16 d0, d1, d2" 120811f3 0x0 (seq empty (set d0 (<< (cast 64 false (ite (== (cast 16 false (>> (var d1) (bv 8 0x0) false)) (cast 16 false (>> (var d2) (bv 8 0x0) false))) (~ (bv 16 0x0)) (bv 16 0x0))) (bv 8 0x0) false)) (set d0 (<< (cast 64 false (ite (== (cast 16 false (>> (var d1) (bv 8 0x10) false)) (cast 16 false (>> (var d2) (bv 8 0x10) false))) (~ (bv 16 0x0)) (bv 16 0x0))) (bv 8 0x10) false)) (set d0 (<< (cast 64 false (ite (== (cast 16 false (>> (var d1) (bv 8 0x20) false)) (cast 16 false (>> (var d2) (bv 8 0x20) false))) (~ (bv 16 0x0)) (bv 16 0x0))) (bv 8 0x20) false)) (set d0 (<< (cast 64 false (ite (== (cast 16 false (>> (var d1) (bv 8 0x30) false)) (cast 16 false (>> (var d2) (bv 8 0x30) false))) (~ (bv 16 0x0)) (bv 16 0x0))) (bv 8 0x30) false)))
d "vceq.i32 d0, d1, d2" 120821f3 0x0 (seq empty (set d0 (<< (cast 64 false (ite (== (cast 32 false (>> (var d1) (bv 8 0x0) false)) (cast 32 false (>> (var d2) (bv 8 0x0) false))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x0) false)) (set d0 (<< (cast 64 false (ite (== (cast 32 false (>> (var d1) (bv 8 0x20) false)) (cast 32 false (>> (var d2) (bv 8 0x20) false))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x20) false)))
@ -759,8 +759,8 @@ d "vldr s0, [fp, -0x14]" 050a1bed 0x0 (set d0 (| (& (var d0) (bv 64 0xffffffff00
d "vstr s1, [fp, 0x30]" 0c0acbed 0x0 (storew 0 (+ (var r11) (bv 32 0x30)) (cast 32 false (>> (var d0) (bv 7 0x20) false)))
d "vldr s0, [sp, 8]" 020a9ded 0x0 (set d0 (| (& (var d0) (bv 64 0xffffffff00000000)) (cast 64 false (loadw 0 32 (+ (var sp) (bv 32 0x8))))))
d "vldr d0, [r2]" 000b92ed 0x0 (set d0 (loadw 0 64 (var r2)))
d "vabs.f32 s0, s15" e70ab0ee 0x0 (set d0 (| (& (var d0) (bv 64 0xffffffff00000000)) (cast 64 false (fbits (fpos (float 0 (cast 32 false (>> (var d7) (bv 7 0x20) false)) ))))))
d "vabs.f64 d1, d8" c81bb0ee 0x0 (set d1 (fbits (fpos (float 1 (var d8) ))))
d "vabs.f32 s0, s15" e70ab0ee 0x0 (set d0 (| (& (var d0) (bv 64 0xffffffff00000000)) (cast 64 false (fbits (fabs (float 0 (cast 32 false (>> (var d7) (bv 7 0x20) false)) ))))))
d "vabs.f64 d1, d8" c81bb0ee 0x0 (set d1 (fbits (fabs (float 1 (var d8) ))))
d "vswp d0, d1" 0100b2f3 0x0 (seq (set d0 (var d1)) (set d1 (var d0)))
d "vswp q2, q3" 4640b2f3 0x0 (seq (set d4 (cast 64 false (append (var d7) (var d6)))) (set d5 (cast 64 false (>> (append (var d7) (var d6)) (bv 8 0x40) false))) (set d6 (cast 64 false (append (var d5) (var d4)))) (set d7 (cast 64 false (>> (append (var d5) (var d4)) (bv 8 0x40) false))))
d "vzip.8 d0, d1" 8101b2f3 0x0 (seq (set d0 (cast 64 false (| (| (| (| (| (| (| (| (bv 128 0x0) (<< (| (<< (cast 128 false (cast 8 false (>> (var d1) (bv 8 0x0) false))) (bv 8 0x8) false) (cast 128 false (cast 8 false (>> (var d0) (bv 8 0x0) false)))) (bv 32 0x10) false)) (<< (| (<< (cast 128 false (cast 8 false (>> (var d1) (bv 8 0x8) false))) (bv 8 0x8) false) (cast 128 false (cast 8 false (>> (var d0) (bv 8 0x8) false)))) (bv 32 0x10) false)) (<< (| (<< (cast 128 false (cast 8 false (>> (var d1) (bv 8 0x10) false))) (bv 8 0x8) false) (cast 128 false (cast 8 false (>> (var d0) (bv 8 0x10) false)))) (bv 32 0x10) false)) (<< (| (<< (cast 128 false (cast 8 false (>> (var d1) (bv 8 0x18) false))) (bv 8 0x8) false) (cast 128 false (cast 8 false (>> (var d0) (bv 8 0x18) false)))) (bv 32 0x10) false)) (<< (| (<< (cast 128 false (cast 8 false (>> (var d1) (bv 8 0x20) false))) (bv 8 0x8) false) (cast 128 false (cast 8 false (>> (var d0) (bv 8 0x20) false)))) (bv 32 0x10) false)) (<< (| (<< (cast 128 false (cast 8 false (>> (var d1) (bv 8 0x28) false))) (bv 8 0x8) false) (cast 128 false (cast 8 false (>> (var d0) (bv 8 0x28) false)))) (bv 32 0x10) false)) (<< (| (<< (cast 128 false (cast 8 false (>> (var d1) (bv 8 0x30) false))) (bv 8 0x8) false) (cast 128 false (cast 8 false (>> (var d0) (bv 8 0x30) false)))) (bv 32 0x10) false)) (<< (| (<< (cast 128 false (cast 8 false (>> (var d1) (bv 8 0x38) false))) (bv 8 0x8) false) (cast 128 false (cast 8 false (>> (var d0) (bv 8 0x38) false)))) (bv 32 0x10) false)))) (set d1 (cast 64 false (>> (| (| (| (| (| (| (| (| (bv 128 0x0) (<< (| (<< (cast 128 false (cast 8 false (>> (var d1) (bv 8 0x0) false))) (bv 8 0x8) false) (cast 128 false (cast 8 false (>> (var d0) (bv 8 0x0) false)))) (bv 32 0x10) false)) (<< (| (<< (cast 128 false (cast 8 false (>> (var d1) (bv 8 0x8) false))) (bv 8 0x8) false) (cast 128 false (cast 8 false (>> (var d0) (bv 8 0x8) false)))) (bv 32 0x10) false)) (<< (| (<< (cast 128 false (cast 8 false (>> (var d1) (bv 8 0x10) false))) (bv 8 0x8) false) (cast 128 false (cast 8 false (>> (var d0) (bv 8 0x10) false)))) (bv 32 0x10) false)) (<< (| (<< (cast 128 false (cast 8 false (>> (var d1) (bv 8 0x18) false))) (bv 8 0x8) false) (cast 128 false (cast 8 false (>> (var d0) (bv 8 0x18) false)))) (bv 32 0x10) false)) (<< (| (<< (cast 128 false (cast 8 false (>> (var d1) (bv 8 0x20) false))) (bv 8 0x8) false) (cast 128 false (cast 8 false (>> (var d0) (bv 8 0x20) false)))) (bv 32 0x10) false)) (<< (| (<< (cast 128 false (cast 8 false (>> (var d1) (bv 8 0x28) false))) (bv 8 0x8) false) (cast 128 false (cast 8 false (>> (var d0) (bv 8 0x28) false)))) (bv 32 0x10) false)) (<< (| (<< (cast 128 false (cast 8 false (>> (var d1) (bv 8 0x30) false))) (bv 8 0x8) false) (cast 128 false (cast 8 false (>> (var d0) (bv 8 0x30) false)))) (bv 32 0x10) false)) (<< (| (<< (cast 128 false (cast 8 false (>> (var d1) (bv 8 0x38) false))) (bv 8 0x8) false) (cast 128 false (cast 8 false (>> (var d0) (bv 8 0x38) false)))) (bv 32 0x10) false)) (bv 8 0x8) false))))

6
test/db/asm/sparc_v9_64
View file

@ -264,9 +264,9 @@ dE "fstoq f0, f4" 89a019a0 0x0 (seq (set bv (fbits (fconvert ieee754-bin128 rna
dE "fnegs f0, f0" 81a000a0 0x0 (seq (set bv (fbits (fneg (float 0 (var f0) )))) (set f0 (cast 32 false (var bv))) (set fprs (| (var fprs) (<< (bv 3 0x1) (bv 8 0x0) false))))
dE "fnegd f32, f0" 81a000c1 0x0 (seq (set bv (fbits (fneg (float 1 (var f32) )))) (set f1 (cast 32 false (var bv))) (set fprs (| (var fprs) (<< (bv 3 0x1) (bv 8 0x0) false))) (set f0 (cast 32 false (>> (var bv) (bv 8 0x20) false))) (set fprs (| (var fprs) (<< (bv 3 0x1) (bv 8 0x0) false))))
dE "fnegq f60, f0" 81a000fd 0x0 (seq (set bv (fbits (fneg (float 3 (append (var f60) (var f62)) )))) (set f3 (cast 32 false (var bv))) (set fprs (| (var fprs) (<< (bv 3 0x1) (bv 8 0x0) false))) (set f2 (cast 32 false (>> (var bv) (bv 8 0x20) false))) (set fprs (| (var fprs) (<< (bv 3 0x1) (bv 8 0x0) false))) (set f1 (cast 32 false (>> (var bv) (bv 8 0x40) false))) (set fprs (| (var fprs) (<< (bv 3 0x1) (bv 8 0x0) false))) (set f0 (cast 32 false (>> (var bv) (bv 8 0x60) false))) (set fprs (| (var fprs) (<< (bv 3 0x1) (bv 8 0x0) false))))
dE "fabss f0, f0" 81a00120 0x0 (seq (set bv (fbits (fpos (float 0 (var f0) )))) (set f0 (cast 32 false (var bv))) (set fprs (| (var fprs) (<< (bv 3 0x1) (bv 8 0x0) false))))
dE "fabsd f32, f0" 81a00141 0x0 (seq (set bv (fbits (fpos (float 1 (var f32) )))) (set f1 (cast 32 false (var bv))) (set fprs (| (var fprs) (<< (bv 3 0x1) (bv 8 0x0) false))) (set f0 (cast 32 false (>> (var bv) (bv 8 0x20) false))) (set fprs (| (var fprs) (<< (bv 3 0x1) (bv 8 0x0) false))))
dE "fabsq f60, f0" 81a0017d 0x0 (seq (set bv (fbits (fpos (float 3 (append (var f60) (var f62)) )))) (set f3 (cast 32 false (var bv))) (set fprs (| (var fprs) (<< (bv 3 0x1) (bv 8 0x0) false))) (set f2 (cast 32 false (>> (var bv) (bv 8 0x20) false))) (set fprs (| (var fprs) (<< (bv 3 0x1) (bv 8 0x0) false))) (set f1 (cast 32 false (>> (var bv) (bv 8 0x40) false))) (set fprs (| (var fprs) (<< (bv 3 0x1) (bv 8 0x0) false))) (set f0 (cast 32 false (>> (var bv) (bv 8 0x60) false))) (set fprs (| (var fprs) (<< (bv 3 0x1) (bv 8 0x0) false))))
dE "fabss f0, f0" 81a00120 0x0 (seq (set bv (fbits (fabs (float 0 (var f0) )))) (set f0 (cast 32 false (var bv))) (set fprs (| (var fprs) (<< (bv 3 0x1) (bv 8 0x0) false))))
dE "fabsd f32, f0" 81a00141 0x0 (seq (set bv (fbits (fabs (float 1 (var f32) )))) (set f1 (cast 32 false (var bv))) (set fprs (| (var fprs) (<< (bv 3 0x1) (bv 8 0x0) false))) (set f0 (cast 32 false (>> (var bv) (bv 8 0x20) false))) (set fprs (| (var fprs) (<< (bv 3 0x1) (bv 8 0x0) false))))
dE "fabsq f60, f0" 81a0017d 0x0 (seq (set bv (fbits (fabs (float 3 (append (var f60) (var f62)) )))) (set f3 (cast 32 false (var bv))) (set fprs (| (var fprs) (<< (bv 3 0x1) (bv 8 0x0) false))) (set f2 (cast 32 false (>> (var bv) (bv 8 0x20) false))) (set fprs (| (var fprs) (<< (bv 3 0x1) (bv 8 0x0) false))) (set f1 (cast 32 false (>> (var bv) (bv 8 0x40) false))) (set fprs (| (var fprs) (<< (bv 3 0x1) (bv 8 0x0) false))) (set f0 (cast 32 false (>> (var bv) (bv 8 0x60) false))) (set fprs (| (var fprs) (<< (bv 3 0x1) (bv 8 0x0) false))))
dE "fone f32" 83b00fc0 0x0 (seq (set bv (bv 64 0xffffffffffffffff)) (set f32 (cast 64 false (var bv))) (set fprs (| (var fprs) (<< (bv 3 0x1) (bv 8 0x1) false))))
dE "fones f0" 81b00fe0 0x0 (seq (set bv (bv 32 0xffffffff)) (set f0 (cast 32 false (var bv))) (set fprs (| (var fprs) (<< (bv 3 0x1) (bv 8 0x0) false))))

30
test/db/asm/tricore
View file

@ -83,9 +83,9 @@ d "add.a a4, a12" 30c4 0x000000 (set a4 (+ (var a4) (var a12)))
d "add.b d2, d3, d14" 0be30024 0x000000 (seq (set result_byte3 (+ (cast 8 false (& (>> (var d3) (bv 32 0x18) false) (bv 32 0xff))) (cast 8 false (& (>> (var d14) (bv 32 0x18) false) (bv 32 0xff))))) (set result_byte2 (+ (cast 8 false (& (>> (var d3) (bv 32 0x10) false) (bv 32 0xff))) (cast 8 false (& (>> (var d14) (bv 32 0x10) false) (bv 32 0xff))))) (set result_byte1 (+ (cast 8 false (& (>> (var d3) (bv 32 0x8) false) (bv 32 0xff))) (cast 8 false (& (>> (var d14) (bv 32 0x8) false) (bv 32 0xff))))) (set result_byte0 (+ (cast 8 false (& (>> (var d3) (bv 32 0x0) false) (bv 32 0xff))) (cast 8 false (& (>> (var d14) (bv 32 0x0) false) (bv 32 0xff))))) (set result (| (cast 32 false (<< (var result_byte3) (bv 32 0x18) false)) (| (cast 32 false (<< (var result_byte2) (bv 32 0x10) false)) (| (cast 32 false (<< (var result_byte1) (bv 32 0x8) false)) (cast 32 false (var result_byte0)))))) (set d2 (var result)) (set ov3 (|| (! (ule (var result_byte3) (bv 8 0x7f))) (&& (sle (var result_byte3) (bv 8 0x80)) (! (== (var result_byte3) (bv 8 0x80)))))) (set ov2 (|| (! (ule (var result_byte2) (bv 8 0x7f))) (&& (sle (var result_byte2) (bv 8 0x80)) (! (== (var result_byte2) (bv 8 0x80)))))) (set ov1 (|| (! (ule (var result_byte1) (bv 8 0x7f))) (&& (sle (var result_byte1) (bv 8 0x80)) (! (== (var result_byte1) (bv 8 0x80)))))) (set ov0 (|| (! (ule (var result_byte0) (bv 8 0x7f))) (&& (sle (var result_byte0) (bv 8 0x80)) (! (== (var result_byte0) (bv 8 0x80)))))) (set overflow (|| (|| (var ov1) (var ov0)) (|| (var ov3) (var ov2)))) (set aov3 (^^ (! (is_zero (& (>> (var result_byte3) (bv 8 0x7) false) (bv 8 0x1)))) (! (is_zero (& (>> (var result_byte3) (bv 8 0x6) false) (bv 8 0x1)))))) (set aov2 (^^ (! (is_zero (& (>> (var result_byte2) (bv 8 0x7) false) (bv 8 0x1)))) (! (is_zero (& (>> (var result_byte2) (bv 8 0x6) false) (bv 8 0x1)))))) (set aov1 (^^ (! (is_zero (& (>> (var result_byte1) (bv 8 0x7) false) (bv 8 0x1)))) (! (is_zero (& (>> (var result_byte1) (bv 8 0x6) false) (bv 8 0x1)))))) (set aov0 (^^ (! (is_zero (& (>> (var result_byte0) (bv 8 0x7) false) (bv 8 0x1)))) (! (is_zero (& (>> (var result_byte0) (bv 8 0x6) false) (bv 8 0x1)))))) (set advanced_overflow (|| (|| (var aov1) (var aov0)) (|| (var aov3) (var aov2)))) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (ite (var overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1e) false))) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (ite (var advanced_overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1c) false))) (branch (var overflow) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (branch (var advanced_overflow) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop))
d "add.b d8, d4, d11" 0bb40084 0x000000 (seq (set result_byte3 (+ (cast 8 false (& (>> (var d4) (bv 32 0x18) false) (bv 32 0xff))) (cast 8 false (& (>> (var d11) (bv 32 0x18) false) (bv 32 0xff))))) (set result_byte2 (+ (cast 8 false (& (>> (var d4) (bv 32 0x10) false) (bv 32 0xff))) (cast 8 false (& (>> (var d11) (bv 32 0x10) false) (bv 32 0xff))))) (set result_byte1 (+ (cast 8 false (& (>> (var d4) (bv 32 0x8) false) (bv 32 0xff))) (cast 8 false (& (>> (var d11) (bv 32 0x8) false) (bv 32 0xff))))) (set result_byte0 (+ (cast 8 false (& (>> (var d4) (bv 32 0x0) false) (bv 32 0xff))) (cast 8 false (& (>> (var d11) (bv 32 0x0) false) (bv 32 0xff))))) (set result (| (cast 32 false (<< (var result_byte3) (bv 32 0x18) false)) (| (cast 32 false (<< (var result_byte2) (bv 32 0x10) false)) (| (cast 32 false (<< (var result_byte1) (bv 32 0x8) false)) (cast 32 false (var result_byte0)))))) (set d8 (var result)) (set ov3 (|| (! (ule (var result_byte3) (bv 8 0x7f))) (&& (sle (var result_byte3) (bv 8 0x80)) (! (== (var result_byte3) (bv 8 0x80)))))) (set ov2 (|| (! (ule (var result_byte2) (bv 8 0x7f))) (&& (sle (var result_byte2) (bv 8 0x80)) (! (== (var result_byte2) (bv 8 0x80)))))) (set ov1 (|| (! (ule (var result_byte1) (bv 8 0x7f))) (&& (sle (var result_byte1) (bv 8 0x80)) (! (== (var result_byte1) (bv 8 0x80)))))) (set ov0 (|| (! (ule (var result_byte0) (bv 8 0x7f))) (&& (sle (var result_byte0) (bv 8 0x80)) (! (== (var result_byte0) (bv 8 0x80)))))) (set overflow (|| (|| (var ov1) (var ov0)) (|| (var ov3) (var ov2)))) (set aov3 (^^ (! (is_zero (& (>> (var result_byte3) (bv 8 0x7) false) (bv 8 0x1)))) (! (is_zero (& (>> (var result_byte3) (bv 8 0x6) false) (bv 8 0x1)))))) (set aov2 (^^ (! (is_zero (& (>> (var result_byte2) (bv 8 0x7) false) (bv 8 0x1)))) (! (is_zero (& (>> (var result_byte2) (bv 8 0x6) false) (bv 8 0x1)))))) (set aov1 (^^ (! (is_zero (& (>> (var result_byte1) (bv 8 0x7) false) (bv 8 0x1)))) (! (is_zero (& (>> (var result_byte1) (bv 8 0x6) false) (bv 8 0x1)))))) (set aov0 (^^ (! (is_zero (& (>> (var result_byte0) (bv 8 0x7) false) (bv 8 0x1)))) (! (is_zero (& (>> (var result_byte0) (bv 8 0x6) false) (bv 8 0x1)))))) (set advanced_overflow (|| (|| (var aov1) (var aov0)) (|| (var aov3) (var aov2)))) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (ite (var overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1e) false))) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (ite (var advanced_overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1c) false))) (branch (var overflow) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (branch (var advanced_overflow) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop))
d "add.b d10, d7, d13" 0bd700a4 0x000000 (seq (set result_byte3 (+ (cast 8 false (& (>> (var d7) (bv 32 0x18) false) (bv 32 0xff))) (cast 8 false (& (>> (var d13) (bv 32 0x18) false) (bv 32 0xff))))) (set result_byte2 (+ (cast 8 false (& (>> (var d7) (bv 32 0x10) false) (bv 32 0xff))) (cast 8 false (& (>> (var d13) (bv 32 0x10) false) (bv 32 0xff))))) (set result_byte1 (+ (cast 8 false (& (>> (var d7) (bv 32 0x8) false) (bv 32 0xff))) (cast 8 false (& (>> (var d13) (bv 32 0x8) false) (bv 32 0xff))))) (set result_byte0 (+ (cast 8 false (& (>> (var d7) (bv 32 0x0) false) (bv 32 0xff))) (cast 8 false (& (>> (var d13) (bv 32 0x0) false) (bv 32 0xff))))) (set result (| (cast 32 false (<< (var result_byte3) (bv 32 0x18) false)) (| (cast 32 false (<< (var result_byte2) (bv 32 0x10) false)) (| (cast 32 false (<< (var result_byte1) (bv 32 0x8) false)) (cast 32 false (var result_byte0)))))) (set d10 (var result)) (set ov3 (|| (! (ule (var result_byte3) (bv 8 0x7f))) (&& (sle (var result_byte3) (bv 8 0x80)) (! (== (var result_byte3) (bv 8 0x80)))))) (set ov2 (|| (! (ule (var result_byte2) (bv 8 0x7f))) (&& (sle (var result_byte2) (bv 8 0x80)) (! (== (var result_byte2) (bv 8 0x80)))))) (set ov1 (|| (! (ule (var result_byte1) (bv 8 0x7f))) (&& (sle (var result_byte1) (bv 8 0x80)) (! (== (var result_byte1) (bv 8 0x80)))))) (set ov0 (|| (! (ule (var result_byte0) (bv 8 0x7f))) (&& (sle (var result_byte0) (bv 8 0x80)) (! (== (var result_byte0) (bv 8 0x80)))))) (set overflow (|| (|| (var ov1) (var ov0)) (|| (var ov3) (var ov2)))) (set aov3 (^^ (! (is_zero (& (>> (var result_byte3) (bv 8 0x7) false) (bv 8 0x1)))) (! (is_zero (& (>> (var result_byte3) (bv 8 0x6) false) (bv 8 0x1)))))) (set aov2 (^^ (! (is_zero (& (>> (var result_byte2) (bv 8 0x7) false) (bv 8 0x1)))) (! (is_zero (& (>> (var result_byte2) (bv 8 0x6) false) (bv 8 0x1)))))) (set aov1 (^^ (! (is_zero (& (>> (var result_byte1) (bv 8 0x7) false) (bv 8 0x1)))) (! (is_zero (& (>> (var result_byte1) (bv 8 0x6) false) (bv 8 0x1)))))) (set aov0 (^^ (! (is_zero (& (>> (var result_byte0) (bv 8 0x7) false) (bv 8 0x1)))) (! (is_zero (& (>> (var result_byte0) (bv 8 0x6) false) (bv 8 0x1)))))) (set advanced_overflow (|| (|| (var aov1) (var aov0)) (|| (var aov3) (var aov2)))) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (ite (var overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1e) false))) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (ite (var advanced_overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1c) false))) (branch (var overflow) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (branch (var advanced_overflow) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop))
d "add.f d13, d3, d7" 6b0721d3 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d3) ))) (set _fb (fconvert ieee754-bin64 rne (float 0 (var d7) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _arg_b (let tmp (var _fb) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _precise_result (+. rne (var _arg_a) (var _arg_b))) (set _normal_result (let tmp (var _precise_result) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _rounded_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _normal_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (|| (is_nan (var _fa)) (is_nan (var _fb))) (float 0 (bv 32 0x7fc00001) ) (ite (&& (is_inf (var _fa)) (is_inf (var _fb))) (float 0 (bv 32 0x7f800001) ) (var _rounded_result)))) (set d13 (fbits (var _result))) (set set_FI (|| (is_nan (var _fa)) (is_nan (var _fb)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set set_FV (&& (! (|| (is_nan (var _rounded_result)) (is_nan (float 0 (bv 32 0x7f800000) )))) (! (<. (var _rounded_result) (float 0 (bv 32 0x7f800000) ))))) (branch (var set_FV) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set set_FU (&& (! (|| (is_nan (fpos (var _precise_result))) (is_nan (float 1 (bv 64 0x3820000000000000) )))) (<. (fpos (var _precise_result)) (float 1 (bv 64 0x3820000000000000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (fconvert ieee754-bin64 rne (var _result)))) (|| (<. (var _precise_result) (fconvert ieee754-bin64 rne (var _result))) (<. (fconvert ieee754-bin64 rne (var _result)) (var _precise_result))))) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (ite (&& (var set_FX) (! (var set_FI))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1a) false))) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (|| (var set_FI) (|| (var set_FV) (|| (var set_FU) (var set_FX)))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "add.f d8, d13, d9" 6b09218d 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d13) ))) (set _fb (fconvert ieee754-bin64 rne (float 0 (var d9) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _arg_b (let tmp (var _fb) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _precise_result (+. rne (var _arg_a) (var _arg_b))) (set _normal_result (let tmp (var _precise_result) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _rounded_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _normal_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (|| (is_nan (var _fa)) (is_nan (var _fb))) (float 0 (bv 32 0x7fc00001) ) (ite (&& (is_inf (var _fa)) (is_inf (var _fb))) (float 0 (bv 32 0x7f800001) ) (var _rounded_result)))) (set d8 (fbits (var _result))) (set set_FI (|| (is_nan (var _fa)) (is_nan (var _fb)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set set_FV (&& (! (|| (is_nan (var _rounded_result)) (is_nan (float 0 (bv 32 0x7f800000) )))) (! (<. (var _rounded_result) (float 0 (bv 32 0x7f800000) ))))) (branch (var set_FV) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set set_FU (&& (! (|| (is_nan (fpos (var _precise_result))) (is_nan (float 1 (bv 64 0x3820000000000000) )))) (<. (fpos (var _precise_result)) (float 1 (bv 64 0x3820000000000000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (fconvert ieee754-bin64 rne (var _result)))) (|| (<. (var _precise_result) (fconvert ieee754-bin64 rne (var _result))) (<. (fconvert ieee754-bin64 rne (var _result)) (var _precise_result))))) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (ite (&& (var set_FX) (! (var set_FI))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1a) false))) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (|| (var set_FI) (|| (var set_FV) (|| (var set_FU) (var set_FX)))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "add.f d1, d7, d12" 6b0c2117 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d7) ))) (set _fb (fconvert ieee754-bin64 rne (float 0 (var d12) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _arg_b (let tmp (var _fb) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _precise_result (+. rne (var _arg_a) (var _arg_b))) (set _normal_result (let tmp (var _precise_result) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _rounded_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _normal_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (|| (is_nan (var _fa)) (is_nan (var _fb))) (float 0 (bv 32 0x7fc00001) ) (ite (&& (is_inf (var _fa)) (is_inf (var _fb))) (float 0 (bv 32 0x7f800001) ) (var _rounded_result)))) (set d1 (fbits (var _result))) (set set_FI (|| (is_nan (var _fa)) (is_nan (var _fb)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set set_FV (&& (! (|| (is_nan (var _rounded_result)) (is_nan (float 0 (bv 32 0x7f800000) )))) (! (<. (var _rounded_result) (float 0 (bv 32 0x7f800000) ))))) (branch (var set_FV) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set set_FU (&& (! (|| (is_nan (fpos (var _precise_result))) (is_nan (float 1 (bv 64 0x3820000000000000) )))) (<. (fpos (var _precise_result)) (float 1 (bv 64 0x3820000000000000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (fconvert ieee754-bin64 rne (var _result)))) (|| (<. (var _precise_result) (fconvert ieee754-bin64 rne (var _result))) (<. (fconvert ieee754-bin64 rne (var _result)) (var _precise_result))))) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (ite (&& (var set_FX) (! (var set_FI))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1a) false))) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (|| (var set_FI) (|| (var set_FV) (|| (var set_FU) (var set_FX)))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "add.f d13, d3, d7" 6b0721d3 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d3) ))) (set _fb (fconvert ieee754-bin64 rne (float 0 (var d7) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _arg_b (let tmp (var _fb) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _precise_result (+. rne (var _arg_a) (var _arg_b))) (set _normal_result (let tmp (var _precise_result) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _rounded_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _normal_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (|| (is_nan (var _fa)) (is_nan (var _fb))) (float 0 (bv 32 0x7fc00001) ) (ite (&& (is_inf (var _fa)) (is_inf (var _fb))) (float 0 (bv 32 0x7f800001) ) (var _rounded_result)))) (set d13 (fbits (var _result))) (set set_FI (|| (is_nan (var _fa)) (is_nan (var _fb)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set set_FV (&& (! (|| (is_nan (var _rounded_result)) (is_nan (float 0 (bv 32 0x7f800000) )))) (! (<. (var _rounded_result) (float 0 (bv 32 0x7f800000) ))))) (branch (var set_FV) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set set_FU (&& (! (|| (is_nan (fabs (var _precise_result))) (is_nan (float 1 (bv 64 0x3820000000000000) )))) (<. (fabs (var _precise_result)) (float 1 (bv 64 0x3820000000000000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (fconvert ieee754-bin64 rne (var _result)))) (|| (<. (var _precise_result) (fconvert ieee754-bin64 rne (var _result))) (<. (fconvert ieee754-bin64 rne (var _result)) (var _precise_result))))) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (ite (&& (var set_FX) (! (var set_FI))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1a) false))) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (|| (var set_FI) (|| (var set_FV) (|| (var set_FU) (var set_FX)))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "add.f d8, d13, d9" 6b09218d 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d13) ))) (set _fb (fconvert ieee754-bin64 rne (float 0 (var d9) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _arg_b (let tmp (var _fb) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _precise_result (+. rne (var _arg_a) (var _arg_b))) (set _normal_result (let tmp (var _precise_result) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _rounded_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _normal_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (|| (is_nan (var _fa)) (is_nan (var _fb))) (float 0 (bv 32 0x7fc00001) ) (ite (&& (is_inf (var _fa)) (is_inf (var _fb))) (float 0 (bv 32 0x7f800001) ) (var _rounded_result)))) (set d8 (fbits (var _result))) (set set_FI (|| (is_nan (var _fa)) (is_nan (var _fb)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set set_FV (&& (! (|| (is_nan (var _rounded_result)) (is_nan (float 0 (bv 32 0x7f800000) )))) (! (<. (var _rounded_result) (float 0 (bv 32 0x7f800000) ))))) (branch (var set_FV) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set set_FU (&& (! (|| (is_nan (fabs (var _precise_result))) (is_nan (float 1 (bv 64 0x3820000000000000) )))) (<. (fabs (var _precise_result)) (float 1 (bv 64 0x3820000000000000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (fconvert ieee754-bin64 rne (var _result)))) (|| (<. (var _precise_result) (fconvert ieee754-bin64 rne (var _result))) (<. (fconvert ieee754-bin64 rne (var _result)) (var _precise_result))))) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (ite (&& (var set_FX) (! (var set_FI))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1a) false))) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (|| (var set_FI) (|| (var set_FV) (|| (var set_FU) (var set_FX)))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "add.f d1, d7, d12" 6b0c2117 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d7) ))) (set _fb (fconvert ieee754-bin64 rne (float 0 (var d12) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _arg_b (let tmp (var _fb) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _precise_result (+. rne (var _arg_a) (var _arg_b))) (set _normal_result (let tmp (var _precise_result) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _rounded_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _normal_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (|| (is_nan (var _fa)) (is_nan (var _fb))) (float 0 (bv 32 0x7fc00001) ) (ite (&& (is_inf (var _fa)) (is_inf (var _fb))) (float 0 (bv 32 0x7f800001) ) (var _rounded_result)))) (set d1 (fbits (var _result))) (set set_FI (|| (is_nan (var _fa)) (is_nan (var _fb)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set set_FV (&& (! (|| (is_nan (var _rounded_result)) (is_nan (float 0 (bv 32 0x7f800000) )))) (! (<. (var _rounded_result) (float 0 (bv 32 0x7f800000) ))))) (branch (var set_FV) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set set_FU (&& (! (|| (is_nan (fabs (var _precise_result))) (is_nan (float 1 (bv 64 0x3820000000000000) )))) (<. (fabs (var _precise_result)) (float 1 (bv 64 0x3820000000000000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (fconvert ieee754-bin64 rne (var _result)))) (|| (<. (var _precise_result) (fconvert ieee754-bin64 rne (var _result))) (<. (fconvert ieee754-bin64 rne (var _result)) (var _precise_result))))) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (ite (&& (var set_FX) (! (var set_FI))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1a) false))) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (|| (var set_FI) (|| (var set_FV) (|| (var set_FU) (var set_FX)))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "add.h d15, d10, d8" 0b8a00f6 0x000000 (seq (set result_hw1 (+ (cast 16 false (& (>> (var d10) (bv 32 0x10) false) (bv 32 0xffff))) (cast 16 false (& (>> (var d8) (bv 32 0x10) false) (bv 32 0xffff))))) (set result_hw0 (+ (cast 16 false (& (>> (var d10) (bv 32 0x0) false) (bv 32 0xffff))) (cast 16 false (& (>> (var d8) (bv 32 0x0) false) (bv 32 0xffff))))) (set result (| (cast 32 false (<< (var result_hw1) (bv 32 0x10) false)) (cast 32 false (var result_hw0)))) (set d15 (var result)) (set ov1 (|| (! (ule (var result_hw1) (bv 16 0x7fff))) (&& (sle (var result_hw1) (bv 16 0x8000)) (! (== (var result_hw1) (bv 16 0x8000)))))) (set ov0 (|| (! (ule (var result_hw0) (bv 16 0x7fff))) (&& (sle (var result_hw0) (bv 16 0x8000)) (! (== (var result_hw0) (bv 16 0x8000)))))) (set overflow (|| (var ov1) (var ov0))) (set aov1 (^^ (! (is_zero (& (>> (var result_hw1) (bv 16 0xf) false) (bv 16 0x1)))) (! (is_zero (& (>> (var result_hw1) (bv 16 0xe) false) (bv 16 0x1)))))) (set aov0 (^^ (! (is_zero (& (>> (var result_hw0) (bv 16 0xf) false) (bv 16 0x1)))) (! (is_zero (& (>> (var result_hw0) (bv 16 0xe) false) (bv 16 0x1)))))) (set advanced_overflow (|| (var aov1) (var aov0))) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (ite (var overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1e) false))) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (ite (var advanced_overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1c) false))) (branch (var overflow) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (branch (var advanced_overflow) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop))
d "add.h d6, d5, d9" 0b950066 0x000000 (seq (set result_hw1 (+ (cast 16 false (& (>> (var d5) (bv 32 0x10) false) (bv 32 0xffff))) (cast 16 false (& (>> (var d9) (bv 32 0x10) false) (bv 32 0xffff))))) (set result_hw0 (+ (cast 16 false (& (>> (var d5) (bv 32 0x0) false) (bv 32 0xffff))) (cast 16 false (& (>> (var d9) (bv 32 0x0) false) (bv 32 0xffff))))) (set result (| (cast 32 false (<< (var result_hw1) (bv 32 0x10) false)) (cast 32 false (var result_hw0)))) (set d6 (var result)) (set ov1 (|| (! (ule (var result_hw1) (bv 16 0x7fff))) (&& (sle (var result_hw1) (bv 16 0x8000)) (! (== (var result_hw1) (bv 16 0x8000)))))) (set ov0 (|| (! (ule (var result_hw0) (bv 16 0x7fff))) (&& (sle (var result_hw0) (bv 16 0x8000)) (! (== (var result_hw0) (bv 16 0x8000)))))) (set overflow (|| (var ov1) (var ov0))) (set aov1 (^^ (! (is_zero (& (>> (var result_hw1) (bv 16 0xf) false) (bv 16 0x1)))) (! (is_zero (& (>> (var result_hw1) (bv 16 0xe) false) (bv 16 0x1)))))) (set aov0 (^^ (! (is_zero (& (>> (var result_hw0) (bv 16 0xf) false) (bv 16 0x1)))) (! (is_zero (& (>> (var result_hw0) (bv 16 0xe) false) (bv 16 0x1)))))) (set advanced_overflow (|| (var aov1) (var aov0))) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (ite (var overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1e) false))) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (ite (var advanced_overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1c) false))) (branch (var overflow) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (branch (var advanced_overflow) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop))
d "add.h d15, d9, d12" 0bc900f6 0x000000 (seq (set result_hw1 (+ (cast 16 false (& (>> (var d9) (bv 32 0x10) false) (bv 32 0xffff))) (cast 16 false (& (>> (var d12) (bv 32 0x10) false) (bv 32 0xffff))))) (set result_hw0 (+ (cast 16 false (& (>> (var d9) (bv 32 0x0) false) (bv 32 0xffff))) (cast 16 false (& (>> (var d12) (bv 32 0x0) false) (bv 32 0xffff))))) (set result (| (cast 32 false (<< (var result_hw1) (bv 32 0x10) false)) (cast 32 false (var result_hw0)))) (set d15 (var result)) (set ov1 (|| (! (ule (var result_hw1) (bv 16 0x7fff))) (&& (sle (var result_hw1) (bv 16 0x8000)) (! (== (var result_hw1) (bv 16 0x8000)))))) (set ov0 (|| (! (ule (var result_hw0) (bv 16 0x7fff))) (&& (sle (var result_hw0) (bv 16 0x8000)) (! (== (var result_hw0) (bv 16 0x8000)))))) (set overflow (|| (var ov1) (var ov0))) (set aov1 (^^ (! (is_zero (& (>> (var result_hw1) (bv 16 0xf) false) (bv 16 0x1)))) (! (is_zero (& (>> (var result_hw1) (bv 16 0xe) false) (bv 16 0x1)))))) (set aov0 (^^ (! (is_zero (& (>> (var result_hw0) (bv 16 0xf) false) (bv 16 0x1)))) (! (is_zero (& (>> (var result_hw0) (bv 16 0xe) false) (bv 16 0x1)))))) (set advanced_overflow (|| (var aov1) (var aov0))) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (ite (var overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1e) false))) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (ite (var advanced_overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1c) false))) (branch (var overflow) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (branch (var advanced_overflow) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop))
@ -350,9 +350,9 @@ d "disable d4" 0d04c003 0x000000 (seq (set d4 (& (>> (var ICR) (bv 32 0x8) false
d "div e10, d4, d15" 4bf401a2 0x000000 (seq (set dividend (var d4)) (set divisor (var d15)) (set remainder (ite (== (var divisor) (bv 32 0x0)) (bv 32 0x0) (ite (&& (== (var divisor) (bv 32 0xffffffff)) (== (var dividend) (bv 32 0x80000000))) (bv 32 0x0) (mod (var dividend) (var divisor))))) (set quotient (ite (== (var divisor) (bv 32 0x0)) (ite (|| (! (sle (var dividend) (bv 32 0x0))) (== (var dividend) (bv 32 0x0))) (bv 32 0x7fffffff) (bv 32 0x80000000)) (ite (&& (== (var divisor) (bv 32 0xffffffff)) (== (var dividend) (bv 32 0x80000000))) (bv 32 0x7fffffff) (div (- (var dividend) (var remainder)) (var divisor))))) (set temp (append (var remainder) (var quotient))) (set d10 (cast 32 false (var temp))) (set d11 (cast 32 false (& (>> (var temp) (bv 64 0x20) false) (bv 64 0xffffffff)))))
d "div e8, d9, d8" 4b890192 0x000000 (seq (set dividend (var d9)) (set divisor (var d8)) (set remainder (ite (== (var divisor) (bv 32 0x0)) (bv 32 0x0) (ite (&& (== (var divisor) (bv 32 0xffffffff)) (== (var dividend) (bv 32 0x80000000))) (bv 32 0x0) (mod (var dividend) (var divisor))))) (set quotient (ite (== (var divisor) (bv 32 0x0)) (ite (|| (! (sle (var dividend) (bv 32 0x0))) (== (var dividend) (bv 32 0x0))) (bv 32 0x7fffffff) (bv 32 0x80000000)) (ite (&& (== (var divisor) (bv 32 0xffffffff)) (== (var dividend) (bv 32 0x80000000))) (bv 32 0x7fffffff) (div (- (var dividend) (var remainder)) (var divisor))))) (set temp (append (var remainder) (var quotient))) (set d8 (cast 32 false (var temp))) (set d9 (cast 32 false (& (>> (var temp) (bv 64 0x20) false) (bv 64 0xffffffff)))))
d "div e8, d15, d8" 4b8f0192 0x000000 (seq (set dividend (var d15)) (set divisor (var d8)) (set remainder (ite (== (var divisor) (bv 32 0x0)) (bv 32 0x0) (ite (&& (== (var divisor) (bv 32 0xffffffff)) (== (var dividend) (bv 32 0x80000000))) (bv 32 0x0) (mod (var dividend) (var divisor))))) (set quotient (ite (== (var divisor) (bv 32 0x0)) (ite (|| (! (sle (var dividend) (bv 32 0x0))) (== (var dividend) (bv 32 0x0))) (bv 32 0x7fffffff) (bv 32 0x80000000)) (ite (&& (== (var divisor) (bv 32 0xffffffff)) (== (var dividend) (bv 32 0x80000000))) (bv 32 0x7fffffff) (div (- (var dividend) (var remainder)) (var divisor))))) (set temp (append (var remainder) (var quotient))) (set d8 (cast 32 false (var temp))) (set d9 (cast 32 false (& (>> (var temp) (bv 64 0x20) false) (bv 64 0xffffffff)))))
d "div.f d5, d1, d12" 4bc15150 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d1) ))) (set _fb (fconvert ieee754-bin64 rne (float 0 (var d12) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _arg_b (let tmp (var _fb) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _precise_result (/. rne (var _arg_a) (var _arg_b))) (set _normal_result (let tmp (var _precise_result) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _rounded_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _normal_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (|| (is_nan (var _fa)) (is_nan (var _fb))) (float 0 (bv 32 0x7fc00001) ) (ite (|| (&& (is_inf (var _fa)) (is_inf (var _fb))) (&& (is_fzero (var _fa)) (is_fzero (var _fb)))) (float 0 (bv 32 0x7f800001) ) (var _rounded_result)))) (set d5 (fbits (var _result))) (set set_FI (|| (|| (is_nan (var _fa)) (is_nan (var _fb))) (is_nan (var _result)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set set_FV (&& (! (|| (is_nan (var _rounded_result)) (is_nan (float 0 (bv 32 0x7f800000) )))) (! (<. (var _rounded_result) (float 0 (bv 32 0x7f800000) ))))) (branch (var set_FV) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set set_FZ (&& (is_fzero (var _fb)) (! (is_inf (var _fa))))) (branch (var set_FZ) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1c) false))) nop) (set set_FU (&& (! (|| (is_nan (fpos (var _precise_result))) (is_nan (float 1 (bv 64 0x3820000000000000) )))) (<. (fpos (var _precise_result)) (float 1 (bv 64 0x3820000000000000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (fconvert ieee754-bin64 rne (var _result)))) (|| (<. (var _precise_result) (fconvert ieee754-bin64 rne (var _result))) (<. (fconvert ieee754-bin64 rne (var _result)) (var _precise_result))))) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (ite (&& (var set_FX) (! (var set_FI))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1a) false))) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (|| (var set_FI) (|| (var set_FV) (|| (var set_FU) (var set_FX)))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "div.f d8, d8, d8" 4b885180 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d8) ))) (set _fb (fconvert ieee754-bin64 rne (float 0 (var d8) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _arg_b (let tmp (var _fb) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _precise_result (/. rne (var _arg_a) (var _arg_b))) (set _normal_result (let tmp (var _precise_result) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _rounded_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _normal_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (|| (is_nan (var _fa)) (is_nan (var _fb))) (float 0 (bv 32 0x7fc00001) ) (ite (|| (&& (is_inf (var _fa)) (is_inf (var _fb))) (&& (is_fzero (var _fa)) (is_fzero (var _fb)))) (float 0 (bv 32 0x7f800001) ) (var _rounded_result)))) (set d8 (fbits (var _result))) (set set_FI (|| (|| (is_nan (var _fa)) (is_nan (var _fb))) (is_nan (var _result)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set set_FV (&& (! (|| (is_nan (var _rounded_result)) (is_nan (float 0 (bv 32 0x7f800000) )))) (! (<. (var _rounded_result) (float 0 (bv 32 0x7f800000) ))))) (branch (var set_FV) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set set_FZ (&& (is_fzero (var _fb)) (! (is_inf (var _fa))))) (branch (var set_FZ) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1c) false))) nop) (set set_FU (&& (! (|| (is_nan (fpos (var _precise_result))) (is_nan (float 1 (bv 64 0x3820000000000000) )))) (<. (fpos (var _precise_result)) (float 1 (bv 64 0x3820000000000000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (fconvert ieee754-bin64 rne (var _result)))) (|| (<. (var _precise_result) (fconvert ieee754-bin64 rne (var _result))) (<. (fconvert ieee754-bin64 rne (var _result)) (var _precise_result))))) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (ite (&& (var set_FX) (! (var set_FI))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1a) false))) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (|| (var set_FI) (|| (var set_FV) (|| (var set_FU) (var set_FX)))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "div.f d8, d7, d15" 4bf75180 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d7) ))) (set _fb (fconvert ieee754-bin64 rne (float 0 (var d15) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _arg_b (let tmp (var _fb) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _precise_result (/. rne (var _arg_a) (var _arg_b))) (set _normal_result (let tmp (var _precise_result) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _rounded_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _normal_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (|| (is_nan (var _fa)) (is_nan (var _fb))) (float 0 (bv 32 0x7fc00001) ) (ite (|| (&& (is_inf (var _fa)) (is_inf (var _fb))) (&& (is_fzero (var _fa)) (is_fzero (var _fb)))) (float 0 (bv 32 0x7f800001) ) (var _rounded_result)))) (set d8 (fbits (var _result))) (set set_FI (|| (|| (is_nan (var _fa)) (is_nan (var _fb))) (is_nan (var _result)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set set_FV (&& (! (|| (is_nan (var _rounded_result)) (is_nan (float 0 (bv 32 0x7f800000) )))) (! (<. (var _rounded_result) (float 0 (bv 32 0x7f800000) ))))) (branch (var set_FV) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set set_FZ (&& (is_fzero (var _fb)) (! (is_inf (var _fa))))) (branch (var set_FZ) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1c) false))) nop) (set set_FU (&& (! (|| (is_nan (fpos (var _precise_result))) (is_nan (float 1 (bv 64 0x3820000000000000) )))) (<. (fpos (var _precise_result)) (float 1 (bv 64 0x3820000000000000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (fconvert ieee754-bin64 rne (var _result)))) (|| (<. (var _precise_result) (fconvert ieee754-bin64 rne (var _result))) (<. (fconvert ieee754-bin64 rne (var _result)) (var _precise_result))))) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (ite (&& (var set_FX) (! (var set_FI))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1a) false))) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (|| (var set_FI) (|| (var set_FV) (|| (var set_FU) (var set_FX)))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "div.f d5, d1, d12" 4bc15150 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d1) ))) (set _fb (fconvert ieee754-bin64 rne (float 0 (var d12) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _arg_b (let tmp (var _fb) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _precise_result (/. rne (var _arg_a) (var _arg_b))) (set _normal_result (let tmp (var _precise_result) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _rounded_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _normal_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (|| (is_nan (var _fa)) (is_nan (var _fb))) (float 0 (bv 32 0x7fc00001) ) (ite (|| (&& (is_inf (var _fa)) (is_inf (var _fb))) (&& (is_fzero (var _fa)) (is_fzero (var _fb)))) (float 0 (bv 32 0x7f800001) ) (var _rounded_result)))) (set d5 (fbits (var _result))) (set set_FI (|| (|| (is_nan (var _fa)) (is_nan (var _fb))) (is_nan (var _result)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set set_FV (&& (! (|| (is_nan (var _rounded_result)) (is_nan (float 0 (bv 32 0x7f800000) )))) (! (<. (var _rounded_result) (float 0 (bv 32 0x7f800000) ))))) (branch (var set_FV) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set set_FZ (&& (is_fzero (var _fb)) (! (is_inf (var _fa))))) (branch (var set_FZ) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1c) false))) nop) (set set_FU (&& (! (|| (is_nan (fabs (var _precise_result))) (is_nan (float 1 (bv 64 0x3820000000000000) )))) (<. (fabs (var _precise_result)) (float 1 (bv 64 0x3820000000000000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (fconvert ieee754-bin64 rne (var _result)))) (|| (<. (var _precise_result) (fconvert ieee754-bin64 rne (var _result))) (<. (fconvert ieee754-bin64 rne (var _result)) (var _precise_result))))) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (ite (&& (var set_FX) (! (var set_FI))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1a) false))) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (|| (var set_FI) (|| (var set_FV) (|| (var set_FU) (var set_FX)))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "div.f d8, d8, d8" 4b885180 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d8) ))) (set _fb (fconvert ieee754-bin64 rne (float 0 (var d8) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _arg_b (let tmp (var _fb) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _precise_result (/. rne (var _arg_a) (var _arg_b))) (set _normal_result (let tmp (var _precise_result) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _rounded_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _normal_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (|| (is_nan (var _fa)) (is_nan (var _fb))) (float 0 (bv 32 0x7fc00001) ) (ite (|| (&& (is_inf (var _fa)) (is_inf (var _fb))) (&& (is_fzero (var _fa)) (is_fzero (var _fb)))) (float 0 (bv 32 0x7f800001) ) (var _rounded_result)))) (set d8 (fbits (var _result))) (set set_FI (|| (|| (is_nan (var _fa)) (is_nan (var _fb))) (is_nan (var _result)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set set_FV (&& (! (|| (is_nan (var _rounded_result)) (is_nan (float 0 (bv 32 0x7f800000) )))) (! (<. (var _rounded_result) (float 0 (bv 32 0x7f800000) ))))) (branch (var set_FV) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set set_FZ (&& (is_fzero (var _fb)) (! (is_inf (var _fa))))) (branch (var set_FZ) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1c) false))) nop) (set set_FU (&& (! (|| (is_nan (fabs (var _precise_result))) (is_nan (float 1 (bv 64 0x3820000000000000) )))) (<. (fabs (var _precise_result)) (float 1 (bv 64 0x3820000000000000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (fconvert ieee754-bin64 rne (var _result)))) (|| (<. (var _precise_result) (fconvert ieee754-bin64 rne (var _result))) (<. (fconvert ieee754-bin64 rne (var _result)) (var _precise_result))))) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (ite (&& (var set_FX) (! (var set_FI))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1a) false))) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (|| (var set_FI) (|| (var set_FV) (|| (var set_FU) (var set_FX)))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "div.f d8, d7, d15" 4bf75180 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d7) ))) (set _fb (fconvert ieee754-bin64 rne (float 0 (var d15) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _arg_b (let tmp (var _fb) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _precise_result (/. rne (var _arg_a) (var _arg_b))) (set _normal_result (let tmp (var _precise_result) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _rounded_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _normal_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (|| (is_nan (var _fa)) (is_nan (var _fb))) (float 0 (bv 32 0x7fc00001) ) (ite (|| (&& (is_inf (var _fa)) (is_inf (var _fb))) (&& (is_fzero (var _fa)) (is_fzero (var _fb)))) (float 0 (bv 32 0x7f800001) ) (var _rounded_result)))) (set d8 (fbits (var _result))) (set set_FI (|| (|| (is_nan (var _fa)) (is_nan (var _fb))) (is_nan (var _result)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set set_FV (&& (! (|| (is_nan (var _rounded_result)) (is_nan (float 0 (bv 32 0x7f800000) )))) (! (<. (var _rounded_result) (float 0 (bv 32 0x7f800000) ))))) (branch (var set_FV) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set set_FZ (&& (is_fzero (var _fb)) (! (is_inf (var _fa))))) (branch (var set_FZ) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1c) false))) nop) (set set_FU (&& (! (|| (is_nan (fabs (var _precise_result))) (is_nan (float 1 (bv 64 0x3820000000000000) )))) (<. (fabs (var _precise_result)) (float 1 (bv 64 0x3820000000000000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (fconvert ieee754-bin64 rne (var _result)))) (|| (<. (var _precise_result) (fconvert ieee754-bin64 rne (var _result))) (<. (fconvert ieee754-bin64 rne (var _result)) (var _precise_result))))) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (ite (&& (var set_FX) (! (var set_FI))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1a) false))) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (|| (var set_FI) (|| (var set_FV) (|| (var set_FU) (var set_FX)))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "div.u e2, d12, d13" 4bdc1132 0x000000 (seq (set dividend (var d12)) (set divisor (var d13)) (set remainder (ite (== (var divisor) (bv 32 0x0)) (bv 32 0x0) (mod (var dividend) (var divisor)))) (set quotient (ite (== (var divisor) (bv 32 0x0)) (bv 32 0xffffffff) (div (- (var dividend) (var remainder)) (var divisor)))) (set temp (append (var remainder) (var quotient))) (set d2 (cast 32 false (var temp))) (set d3 (cast 32 false (& (>> (var temp) (bv 64 0x20) false) (bv 64 0xffffffff)))))
d "div.u e4, d11, d1" 4b1b1152 0x000000 (seq (set dividend (var d11)) (set divisor (var d1)) (set remainder (ite (== (var divisor) (bv 32 0x0)) (bv 32 0x0) (mod (var dividend) (var divisor)))) (set quotient (ite (== (var divisor) (bv 32 0x0)) (bv 32 0xffffffff) (div (- (var dividend) (var remainder)) (var divisor)))) (set temp (append (var remainder) (var quotient))) (set d4 (cast 32 false (var temp))) (set d5 (cast 32 false (& (>> (var temp) (bv 64 0x20) false) (bv 64 0xffffffff)))))
d "div.u e2, d9, d8" 4b891132 0x000000 (seq (set dividend (var d9)) (set divisor (var d8)) (set remainder (ite (== (var divisor) (bv 32 0x0)) (bv 32 0x0) (mod (var dividend) (var divisor)))) (set quotient (ite (== (var divisor) (bv 32 0x0)) (bv 32 0xffffffff) (div (- (var dividend) (var remainder)) (var divisor)))) (set temp (append (var remainder) (var quotient))) (set d2 (cast 32 false (var temp))) (set d3 (cast 32 false (& (>> (var temp) (bv 64 0x20) false) (bv 64 0xffffffff)))))
@ -1527,9 +1527,9 @@ d "mul e8, d4, #-0xd6" 53a47280 0x000000 (seq (set result (* (cast 64 (msb (var
d "mul e10, d15, d12" 73cf6ab0 0x000000 (seq (set result (* (cast 64 (msb (var d15)) (var d15)) (cast 64 (msb (var d12)) (var d12)))) (set temp (var result)) (set d10 (cast 32 false (var temp))) (set d11 (cast 32 false (& (>> (var temp) (bv 64 0x20) false) (bv 64 0xffffffff)))) (set overflow (|| (! (ule (var result) (bv 64 0x7fffffffffffffff))) (&& (sle (var result) (bv 64 0x8000000000000000)) (! (== (var result) (bv 64 0x8000000000000000)))))) (set advanced_overflow (^^ (! (is_zero (& (>> (var result) (bv 64 0x3f) false) (bv 64 0x1)))) (! (is_zero (& (>> (var result) (bv 64 0x3e) false) (bv 64 0x1)))))) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (ite (var overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1e) false))) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (ite (var advanced_overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1c) false))) (branch (var overflow) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (branch (var advanced_overflow) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop))
d "mul e14, d9, d15" 73f96ae0 0x000000 (seq (set result (* (cast 64 (msb (var d9)) (var d9)) (cast 64 (msb (var d15)) (var d15)))) (set temp (var result)) (set d14 (cast 32 false (var temp))) (set d15 (cast 32 false (& (>> (var temp) (bv 64 0x20) false) (bv 64 0xffffffff)))) (set overflow (|| (! (ule (var result) (bv 64 0x7fffffffffffffff))) (&& (sle (var result) (bv 64 0x8000000000000000)) (! (== (var result) (bv 64 0x8000000000000000)))))) (set advanced_overflow (^^ (! (is_zero (& (>> (var result) (bv 64 0x3f) false) (bv 64 0x1)))) (! (is_zero (& (>> (var result) (bv 64 0x3e) false) (bv 64 0x1)))))) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (ite (var overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1e) false))) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (ite (var advanced_overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1c) false))) (branch (var overflow) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (branch (var advanced_overflow) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop))
d "mul e2, d1, d2" 73216a20 0x000000 (seq (set result (* (cast 64 (msb (var d1)) (var d1)) (cast 64 (msb (var d2)) (var d2)))) (set temp (var result)) (set d2 (cast 32 false (var temp))) (set d3 (cast 32 false (& (>> (var temp) (bv 64 0x20) false) (bv 64 0xffffffff)))) (set overflow (|| (! (ule (var result) (bv 64 0x7fffffffffffffff))) (&& (sle (var result) (bv 64 0x8000000000000000)) (! (== (var result) (bv 64 0x8000000000000000)))))) (set advanced_overflow (^^ (! (is_zero (& (>> (var result) (bv 64 0x3f) false) (bv 64 0x1)))) (! (is_zero (& (>> (var result) (bv 64 0x3e) false) (bv 64 0x1)))))) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (ite (var overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1e) false))) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (ite (var advanced_overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1c) false))) (branch (var overflow) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (branch (var advanced_overflow) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop))
d "mul.f d7, d9, d1" 4b194170 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d9) ))) (set _fb (fconvert ieee754-bin64 rne (float 0 (var d1) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _arg_b (let tmp (var _fb) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _precise_result (*. rne (var _arg_a) (var _arg_b))) (set _normal_result (let tmp (var _precise_result) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _rounded_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _normal_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (|| (is_nan (var _fa)) (is_nan (var _fb))) (float 0 (bv 32 0x7fc00001) ) (ite (|| (&& (is_inf (var _fa)) (is_fzero (var _fb))) (&& (is_fzero (var _fa)) (is_inf (var _fb)))) (float 0 (bv 32 0x7f800001) ) (var _rounded_result)))) (set d7 (fbits (var _result))) (set set_FI (|| (|| (is_nan (var _fa)) (is_nan (var _fb))) (is_nan (var _result)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set set_FV (&& (! (|| (is_nan (var _rounded_result)) (is_nan (float 0 (bv 32 0x7f800000) )))) (! (<. (var _rounded_result) (float 0 (bv 32 0x7f800000) ))))) (branch (var set_FV) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set set_FU (&& (! (|| (is_nan (fpos (var _precise_result))) (is_nan (float 1 (bv 64 0x3820000000000000) )))) (<. (fpos (var _precise_result)) (float 1 (bv 64 0x3820000000000000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (fconvert ieee754-bin64 rne (var _result)))) (|| (<. (var _precise_result) (fconvert ieee754-bin64 rne (var _result))) (<. (fconvert ieee754-bin64 rne (var _result)) (var _precise_result))))) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (ite (&& (var set_FX) (! (var set_FI))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1a) false))) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (|| (var set_FI) (|| (var set_FV) (|| (var set_FU) (var set_FX)))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "mul.f d1, d10, d11" 4bba4110 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d10) ))) (set _fb (fconvert ieee754-bin64 rne (float 0 (var d11) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _arg_b (let tmp (var _fb) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _precise_result (*. rne (var _arg_a) (var _arg_b))) (set _normal_result (let tmp (var _precise_result) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _rounded_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _normal_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (|| (is_nan (var _fa)) (is_nan (var _fb))) (float 0 (bv 32 0x7fc00001) ) (ite (|| (&& (is_inf (var _fa)) (is_fzero (var _fb))) (&& (is_fzero (var _fa)) (is_inf (var _fb)))) (float 0 (bv 32 0x7f800001) ) (var _rounded_result)))) (set d1 (fbits (var _result))) (set set_FI (|| (|| (is_nan (var _fa)) (is_nan (var _fb))) (is_nan (var _result)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set set_FV (&& (! (|| (is_nan (var _rounded_result)) (is_nan (float 0 (bv 32 0x7f800000) )))) (! (<. (var _rounded_result) (float 0 (bv 32 0x7f800000) ))))) (branch (var set_FV) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set set_FU (&& (! (|| (is_nan (fpos (var _precise_result))) (is_nan (float 1 (bv 64 0x3820000000000000) )))) (<. (fpos (var _precise_result)) (float 1 (bv 64 0x3820000000000000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (fconvert ieee754-bin64 rne (var _result)))) (|| (<. (var _precise_result) (fconvert ieee754-bin64 rne (var _result))) (<. (fconvert ieee754-bin64 rne (var _result)) (var _precise_result))))) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (ite (&& (var set_FX) (! (var set_FI))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1a) false))) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (|| (var set_FI) (|| (var set_FV) (|| (var set_FU) (var set_FX)))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "mul.f d1, d13, d2" 4b2d4110 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d13) ))) (set _fb (fconvert ieee754-bin64 rne (float 0 (var d2) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _arg_b (let tmp (var _fb) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _precise_result (*. rne (var _arg_a) (var _arg_b))) (set _normal_result (let tmp (var _precise_result) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _rounded_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _normal_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (|| (is_nan (var _fa)) (is_nan (var _fb))) (float 0 (bv 32 0x7fc00001) ) (ite (|| (&& (is_inf (var _fa)) (is_fzero (var _fb))) (&& (is_fzero (var _fa)) (is_inf (var _fb)))) (float 0 (bv 32 0x7f800001) ) (var _rounded_result)))) (set d1 (fbits (var _result))) (set set_FI (|| (|| (is_nan (var _fa)) (is_nan (var _fb))) (is_nan (var _result)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set set_FV (&& (! (|| (is_nan (var _rounded_result)) (is_nan (float 0 (bv 32 0x7f800000) )))) (! (<. (var _rounded_result) (float 0 (bv 32 0x7f800000) ))))) (branch (var set_FV) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set set_FU (&& (! (|| (is_nan (fpos (var _precise_result))) (is_nan (float 1 (bv 64 0x3820000000000000) )))) (<. (fpos (var _precise_result)) (float 1 (bv 64 0x3820000000000000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (fconvert ieee754-bin64 rne (var _result)))) (|| (<. (var _precise_result) (fconvert ieee754-bin64 rne (var _result))) (<. (fconvert ieee754-bin64 rne (var _result)) (var _precise_result))))) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (ite (&& (var set_FX) (! (var set_FI))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1a) false))) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (|| (var set_FI) (|| (var set_FV) (|| (var set_FU) (var set_FX)))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "mul.f d7, d9, d1" 4b194170 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d9) ))) (set _fb (fconvert ieee754-bin64 rne (float 0 (var d1) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _arg_b (let tmp (var _fb) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _precise_result (*. rne (var _arg_a) (var _arg_b))) (set _normal_result (let tmp (var _precise_result) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _rounded_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _normal_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (|| (is_nan (var _fa)) (is_nan (var _fb))) (float 0 (bv 32 0x7fc00001) ) (ite (|| (&& (is_inf (var _fa)) (is_fzero (var _fb))) (&& (is_fzero (var _fa)) (is_inf (var _fb)))) (float 0 (bv 32 0x7f800001) ) (var _rounded_result)))) (set d7 (fbits (var _result))) (set set_FI (|| (|| (is_nan (var _fa)) (is_nan (var _fb))) (is_nan (var _result)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set set_FV (&& (! (|| (is_nan (var _rounded_result)) (is_nan (float 0 (bv 32 0x7f800000) )))) (! (<. (var _rounded_result) (float 0 (bv 32 0x7f800000) ))))) (branch (var set_FV) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set set_FU (&& (! (|| (is_nan (fabs (var _precise_result))) (is_nan (float 1 (bv 64 0x3820000000000000) )))) (<. (fabs (var _precise_result)) (float 1 (bv 64 0x3820000000000000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (fconvert ieee754-bin64 rne (var _result)))) (|| (<. (var _precise_result) (fconvert ieee754-bin64 rne (var _result))) (<. (fconvert ieee754-bin64 rne (var _result)) (var _precise_result))))) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (ite (&& (var set_FX) (! (var set_FI))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1a) false))) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (|| (var set_FI) (|| (var set_FV) (|| (var set_FU) (var set_FX)))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "mul.f d1, d10, d11" 4bba4110 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d10) ))) (set _fb (fconvert ieee754-bin64 rne (float 0 (var d11) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _arg_b (let tmp (var _fb) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _precise_result (*. rne (var _arg_a) (var _arg_b))) (set _normal_result (let tmp (var _precise_result) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _rounded_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _normal_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (|| (is_nan (var _fa)) (is_nan (var _fb))) (float 0 (bv 32 0x7fc00001) ) (ite (|| (&& (is_inf (var _fa)) (is_fzero (var _fb))) (&& (is_fzero (var _fa)) (is_inf (var _fb)))) (float 0 (bv 32 0x7f800001) ) (var _rounded_result)))) (set d1 (fbits (var _result))) (set set_FI (|| (|| (is_nan (var _fa)) (is_nan (var _fb))) (is_nan (var _result)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set set_FV (&& (! (|| (is_nan (var _rounded_result)) (is_nan (float 0 (bv 32 0x7f800000) )))) (! (<. (var _rounded_result) (float 0 (bv 32 0x7f800000) ))))) (branch (var set_FV) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set set_FU (&& (! (|| (is_nan (fabs (var _precise_result))) (is_nan (float 1 (bv 64 0x3820000000000000) )))) (<. (fabs (var _precise_result)) (float 1 (bv 64 0x3820000000000000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (fconvert ieee754-bin64 rne (var _result)))) (|| (<. (var _precise_result) (fconvert ieee754-bin64 rne (var _result))) (<. (fconvert ieee754-bin64 rne (var _result)) (var _precise_result))))) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (ite (&& (var set_FX) (! (var set_FI))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1a) false))) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (|| (var set_FI) (|| (var set_FV) (|| (var set_FU) (var set_FX)))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "mul.f d1, d13, d2" 4b2d4110 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d13) ))) (set _fb (fconvert ieee754-bin64 rne (float 0 (var d2) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _arg_b (let tmp (var _fb) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _precise_result (*. rne (var _arg_a) (var _arg_b))) (set _normal_result (let tmp (var _precise_result) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _rounded_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _normal_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (|| (is_nan (var _fa)) (is_nan (var _fb))) (float 0 (bv 32 0x7fc00001) ) (ite (|| (&& (is_inf (var _fa)) (is_fzero (var _fb))) (&& (is_fzero (var _fa)) (is_inf (var _fb)))) (float 0 (bv 32 0x7f800001) ) (var _rounded_result)))) (set d1 (fbits (var _result))) (set set_FI (|| (|| (is_nan (var _fa)) (is_nan (var _fb))) (is_nan (var _result)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set set_FV (&& (! (|| (is_nan (var _rounded_result)) (is_nan (float 0 (bv 32 0x7f800000) )))) (! (<. (var _rounded_result) (float 0 (bv 32 0x7f800000) ))))) (branch (var set_FV) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set set_FU (&& (! (|| (is_nan (fabs (var _precise_result))) (is_nan (float 1 (bv 64 0x3820000000000000) )))) (<. (fabs (var _precise_result)) (float 1 (bv 64 0x3820000000000000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (fconvert ieee754-bin64 rne (var _result)))) (|| (<. (var _precise_result) (fconvert ieee754-bin64 rne (var _result))) (<. (fconvert ieee754-bin64 rne (var _result)) (var _precise_result))))) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (ite (&& (var set_FX) (! (var set_FI))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1a) false))) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (|| (var set_FI) (|| (var set_FV) (|| (var set_FU) (var set_FX)))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "mul.h e6, d11, d9ul, #1" b39b6160 0x000000 (seq (set mul_a (& (>> (var d11) (bv 32 0x10) false) (bv 32 0xffff))) (set mul_b (& (>> (var d9) (bv 32 0x10) false) (bv 32 0xffff))) (set sc1 (&& (== (var mul_a) (bv 32 0x8000)) (&& (== (var mul_b) (bv 32 0x8000)) (== (bv 32 0x1) (bv 32 0x1))))) (set result_word1 (ite (var sc1) (bv 32 0x7fffffff) (<< (* (var mul_a) (var mul_b)) (bv 32 0x1) false))) (set mul_a (& (>> (var d11) (bv 32 0x0) false) (bv 32 0xffff))) (set mul_b (& (>> (var d9) (bv 32 0x0) false) (bv 32 0xffff))) (set sc0 (&& (== (var mul_a) (bv 32 0x8000)) (&& (== (var mul_b) (bv 32 0x8000)) (== (bv 32 0x1) (bv 32 0x1))))) (set result_word0 (ite (var sc0) (bv 32 0x7fffffff) (<< (* (var mul_a) (var mul_b)) (bv 32 0x1) false))) (set temp (append (var result_word1) (var result_word0))) (set d6 (cast 32 false (var temp))) (set d7 (cast 32 false (& (>> (var temp) (bv 64 0x20) false) (bv 64 0xffffffff)))) (set ov1 (|| (! (ule (var result_word1) (bv 32 0x7fffffff))) (&& (sle (var result_word1) (bv 32 0x80000000)) (! (== (var result_word1) (bv 32 0x80000000)))))) (set ov0 (|| (! (ule (var result_word0) (bv 32 0x7fffffff))) (&& (sle (var result_word0) (bv 32 0x80000000)) (! (== (var result_word0) (bv 32 0x80000000)))))) (set overflow (|| (var ov1) (var ov0))) (set aov1 (^^ (! (is_zero (& (>> (var result_word1) (bv 32 0x1f) false) (bv 32 0x1)))) (! (is_zero (& (>> (var result_word1) (bv 32 0x1e) false) (bv 32 0x1)))))) (set aov0 (^^ (! (is_zero (& (>> (var result_word0) (bv 32 0x1f) false) (bv 32 0x1)))) (! (is_zero (& (>> (var result_word0) (bv 32 0x1e) false) (bv 32 0x1)))))) (set advanced_overflow (|| (var aov1) (var aov0))) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (ite (var overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1e) false))) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (ite (var advanced_overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1c) false))) (branch (var overflow) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (branch (var advanced_overflow) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop))
d "mul.h e10, d0, d7ul, #0" b37060a0 0x000000 (seq (set mul_a (& (>> (var d0) (bv 32 0x10) false) (bv 32 0xffff))) (set mul_b (& (>> (var d7) (bv 32 0x10) false) (bv 32 0xffff))) (set sc1 (&& (== (var mul_a) (bv 32 0x8000)) (&& (== (var mul_b) (bv 32 0x8000)) (== (bv 32 0x0) (bv 32 0x1))))) (set result_word1 (ite (var sc1) (bv 32 0x7fffffff) (<< (* (var mul_a) (var mul_b)) (bv 32 0x0) false))) (set mul_a (& (>> (var d0) (bv 32 0x0) false) (bv 32 0xffff))) (set mul_b (& (>> (var d7) (bv 32 0x0) false) (bv 32 0xffff))) (set sc0 (&& (== (var mul_a) (bv 32 0x8000)) (&& (== (var mul_b) (bv 32 0x8000)) (== (bv 32 0x0) (bv 32 0x1))))) (set result_word0 (ite (var sc0) (bv 32 0x7fffffff) (<< (* (var mul_a) (var mul_b)) (bv 32 0x0) false))) (set temp (append (var result_word1) (var result_word0))) (set d10 (cast 32 false (var temp))) (set d11 (cast 32 false (& (>> (var temp) (bv 64 0x20) false) (bv 64 0xffffffff)))) (set ov1 (|| (! (ule (var result_word1) (bv 32 0x7fffffff))) (&& (sle (var result_word1) (bv 32 0x80000000)) (! (== (var result_word1) (bv 32 0x80000000)))))) (set ov0 (|| (! (ule (var result_word0) (bv 32 0x7fffffff))) (&& (sle (var result_word0) (bv 32 0x80000000)) (! (== (var result_word0) (bv 32 0x80000000)))))) (set overflow (|| (var ov1) (var ov0))) (set aov1 (^^ (! (is_zero (& (>> (var result_word1) (bv 32 0x1f) false) (bv 32 0x1)))) (! (is_zero (& (>> (var result_word1) (bv 32 0x1e) false) (bv 32 0x1)))))) (set aov0 (^^ (! (is_zero (& (>> (var result_word0) (bv 32 0x1f) false) (bv 32 0x1)))) (! (is_zero (& (>> (var result_word0) (bv 32 0x1e) false) (bv 32 0x1)))))) (set advanced_overflow (|| (var aov1) (var aov0))) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (ite (var overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1e) false))) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (ite (var advanced_overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1c) false))) (branch (var overflow) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (branch (var advanced_overflow) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop))
d "mul.h e2, d14, d13ul, #2" b3de6230 0x000000 (seq (set mul_a (& (>> (var d14) (bv 32 0x10) false) (bv 32 0xffff))) (set mul_b (& (>> (var d13) (bv 32 0x10) false) (bv 32 0xffff))) (set sc1 (&& (== (var mul_a) (bv 32 0x8000)) (&& (== (var mul_b) (bv 32 0x8000)) (== (bv 32 0x2) (bv 32 0x1))))) (set result_word1 (ite (var sc1) (bv 32 0x7fffffff) (<< (* (var mul_a) (var mul_b)) (bv 32 0x2) false))) (set mul_a (& (>> (var d14) (bv 32 0x0) false) (bv 32 0xffff))) (set mul_b (& (>> (var d13) (bv 32 0x0) false) (bv 32 0xffff))) (set sc0 (&& (== (var mul_a) (bv 32 0x8000)) (&& (== (var mul_b) (bv 32 0x8000)) (== (bv 32 0x2) (bv 32 0x1))))) (set result_word0 (ite (var sc0) (bv 32 0x7fffffff) (<< (* (var mul_a) (var mul_b)) (bv 32 0x2) false))) (set temp (append (var result_word1) (var result_word0))) (set d2 (cast 32 false (var temp))) (set d3 (cast 32 false (& (>> (var temp) (bv 64 0x20) false) (bv 64 0xffffffff)))) (set ov1 (|| (! (ule (var result_word1) (bv 32 0x7fffffff))) (&& (sle (var result_word1) (bv 32 0x80000000)) (! (== (var result_word1) (bv 32 0x80000000)))))) (set ov0 (|| (! (ule (var result_word0) (bv 32 0x7fffffff))) (&& (sle (var result_word0) (bv 32 0x80000000)) (! (== (var result_word0) (bv 32 0x80000000)))))) (set overflow (|| (var ov1) (var ov0))) (set aov1 (^^ (! (is_zero (& (>> (var result_word1) (bv 32 0x1f) false) (bv 32 0x1)))) (! (is_zero (& (>> (var result_word1) (bv 32 0x1e) false) (bv 32 0x1)))))) (set aov0 (^^ (! (is_zero (& (>> (var result_word0) (bv 32 0x1f) false) (bv 32 0x1)))) (! (is_zero (& (>> (var result_word0) (bv 32 0x1e) false) (bv 32 0x1)))))) (set advanced_overflow (|| (var aov1) (var aov0))) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (ite (var overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1e) false))) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (ite (var advanced_overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1c) false))) (branch (var overflow) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (branch (var advanced_overflow) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop))
@ -1736,9 +1736,9 @@ d "pack d3, e0, d7" 6b070031 0x000000 (seq (set int_exp (var d1)) (set int_mant
d "parity d13, d10" 4b0a20d0 0x000000 (set d13 (let _31_24 (ite (^^ (^^ (! (is_zero (& (>> (var d10) (bv 32 0x18) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d10) (bv 32 0x19) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d10) (bv 32 0x1a) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d10) (bv 32 0x1b) false) (bv 32 0x1))))))) (^^ (! (is_zero (& (>> (var d10) (bv 32 0x1c) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d10) (bv 32 0x1d) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d10) (bv 32 0x1e) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d10) (bv 32 0x1f) false) (bv 32 0x1)))))))) (bv 8 0x1) (bv 8 0x0)) (let _23_16 (ite (^^ (^^ (! (is_zero (& (>> (var d10) (bv 32 0x10) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d10) (bv 32 0x11) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d10) (bv 32 0x12) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d10) (bv 32 0x13) false) (bv 32 0x1))))))) (^^ (! (is_zero (& (>> (var d10) (bv 32 0x14) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d10) (bv 32 0x15) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d10) (bv 32 0x16) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d10) (bv 32 0x17) false) (bv 32 0x1)))))))) (bv 8 0x1) (bv 8 0x0)) (let _15_8 (ite (^^ (^^ (! (is_zero (& (>> (var d10) (bv 32 0x8) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d10) (bv 32 0x9) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d10) (bv 32 0xa) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d10) (bv 32 0xb) false) (bv 32 0x1))))))) (^^ (! (is_zero (& (>> (var d10) (bv 32 0xc) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d10) (bv 32 0xd) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d10) (bv 32 0xe) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d10) (bv 32 0xf) false) (bv 32 0x1)))))))) (bv 8 0x1) (bv 8 0x0)) (let _7_0 (ite (^^ (^^ (! (is_zero (& (>> (var d10) (bv 32 0x0) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d10) (bv 32 0x1) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d10) (bv 32 0x2) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d10) (bv 32 0x3) false) (bv 32 0x1))))))) (^^ (! (is_zero (& (>> (var d10) (bv 32 0x4) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d10) (bv 32 0x5) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d10) (bv 32 0x6) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d10) (bv 32 0x7) false) (bv 32 0x1)))))))) (bv 8 0x1) (bv 8 0x0)) (append (append (var _31_24) (var _23_16)) (append (var _15_8) (var _7_0))))))))
d "parity d0, d12" 4b0c2000 0x000000 (set d0 (let _31_24 (ite (^^ (^^ (! (is_zero (& (>> (var d12) (bv 32 0x18) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d12) (bv 32 0x19) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d12) (bv 32 0x1a) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d12) (bv 32 0x1b) false) (bv 32 0x1))))))) (^^ (! (is_zero (& (>> (var d12) (bv 32 0x1c) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d12) (bv 32 0x1d) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d12) (bv 32 0x1e) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d12) (bv 32 0x1f) false) (bv 32 0x1)))))))) (bv 8 0x1) (bv 8 0x0)) (let _23_16 (ite (^^ (^^ (! (is_zero (& (>> (var d12) (bv 32 0x10) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d12) (bv 32 0x11) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d12) (bv 32 0x12) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d12) (bv 32 0x13) false) (bv 32 0x1))))))) (^^ (! (is_zero (& (>> (var d12) (bv 32 0x14) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d12) (bv 32 0x15) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d12) (bv 32 0x16) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d12) (bv 32 0x17) false) (bv 32 0x1)))))))) (bv 8 0x1) (bv 8 0x0)) (let _15_8 (ite (^^ (^^ (! (is_zero (& (>> (var d12) (bv 32 0x8) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d12) (bv 32 0x9) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d12) (bv 32 0xa) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d12) (bv 32 0xb) false) (bv 32 0x1))))))) (^^ (! (is_zero (& (>> (var d12) (bv 32 0xc) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d12) (bv 32 0xd) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d12) (bv 32 0xe) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d12) (bv 32 0xf) false) (bv 32 0x1)))))))) (bv 8 0x1) (bv 8 0x0)) (let _7_0 (ite (^^ (^^ (! (is_zero (& (>> (var d12) (bv 32 0x0) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d12) (bv 32 0x1) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d12) (bv 32 0x2) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d12) (bv 32 0x3) false) (bv 32 0x1))))))) (^^ (! (is_zero (& (>> (var d12) (bv 32 0x4) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d12) (bv 32 0x5) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d12) (bv 32 0x6) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d12) (bv 32 0x7) false) (bv 32 0x1)))))))) (bv 8 0x1) (bv 8 0x0)) (append (append (var _31_24) (var _23_16)) (append (var _15_8) (var _7_0))))))))
d "parity d14, d4" 4b0420e0 0x000000 (set d14 (let _31_24 (ite (^^ (^^ (! (is_zero (& (>> (var d4) (bv 32 0x18) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d4) (bv 32 0x19) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d4) (bv 32 0x1a) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d4) (bv 32 0x1b) false) (bv 32 0x1))))))) (^^ (! (is_zero (& (>> (var d4) (bv 32 0x1c) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d4) (bv 32 0x1d) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d4) (bv 32 0x1e) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d4) (bv 32 0x1f) false) (bv 32 0x1)))))))) (bv 8 0x1) (bv 8 0x0)) (let _23_16 (ite (^^ (^^ (! (is_zero (& (>> (var d4) (bv 32 0x10) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d4) (bv 32 0x11) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d4) (bv 32 0x12) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d4) (bv 32 0x13) false) (bv 32 0x1))))))) (^^ (! (is_zero (& (>> (var d4) (bv 32 0x14) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d4) (bv 32 0x15) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d4) (bv 32 0x16) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d4) (bv 32 0x17) false) (bv 32 0x1)))))))) (bv 8 0x1) (bv 8 0x0)) (let _15_8 (ite (^^ (^^ (! (is_zero (& (>> (var d4) (bv 32 0x8) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d4) (bv 32 0x9) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d4) (bv 32 0xa) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d4) (bv 32 0xb) false) (bv 32 0x1))))))) (^^ (! (is_zero (& (>> (var d4) (bv 32 0xc) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d4) (bv 32 0xd) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d4) (bv 32 0xe) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d4) (bv 32 0xf) false) (bv 32 0x1)))))))) (bv 8 0x1) (bv 8 0x0)) (let _7_0 (ite (^^ (^^ (! (is_zero (& (>> (var d4) (bv 32 0x0) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d4) (bv 32 0x1) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d4) (bv 32 0x2) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d4) (bv 32 0x3) false) (bv 32 0x1))))))) (^^ (! (is_zero (& (>> (var d4) (bv 32 0x4) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d4) (bv 32 0x5) false) (bv 32 0x1)))) (^^ (! (is_zero (& (>> (var d4) (bv 32 0x6) false) (bv 32 0x1)))) (! (is_zero (& (>> (var d4) (bv 32 0x7) false) (bv 32 0x1)))))))) (bv 8 0x1) (bv 8 0x0)) (append (append (var _31_24) (var _23_16)) (append (var _15_8) (var _7_0))))))))
d "q31tof d12, d4, d10" 4ba451c1 0x000000 (seq (set _a (var d4)) (set _qa (float 0 (bv 32 0x0) )) (set _x (var _a)) (set _i (bv 32 0x0)) (set _qa (ite (msb (var _x)) (float 0 (bv 32 0xbf800000) ) (float 0 (bv 32 0x0) ))) (repeat (&& (ule (var _i) (bv 32 0x1f)) (! (== (var _i) (bv 32 0x1f)))) (seq (set _i (+ (var _i) (bv 32 0x1))) (set _m (<< (bv 32 0x1) (- (bv 32 0x1e) (var _i)) false)) (set _b (/. rne (float 0 (bv 32 0x3f800000) ) (float 0 (<< (bv 32 0x2) (var _i) false) ))) (branch (! (is_zero (& (var _x) (var _m)))) (set _qa (+. rne (var _qa) (var _b))) nop))) (set _precise_result (*. rne (var _qa) (pow rne (float 0 (bv 32 0x40000000) ) (float 0 (& (var d10) (bv 32 0x1ff)) )))) (set _result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _precise_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set d12 (fbits (var _result))) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (var _result))) (|| (<. (var _precise_result) (var _result)) (<. (var _result) (var _precise_result))))) (branch (var set_FX) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1a) false))) nop) (set set_FU (&& (! (|| (is_nan (fpos (var _precise_result))) (is_nan (float 0 (bv 32 0x400000) )))) (<. (fpos (var _precise_result)) (float 0 (bv 32 0x400000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (var set_FX) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "q31tof d14, d13, d13" 4bdd51e1 0x000000 (seq (set _a (var d13)) (set _qa (float 0 (bv 32 0x0) )) (set _x (var _a)) (set _i (bv 32 0x0)) (set _qa (ite (msb (var _x)) (float 0 (bv 32 0xbf800000) ) (float 0 (bv 32 0x0) ))) (repeat (&& (ule (var _i) (bv 32 0x1f)) (! (== (var _i) (bv 32 0x1f)))) (seq (set _i (+ (var _i) (bv 32 0x1))) (set _m (<< (bv 32 0x1) (- (bv 32 0x1e) (var _i)) false)) (set _b (/. rne (float 0 (bv 32 0x3f800000) ) (float 0 (<< (bv 32 0x2) (var _i) false) ))) (branch (! (is_zero (& (var _x) (var _m)))) (set _qa (+. rne (var _qa) (var _b))) nop))) (set _precise_result (*. rne (var _qa) (pow rne (float 0 (bv 32 0x40000000) ) (float 0 (& (var d13) (bv 32 0x1ff)) )))) (set _result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _precise_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set d14 (fbits (var _result))) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (var _result))) (|| (<. (var _precise_result) (var _result)) (<. (var _result) (var _precise_result))))) (branch (var set_FX) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1a) false))) nop) (set set_FU (&& (! (|| (is_nan (fpos (var _precise_result))) (is_nan (float 0 (bv 32 0x400000) )))) (<. (fpos (var _precise_result)) (float 0 (bv 32 0x400000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (var set_FX) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "q31tof d6, d11, d12" 4bcb5161 0x000000 (seq (set _a (var d11)) (set _qa (float 0 (bv 32 0x0) )) (set _x (var _a)) (set _i (bv 32 0x0)) (set _qa (ite (msb (var _x)) (float 0 (bv 32 0xbf800000) ) (float 0 (bv 32 0x0) ))) (repeat (&& (ule (var _i) (bv 32 0x1f)) (! (== (var _i) (bv 32 0x1f)))) (seq (set _i (+ (var _i) (bv 32 0x1))) (set _m (<< (bv 32 0x1) (- (bv 32 0x1e) (var _i)) false)) (set _b (/. rne (float 0 (bv 32 0x3f800000) ) (float 0 (<< (bv 32 0x2) (var _i) false) ))) (branch (! (is_zero (& (var _x) (var _m)))) (set _qa (+. rne (var _qa) (var _b))) nop))) (set _precise_result (*. rne (var _qa) (pow rne (float 0 (bv 32 0x40000000) ) (float 0 (& (var d12) (bv 32 0x1ff)) )))) (set _result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _precise_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set d6 (fbits (var _result))) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (var _result))) (|| (<. (var _precise_result) (var _result)) (<. (var _result) (var _precise_result))))) (branch (var set_FX) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1a) false))) nop) (set set_FU (&& (! (|| (is_nan (fpos (var _precise_result))) (is_nan (float 0 (bv 32 0x400000) )))) (<. (fpos (var _precise_result)) (float 0 (bv 32 0x400000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (var set_FX) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "q31tof d12, d4, d10" 4ba451c1 0x000000 (seq (set _a (var d4)) (set _qa (float 0 (bv 32 0x0) )) (set _x (var _a)) (set _i (bv 32 0x0)) (set _qa (ite (msb (var _x)) (float 0 (bv 32 0xbf800000) ) (float 0 (bv 32 0x0) ))) (repeat (&& (ule (var _i) (bv 32 0x1f)) (! (== (var _i) (bv 32 0x1f)))) (seq (set _i (+ (var _i) (bv 32 0x1))) (set _m (<< (bv 32 0x1) (- (bv 32 0x1e) (var _i)) false)) (set _b (/. rne (float 0 (bv 32 0x3f800000) ) (float 0 (<< (bv 32 0x2) (var _i) false) ))) (branch (! (is_zero (& (var _x) (var _m)))) (set _qa (+. rne (var _qa) (var _b))) nop))) (set _precise_result (*. rne (var _qa) (pow rne (float 0 (bv 32 0x40000000) ) (float 0 (& (var d10) (bv 32 0x1ff)) )))) (set _result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _precise_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set d12 (fbits (var _result))) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (var _result))) (|| (<. (var _precise_result) (var _result)) (<. (var _result) (var _precise_result))))) (branch (var set_FX) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1a) false))) nop) (set set_FU (&& (! (|| (is_nan (fabs (var _precise_result))) (is_nan (float 0 (bv 32 0x400000) )))) (<. (fabs (var _precise_result)) (float 0 (bv 32 0x400000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (var set_FX) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "q31tof d14, d13, d13" 4bdd51e1 0x000000 (seq (set _a (var d13)) (set _qa (float 0 (bv 32 0x0) )) (set _x (var _a)) (set _i (bv 32 0x0)) (set _qa (ite (msb (var _x)) (float 0 (bv 32 0xbf800000) ) (float 0 (bv 32 0x0) ))) (repeat (&& (ule (var _i) (bv 32 0x1f)) (! (== (var _i) (bv 32 0x1f)))) (seq (set _i (+ (var _i) (bv 32 0x1))) (set _m (<< (bv 32 0x1) (- (bv 32 0x1e) (var _i)) false)) (set _b (/. rne (float 0 (bv 32 0x3f800000) ) (float 0 (<< (bv 32 0x2) (var _i) false) ))) (branch (! (is_zero (& (var _x) (var _m)))) (set _qa (+. rne (var _qa) (var _b))) nop))) (set _precise_result (*. rne (var _qa) (pow rne (float 0 (bv 32 0x40000000) ) (float 0 (& (var d13) (bv 32 0x1ff)) )))) (set _result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _precise_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set d14 (fbits (var _result))) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (var _result))) (|| (<. (var _precise_result) (var _result)) (<. (var _result) (var _precise_result))))) (branch (var set_FX) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1a) false))) nop) (set set_FU (&& (! (|| (is_nan (fabs (var _precise_result))) (is_nan (float 0 (bv 32 0x400000) )))) (<. (fabs (var _precise_result)) (float 0 (bv 32 0x400000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (var set_FX) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "q31tof d6, d11, d12" 4bcb5161 0x000000 (seq (set _a (var d11)) (set _qa (float 0 (bv 32 0x0) )) (set _x (var _a)) (set _i (bv 32 0x0)) (set _qa (ite (msb (var _x)) (float 0 (bv 32 0xbf800000) ) (float 0 (bv 32 0x0) ))) (repeat (&& (ule (var _i) (bv 32 0x1f)) (! (== (var _i) (bv 32 0x1f)))) (seq (set _i (+ (var _i) (bv 32 0x1))) (set _m (<< (bv 32 0x1) (- (bv 32 0x1e) (var _i)) false)) (set _b (/. rne (float 0 (bv 32 0x3f800000) ) (float 0 (<< (bv 32 0x2) (var _i) false) ))) (branch (! (is_zero (& (var _x) (var _m)))) (set _qa (+. rne (var _qa) (var _b))) nop))) (set _precise_result (*. rne (var _qa) (pow rne (float 0 (bv 32 0x40000000) ) (float 0 (& (var d12) (bv 32 0x1ff)) )))) (set _result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _precise_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set d6 (fbits (var _result))) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (var _result))) (|| (<. (var _precise_result) (var _result)) (<. (var _result) (var _precise_result))))) (branch (var set_FX) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1a) false))) nop) (set set_FU (&& (! (|| (is_nan (fabs (var _precise_result))) (is_nan (float 0 (bv 32 0x400000) )))) (<. (fabs (var _precise_result)) (float 0 (bv 32 0x400000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (var set_FX) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "qseed.f d3, d9" 4b099131 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d9) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _normal_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (frsqrt rne (var _arg_a)) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (is_fzero (var _arg_a)) (float 0 (bv 32 0x0) ) (ite (&& (! (|| (is_nan (var _fa)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var _fa) (float 1 (bv 64 0x0) ))) (float 0 (bv 32 0x7f800001) ) (var _normal_result)))) (set d3 (fbits (var _result))) (set set_FI (|| (is_nan (var _fa)) (is_nan (var _result)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (var set_FI) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "qseed.f d0, d11" 4b0b9101 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d11) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _normal_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (frsqrt rne (var _arg_a)) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (is_fzero (var _arg_a)) (float 0 (bv 32 0x0) ) (ite (&& (! (|| (is_nan (var _fa)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var _fa) (float 1 (bv 64 0x0) ))) (float 0 (bv 32 0x7f800001) ) (var _normal_result)))) (set d0 (fbits (var _result))) (set set_FI (|| (is_nan (var _fa)) (is_nan (var _result)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (var set_FI) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "qseed.f d5, d1" 4b019151 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d1) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _normal_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (frsqrt rne (var _arg_a)) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (is_fzero (var _arg_a)) (float 0 (bv 32 0x0) ) (ite (&& (! (|| (is_nan (var _fa)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var _fa) (float 1 (bv 64 0x0) ))) (float 0 (bv 32 0x7f800001) ) (var _normal_result)))) (set d5 (fbits (var _result))) (set set_FI (|| (is_nan (var _fa)) (is_nan (var _result)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (var set_FI) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
@ -2059,9 +2059,9 @@ d "sub.a sp, #0x75" 2075 0x000000 (set a10 (- (var a10) (bv 32 0x75)))
d "sub.b d2, d11, d14" 0beb8024 0x000000 (seq (set result_byte3 (- (cast 8 false (& (>> (var d11) (bv 32 0x18) false) (bv 32 0xff))) (cast 8 false (& (>> (var d14) (bv 32 0x18) false) (bv 32 0xff))))) (set result_byte2 (- (cast 8 false (& (>> (var d11) (bv 32 0x10) false) (bv 32 0xff))) (cast 8 false (& (>> (var d14) (bv 32 0x10) false) (bv 32 0xff))))) (set result_byte1 (- (cast 8 false (& (>> (var d11) (bv 32 0x8) false) (bv 32 0xff))) (cast 8 false (& (>> (var d14) (bv 32 0x8) false) (bv 32 0xff))))) (set result_byte0 (- (cast 8 false (& (>> (var d11) (bv 32 0x0) false) (bv 32 0xff))) (cast 8 false (& (>> (var d14) (bv 32 0x0) false) (bv 32 0xff))))) (set result (| (cast 32 false (<< (var result_byte3) (bv 32 0x18) false)) (| (cast 32 false (<< (var result_byte2) (bv 32 0x10) false)) (| (cast 32 false (<< (var result_byte1) (bv 32 0x8) false)) (cast 32 false (var result_byte0)))))) (set d2 (var result)) (set ov3 (|| (! (ule (var result_byte3) (bv 8 0x7f))) (&& (sle (var result_byte3) (bv 8 0x80)) (! (== (var result_byte3) (bv 8 0x80)))))) (set ov2 (|| (! (ule (var result_byte2) (bv 8 0x7f))) (&& (sle (var result_byte2) (bv 8 0x80)) (! (== (var result_byte2) (bv 8 0x80)))))) (set ov1 (|| (! (ule (var result_byte1) (bv 8 0x7f))) (&& (sle (var result_byte1) (bv 8 0x80)) (! (== (var result_byte1) (bv 8 0x80)))))) (set ov0 (|| (! (ule (var result_byte0) (bv 8 0x7f))) (&& (sle (var result_byte0) (bv 8 0x80)) (! (== (var result_byte0) (bv 8 0x80)))))) (set overflow (|| (|| (var ov1) (var ov0)) (|| (var ov3) (var ov2)))) (set aov3 (^^ (! (is_zero (& (>> (var result_byte3) (bv 8 0x7) false) (bv 8 0x1)))) (! (is_zero (& (>> (var result_byte3) (bv 8 0x6) false) (bv 8 0x1)))))) (set aov2 (^^ (! (is_zero (& (>> (var result_byte2) (bv 8 0x7) false) (bv 8 0x1)))) (! (is_zero (& (>> (var result_byte2) (bv 8 0x6) false) (bv 8 0x1)))))) (set aov1 (^^ (! (is_zero (& (>> (var result_byte1) (bv 8 0x7) false) (bv 8 0x1)))) (! (is_zero (& (>> (var result_byte1) (bv 8 0x6) false) (bv 8 0x1)))))) (set aov0 (^^ (! (is_zero (& (>> (var result_byte0) (bv 8 0x7) false) (bv 8 0x1)))) (! (is_zero (& (>> (var result_byte0) (bv 8 0x6) false) (bv 8 0x1)))))) (set advanced_overflow (|| (|| (var aov1) (var aov0)) (|| (var aov3) (var aov2)))) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (ite (var overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1e) false))) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (ite (var advanced_overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1c) false))) (branch (var overflow) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (branch (var advanced_overflow) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop))
d "sub.b d0, d1, d9" 0b918004 0x000000 (seq (set result_byte3 (- (cast 8 false (& (>> (var d1) (bv 32 0x18) false) (bv 32 0xff))) (cast 8 false (& (>> (var d9) (bv 32 0x18) false) (bv 32 0xff))))) (set result_byte2 (- (cast 8 false (& (>> (var d1) (bv 32 0x10) false) (bv 32 0xff))) (cast 8 false (& (>> (var d9) (bv 32 0x10) false) (bv 32 0xff))))) (set result_byte1 (- (cast 8 false (& (>> (var d1) (bv 32 0x8) false) (bv 32 0xff))) (cast 8 false (& (>> (var d9) (bv 32 0x8) false) (bv 32 0xff))))) (set result_byte0 (- (cast 8 false (& (>> (var d1) (bv 32 0x0) false) (bv 32 0xff))) (cast 8 false (& (>> (var d9) (bv 32 0x0) false) (bv 32 0xff))))) (set result (| (cast 32 false (<< (var result_byte3) (bv 32 0x18) false)) (| (cast 32 false (<< (var result_byte2) (bv 32 0x10) false)) (| (cast 32 false (<< (var result_byte1) (bv 32 0x8) false)) (cast 32 false (var result_byte0)))))) (set d0 (var result)) (set ov3 (|| (! (ule (var result_byte3) (bv 8 0x7f))) (&& (sle (var result_byte3) (bv 8 0x80)) (! (== (var result_byte3) (bv 8 0x80)))))) (set ov2 (|| (! (ule (var result_byte2) (bv 8 0x7f))) (&& (sle (var result_byte2) (bv 8 0x80)) (! (== (var result_byte2) (bv 8 0x80)))))) (set ov1 (|| (! (ule (var result_byte1) (bv 8 0x7f))) (&& (sle (var result_byte1) (bv 8 0x80)) (! (== (var result_byte1) (bv 8 0x80)))))) (set ov0 (|| (! (ule (var result_byte0) (bv 8 0x7f))) (&& (sle (var result_byte0) (bv 8 0x80)) (! (== (var result_byte0) (bv 8 0x80)))))) (set overflow (|| (|| (var ov1) (var ov0)) (|| (var ov3) (var ov2)))) (set aov3 (^^ (! (is_zero (& (>> (var result_byte3) (bv 8 0x7) false) (bv 8 0x1)))) (! (is_zero (& (>> (var result_byte3) (bv 8 0x6) false) (bv 8 0x1)))))) (set aov2 (^^ (! (is_zero (& (>> (var result_byte2) (bv 8 0x7) false) (bv 8 0x1)))) (! (is_zero (& (>> (var result_byte2) (bv 8 0x6) false) (bv 8 0x1)))))) (set aov1 (^^ (! (is_zero (& (>> (var result_byte1) (bv 8 0x7) false) (bv 8 0x1)))) (! (is_zero (& (>> (var result_byte1) (bv 8 0x6) false) (bv 8 0x1)))))) (set aov0 (^^ (! (is_zero (& (>> (var result_byte0) (bv 8 0x7) false) (bv 8 0x1)))) (! (is_zero (& (>> (var result_byte0) (bv 8 0x6) false) (bv 8 0x1)))))) (set advanced_overflow (|| (|| (var aov1) (var aov0)) (|| (var aov3) (var aov2)))) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (ite (var overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1e) false))) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (ite (var advanced_overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1c) false))) (branch (var overflow) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (branch (var advanced_overflow) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop))
d "sub.b d0, d6, d6" 0b668004 0x000000 (seq (set result_byte3 (- (cast 8 false (& (>> (var d6) (bv 32 0x18) false) (bv 32 0xff))) (cast 8 false (& (>> (var d6) (bv 32 0x18) false) (bv 32 0xff))))) (set result_byte2 (- (cast 8 false (& (>> (var d6) (bv 32 0x10) false) (bv 32 0xff))) (cast 8 false (& (>> (var d6) (bv 32 0x10) false) (bv 32 0xff))))) (set result_byte1 (- (cast 8 false (& (>> (var d6) (bv 32 0x8) false) (bv 32 0xff))) (cast 8 false (& (>> (var d6) (bv 32 0x8) false) (bv 32 0xff))))) (set result_byte0 (- (cast 8 false (& (>> (var d6) (bv 32 0x0) false) (bv 32 0xff))) (cast 8 false (& (>> (var d6) (bv 32 0x0) false) (bv 32 0xff))))) (set result (| (cast 32 false (<< (var result_byte3) (bv 32 0x18) false)) (| (cast 32 false (<< (var result_byte2) (bv 32 0x10) false)) (| (cast 32 false (<< (var result_byte1) (bv 32 0x8) false)) (cast 32 false (var result_byte0)))))) (set d0 (var result)) (set ov3 (|| (! (ule (var result_byte3) (bv 8 0x7f))) (&& (sle (var result_byte3) (bv 8 0x80)) (! (== (var result_byte3) (bv 8 0x80)))))) (set ov2 (|| (! (ule (var result_byte2) (bv 8 0x7f))) (&& (sle (var result_byte2) (bv 8 0x80)) (! (== (var result_byte2) (bv 8 0x80)))))) (set ov1 (|| (! (ule (var result_byte1) (bv 8 0x7f))) (&& (sle (var result_byte1) (bv 8 0x80)) (! (== (var result_byte1) (bv 8 0x80)))))) (set ov0 (|| (! (ule (var result_byte0) (bv 8 0x7f))) (&& (sle (var result_byte0) (bv 8 0x80)) (! (== (var result_byte0) (bv 8 0x80)))))) (set overflow (|| (|| (var ov1) (var ov0)) (|| (var ov3) (var ov2)))) (set aov3 (^^ (! (is_zero (& (>> (var result_byte3) (bv 8 0x7) false) (bv 8 0x1)))) (! (is_zero (& (>> (var result_byte3) (bv 8 0x6) false) (bv 8 0x1)))))) (set aov2 (^^ (! (is_zero (& (>> (var result_byte2) (bv 8 0x7) false) (bv 8 0x1)))) (! (is_zero (& (>> (var result_byte2) (bv 8 0x6) false) (bv 8 0x1)))))) (set aov1 (^^ (! (is_zero (& (>> (var result_byte1) (bv 8 0x7) false) (bv 8 0x1)))) (! (is_zero (& (>> (var result_byte1) (bv 8 0x6) false) (bv 8 0x1)))))) (set aov0 (^^ (! (is_zero (& (>> (var result_byte0) (bv 8 0x7) false) (bv 8 0x1)))) (! (is_zero (& (>> (var result_byte0) (bv 8 0x6) false) (bv 8 0x1)))))) (set advanced_overflow (|| (|| (var aov1) (var aov0)) (|| (var aov3) (var aov2)))) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (ite (var overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1e) false))) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (ite (var advanced_overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1c) false))) (branch (var overflow) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (branch (var advanced_overflow) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop))
d "sub.f d11, d12, d10" 6b0a31bc 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d12) ))) (set _fb (fconvert ieee754-bin64 rne (float 0 (var d10) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _arg_b (let tmp (var _fb) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _precise_result (+. rne (fneg (var _arg_a)) (var _arg_b))) (set _normal_result (let tmp (var _precise_result) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _rounded_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _normal_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (|| (is_nan (var _fa)) (is_nan (var _fb))) (float 0 (bv 32 0x7fc00001) ) (ite (&& (is_inf (var _fa)) (is_inf (var _fb))) (float 0 (bv 32 0x7f800001) ) (var _rounded_result)))) (set d11 (fbits (var _result))) (set set_FI (|| (is_nan (var _fa)) (is_nan (var _fb)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set set_FV (&& (! (|| (is_nan (var _rounded_result)) (is_nan (float 0 (bv 32 0x7f800000) )))) (! (<. (var _rounded_result) (float 0 (bv 32 0x7f800000) ))))) (branch (var set_FV) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set set_FU (&& (! (|| (is_nan (fpos (var _precise_result))) (is_nan (float 1 (bv 64 0x3820000000000000) )))) (<. (fpos (var _precise_result)) (float 1 (bv 64 0x3820000000000000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (fconvert ieee754-bin64 rne (var _result)))) (|| (<. (var _precise_result) (fconvert ieee754-bin64 rne (var _result))) (<. (fconvert ieee754-bin64 rne (var _result)) (var _precise_result))))) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (ite (&& (var set_FX) (! (var set_FI))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1a) false))) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (|| (var set_FI) (|| (var set_FV) (|| (var set_FU) (var set_FX)))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "sub.f d7, d13, d3" 6b03317d 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d13) ))) (set _fb (fconvert ieee754-bin64 rne (float 0 (var d3) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _arg_b (let tmp (var _fb) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _precise_result (+. rne (fneg (var _arg_a)) (var _arg_b))) (set _normal_result (let tmp (var _precise_result) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _rounded_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _normal_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (|| (is_nan (var _fa)) (is_nan (var _fb))) (float 0 (bv 32 0x7fc00001) ) (ite (&& (is_inf (var _fa)) (is_inf (var _fb))) (float 0 (bv 32 0x7f800001) ) (var _rounded_result)))) (set d7 (fbits (var _result))) (set set_FI (|| (is_nan (var _fa)) (is_nan (var _fb)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set set_FV (&& (! (|| (is_nan (var _rounded_result)) (is_nan (float 0 (bv 32 0x7f800000) )))) (! (<. (var _rounded_result) (float 0 (bv 32 0x7f800000) ))))) (branch (var set_FV) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set set_FU (&& (! (|| (is_nan (fpos (var _precise_result))) (is_nan (float 1 (bv 64 0x3820000000000000) )))) (<. (fpos (var _precise_result)) (float 1 (bv 64 0x3820000000000000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (fconvert ieee754-bin64 rne (var _result)))) (|| (<. (var _precise_result) (fconvert ieee754-bin64 rne (var _result))) (<. (fconvert ieee754-bin64 rne (var _result)) (var _precise_result))))) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (ite (&& (var set_FX) (! (var set_FI))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1a) false))) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (|| (var set_FI) (|| (var set_FV) (|| (var set_FU) (var set_FX)))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "sub.f d3, d6, d8" 6b083136 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d6) ))) (set _fb (fconvert ieee754-bin64 rne (float 0 (var d8) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _arg_b (let tmp (var _fb) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _precise_result (+. rne (fneg (var _arg_a)) (var _arg_b))) (set _normal_result (let tmp (var _precise_result) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _rounded_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _normal_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (|| (is_nan (var _fa)) (is_nan (var _fb))) (float 0 (bv 32 0x7fc00001) ) (ite (&& (is_inf (var _fa)) (is_inf (var _fb))) (float 0 (bv 32 0x7f800001) ) (var _rounded_result)))) (set d3 (fbits (var _result))) (set set_FI (|| (is_nan (var _fa)) (is_nan (var _fb)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set set_FV (&& (! (|| (is_nan (var _rounded_result)) (is_nan (float 0 (bv 32 0x7f800000) )))) (! (<. (var _rounded_result) (float 0 (bv 32 0x7f800000) ))))) (branch (var set_FV) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set set_FU (&& (! (|| (is_nan (fpos (var _precise_result))) (is_nan (float 1 (bv 64 0x3820000000000000) )))) (<. (fpos (var _precise_result)) (float 1 (bv 64 0x3820000000000000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (fconvert ieee754-bin64 rne (var _result)))) (|| (<. (var _precise_result) (fconvert ieee754-bin64 rne (var _result))) (<. (fconvert ieee754-bin64 rne (var _result)) (var _precise_result))))) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (ite (&& (var set_FX) (! (var set_FI))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1a) false))) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (|| (var set_FI) (|| (var set_FV) (|| (var set_FU) (var set_FX)))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "sub.f d11, d12, d10" 6b0a31bc 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d12) ))) (set _fb (fconvert ieee754-bin64 rne (float 0 (var d10) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _arg_b (let tmp (var _fb) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _precise_result (+. rne (fneg (var _arg_a)) (var _arg_b))) (set _normal_result (let tmp (var _precise_result) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _rounded_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _normal_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (|| (is_nan (var _fa)) (is_nan (var _fb))) (float 0 (bv 32 0x7fc00001) ) (ite (&& (is_inf (var _fa)) (is_inf (var _fb))) (float 0 (bv 32 0x7f800001) ) (var _rounded_result)))) (set d11 (fbits (var _result))) (set set_FI (|| (is_nan (var _fa)) (is_nan (var _fb)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set set_FV (&& (! (|| (is_nan (var _rounded_result)) (is_nan (float 0 (bv 32 0x7f800000) )))) (! (<. (var _rounded_result) (float 0 (bv 32 0x7f800000) ))))) (branch (var set_FV) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set set_FU (&& (! (|| (is_nan (fabs (var _precise_result))) (is_nan (float 1 (bv 64 0x3820000000000000) )))) (<. (fabs (var _precise_result)) (float 1 (bv 64 0x3820000000000000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (fconvert ieee754-bin64 rne (var _result)))) (|| (<. (var _precise_result) (fconvert ieee754-bin64 rne (var _result))) (<. (fconvert ieee754-bin64 rne (var _result)) (var _precise_result))))) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (ite (&& (var set_FX) (! (var set_FI))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1a) false))) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (|| (var set_FI) (|| (var set_FV) (|| (var set_FU) (var set_FX)))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "sub.f d7, d13, d3" 6b03317d 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d13) ))) (set _fb (fconvert ieee754-bin64 rne (float 0 (var d3) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _arg_b (let tmp (var _fb) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _precise_result (+. rne (fneg (var _arg_a)) (var _arg_b))) (set _normal_result (let tmp (var _precise_result) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _rounded_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _normal_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (|| (is_nan (var _fa)) (is_nan (var _fb))) (float 0 (bv 32 0x7fc00001) ) (ite (&& (is_inf (var _fa)) (is_inf (var _fb))) (float 0 (bv 32 0x7f800001) ) (var _rounded_result)))) (set d7 (fbits (var _result))) (set set_FI (|| (is_nan (var _fa)) (is_nan (var _fb)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set set_FV (&& (! (|| (is_nan (var _rounded_result)) (is_nan (float 0 (bv 32 0x7f800000) )))) (! (<. (var _rounded_result) (float 0 (bv 32 0x7f800000) ))))) (branch (var set_FV) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set set_FU (&& (! (|| (is_nan (fabs (var _precise_result))) (is_nan (float 1 (bv 64 0x3820000000000000) )))) (<. (fabs (var _precise_result)) (float 1 (bv 64 0x3820000000000000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (fconvert ieee754-bin64 rne (var _result)))) (|| (<. (var _precise_result) (fconvert ieee754-bin64 rne (var _result))) (<. (fconvert ieee754-bin64 rne (var _result)) (var _precise_result))))) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (ite (&& (var set_FX) (! (var set_FI))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1a) false))) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (|| (var set_FI) (|| (var set_FV) (|| (var set_FU) (var set_FX)))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "sub.f d3, d6, d8" 6b083136 0x0 (seq (set _fa (fconvert ieee754-bin64 rne (float 0 (var d6) ))) (set _fb (fconvert ieee754-bin64 rne (float 0 (var d8) ))) (set _arg_a (let tmp (var _fa) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _arg_b (let tmp (var _fb) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _precise_result (+. rne (fneg (var _arg_a)) (var _arg_b))) (set _normal_result (let tmp (var _precise_result) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (var tmp) (float 1 (bv 64 0x0) ))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (float 1 (bv 64 0x3810000000000000) ) (var tmp)))) (fneg (float 1 (bv 64 0x0) )) (ite (&& (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x0) )))) (<. (float 1 (bv 64 0x0) ) (var tmp))) (&& (! (|| (is_nan (var tmp)) (is_nan (float 1 (bv 64 0x3810000000000000) )))) (<. (var tmp) (float 1 (bv 64 0x3810000000000000) )))) (float 1 (bv 64 0x0) ) (var tmp))))) (set _rounded_result (let _mode (cast 8 false (& (>> (var PSW) (bv 32 0x18) false) (bv 32 0x3))) (let _x (var _normal_result) (ite (== (var _mode) (bv 8 0x0)) (fconvert ieee754-bin32 rne (var _x)) (ite (== (var _mode) (bv 8 0x1)) (fconvert ieee754-bin32 rna (var _x)) (ite (== (var _mode) (bv 8 0x2)) (fconvert ieee754-bin32 rtn (var _x)) (ite (== (var _mode) (bv 8 0x3)) (fconvert ieee754-bin32 rtp (var _x)) (ite (== (var _mode) (bv 8 0x4)) (fconvert ieee754-bin32 rtz (var _x)) (float 0 (bv 32 0x0) ))))))))) (set _result (ite (|| (is_nan (var _fa)) (is_nan (var _fb))) (float 0 (bv 32 0x7fc00001) ) (ite (&& (is_inf (var _fa)) (is_inf (var _fb))) (float 0 (bv 32 0x7f800001) ) (var _rounded_result)))) (set d3 (fbits (var _result))) (set set_FI (|| (is_nan (var _fa)) (is_nan (var _fb)))) (branch (var set_FI) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (set set_FV (&& (! (|| (is_nan (var _rounded_result)) (is_nan (float 0 (bv 32 0x7f800000) )))) (! (<. (var _rounded_result) (float 0 (bv 32 0x7f800000) ))))) (branch (var set_FV) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set set_FU (&& (! (|| (is_nan (fabs (var _precise_result))) (is_nan (float 1 (bv 64 0x3820000000000000) )))) (<. (fabs (var _precise_result)) (float 1 (bv 64 0x3820000000000000) )))) (branch (var set_FU) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop) (set set_FX (|| (|| (is_nan (var _precise_result)) (is_nan (fconvert ieee754-bin64 rne (var _result)))) (|| (<. (var _precise_result) (fconvert ieee754-bin64 rne (var _result))) (<. (fconvert ieee754-bin64 rne (var _result)) (var _precise_result))))) (set PSW (| (& (var PSW) (bv 32 0xfbffffff)) (<< (& (ite (&& (var set_FX) (! (var set_FI))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1a) false))) (set PSW (| (& (var PSW) (bv 32 0x7fffffff)) (<< (& (ite (|| (var set_FI) (|| (var set_FV) (|| (var set_FU) (var set_FX)))) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1f) false))))
d "sub.h d1, d9, d12" 0bc98016 0x000000 (seq (set result_hw1 (- (cast 16 false (& (>> (var d9) (bv 32 0x10) false) (bv 32 0xffff))) (cast 16 false (& (>> (var d12) (bv 32 0x10) false) (bv 32 0xffff))))) (set result_hw0 (- (cast 16 false (& (>> (var d9) (bv 32 0x0) false) (bv 32 0xffff))) (cast 16 false (& (>> (var d12) (bv 32 0x0) false) (bv 32 0xffff))))) (set result (| (cast 32 false (<< (var result_hw1) (bv 32 0x10) false)) (cast 32 false (var result_hw0)))) (set d1 (var result)) (set ov1 (|| (! (ule (var result_hw1) (bv 16 0x7fff))) (&& (sle (var result_hw1) (bv 16 0x8000)) (! (== (var result_hw1) (bv 16 0x8000)))))) (set ov0 (|| (! (ule (var result_hw0) (bv 16 0x7fff))) (&& (sle (var result_hw0) (bv 16 0x8000)) (! (== (var result_hw0) (bv 16 0x8000)))))) (set overflow (|| (var ov1) (var ov0))) (set aov1 (^^ (! (is_zero (& (>> (var result_hw1) (bv 16 0xf) false) (bv 16 0x1)))) (! (is_zero (& (>> (var result_hw1) (bv 16 0xe) false) (bv 16 0x1)))))) (set aov0 (^^ (! (is_zero (& (>> (var result_hw0) (bv 16 0xf) false) (bv 16 0x1)))) (! (is_zero (& (>> (var result_hw0) (bv 16 0xe) false) (bv 16 0x1)))))) (set advanced_overflow (|| (var aov1) (var aov0))) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (ite (var overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1e) false))) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (ite (var advanced_overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1c) false))) (branch (var overflow) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (branch (var advanced_overflow) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop))
d "sub.h d9, d9, d9" 0b998096 0x000000 (seq (set result_hw1 (- (cast 16 false (& (>> (var d9) (bv 32 0x10) false) (bv 32 0xffff))) (cast 16 false (& (>> (var d9) (bv 32 0x10) false) (bv 32 0xffff))))) (set result_hw0 (- (cast 16 false (& (>> (var d9) (bv 32 0x0) false) (bv 32 0xffff))) (cast 16 false (& (>> (var d9) (bv 32 0x0) false) (bv 32 0xffff))))) (set result (| (cast 32 false (<< (var result_hw1) (bv 32 0x10) false)) (cast 32 false (var result_hw0)))) (set d9 (var result)) (set ov1 (|| (! (ule (var result_hw1) (bv 16 0x7fff))) (&& (sle (var result_hw1) (bv 16 0x8000)) (! (== (var result_hw1) (bv 16 0x8000)))))) (set ov0 (|| (! (ule (var result_hw0) (bv 16 0x7fff))) (&& (sle (var result_hw0) (bv 16 0x8000)) (! (== (var result_hw0) (bv 16 0x8000)))))) (set overflow (|| (var ov1) (var ov0))) (set aov1 (^^ (! (is_zero (& (>> (var result_hw1) (bv 16 0xf) false) (bv 16 0x1)))) (! (is_zero (& (>> (var result_hw1) (bv 16 0xe) false) (bv 16 0x1)))))) (set aov0 (^^ (! (is_zero (& (>> (var result_hw0) (bv 16 0xf) false) (bv 16 0x1)))) (! (is_zero (& (>> (var result_hw0) (bv 16 0xe) false) (bv 16 0x1)))))) (set advanced_overflow (|| (var aov1) (var aov0))) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (ite (var overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1e) false))) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (ite (var advanced_overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1c) false))) (branch (var overflow) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (branch (var advanced_overflow) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop))
d "sub.h d8, d7, d13" 0bd78086 0x000000 (seq (set result_hw1 (- (cast 16 false (& (>> (var d7) (bv 32 0x10) false) (bv 32 0xffff))) (cast 16 false (& (>> (var d13) (bv 32 0x10) false) (bv 32 0xffff))))) (set result_hw0 (- (cast 16 false (& (>> (var d7) (bv 32 0x0) false) (bv 32 0xffff))) (cast 16 false (& (>> (var d13) (bv 32 0x0) false) (bv 32 0xffff))))) (set result (| (cast 32 false (<< (var result_hw1) (bv 32 0x10) false)) (cast 32 false (var result_hw0)))) (set d8 (var result)) (set ov1 (|| (! (ule (var result_hw1) (bv 16 0x7fff))) (&& (sle (var result_hw1) (bv 16 0x8000)) (! (== (var result_hw1) (bv 16 0x8000)))))) (set ov0 (|| (! (ule (var result_hw0) (bv 16 0x7fff))) (&& (sle (var result_hw0) (bv 16 0x8000)) (! (== (var result_hw0) (bv 16 0x8000)))))) (set overflow (|| (var ov1) (var ov0))) (set aov1 (^^ (! (is_zero (& (>> (var result_hw1) (bv 16 0xf) false) (bv 16 0x1)))) (! (is_zero (& (>> (var result_hw1) (bv 16 0xe) false) (bv 16 0x1)))))) (set aov0 (^^ (! (is_zero (& (>> (var result_hw0) (bv 16 0xf) false) (bv 16 0x1)))) (! (is_zero (& (>> (var result_hw0) (bv 16 0xe) false) (bv 16 0x1)))))) (set advanced_overflow (|| (var aov1) (var aov0))) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (ite (var overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1e) false))) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (ite (var advanced_overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1c) false))) (branch (var overflow) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (branch (var advanced_overflow) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop))

4
test/db/asm/xtensa
View file

@ -1,5 +1,5 @@
d "abs a1, a0" 001160 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (ite (! (sle (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (bv 32 0x0))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (~- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))))
d "abs.s f1, f2" 1012fa 0x0 (set f1 (cast 64 false (fbits (fpos (float 0 (var f2) )))))
d "abs.s f1, f2" 1012fa 0x0 (set f1 (cast 64 false (fbits (fabs (float 0 (var f2) )))))
d "add a0, a0, a0" 000080 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))))
d "add.s f0, f0, f0" 00000a 0x0 (seq (set fres (+. rna (float 0 (var f0) ) (float 0 (var f0) ))) (set f0 (cast 64 false (fbits (var fres)))) (set fsr_v (var fres)) nop (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false))) (& (<< (ite (fexcept e_invalid_op (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0xb) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0xb) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false))) (& (<< (ite (fexcept e_inexact (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x7) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x7) false)))) (set fsr (| (& (var fsr) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x9) false))) (& (<< (ite (fexcept e_overflow (var fsr_v)) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x9) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false) (bv 32 0x9) false)))))
d "add.n a0, a0, a0" 0a00 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (+ (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))) (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x0) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))))
@ -196,7 +196,7 @@ d "mulsh a2, a3, a1" 1023b2 0x0 (seq (set ars (>> (cast 64 false (<< (loadw 1 32
d "muluh a2, a3, a1" 1023a2 0x0 (seq (set ars (cast 64 false (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x3) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) (set art (cast 64 false (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false)))))) (set tp (* (var ars) (var art))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (cast 32 false (>> (var tp) (bv 32 0x20) false))))
d "neg a2, a1" 102060 0x0 (storew 1 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (~- (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))))
d "neg.s f1, f2" 6012fa 0x0 (set f1 (cast 64 false (fbits (fneg (float 0 (var f2) )))))
d "nexp01.s f1, f2" b012fa 0x0 (seq (set rs (var f2)) (set frs (float 0 (var rs) )) (set frs64 (fconvert ieee754-bin64 rna (var frs))) (set rs31 (<< (ite (! (ite (== (& (>> (var rs) (bv 32 0x1f) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x1)) false)) (bv 64 0x0)) false true)) (bv 64 0x1) (bv 64 0x0)) (bv 32 0x1f) false)) (set f1 (ite (== (& (>> (var rs) (bv 32 0x17) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x8)) false)) (bv 64 0xff)) (| (& (>> (var rs) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x17)) false)) (| (bv 64 0x3f800000) (var rs31))) (ite (== (& (>> (var rs) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x1f)) false)) (bv 64 0x0)) (| (bv 64 0x40000000) (var rs31)) (let N (/. rna (fpos (var frs64)) (float 1 (bv 64 0x4000000000000000) )) (fbits (fneg (/. rna (var frs64) (pow rna (float 1 (bv 64 0x4010000000000000) ) (var N))))))))))
d "nexp01.s f1, f2" b012fa 0x0 (seq (set rs (var f2)) (set frs (float 0 (var rs) )) (set frs64 (fconvert ieee754-bin64 rna (var frs))) (set rs31 (<< (ite (! (ite (== (& (>> (var rs) (bv 32 0x1f) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x1)) false)) (bv 64 0x0)) false true)) (bv 64 0x1) (bv 64 0x0)) (bv 32 0x1f) false)) (set f1 (ite (== (& (>> (var rs) (bv 32 0x17) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x8)) false)) (bv 64 0xff)) (| (& (>> (var rs) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x17)) false)) (| (bv 64 0x3f800000) (var rs31))) (ite (== (& (>> (var rs) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x1f)) false)) (bv 64 0x0)) (| (bv 64 0x40000000) (var rs31)) (let N (/. rna (fabs (var frs64)) (float 1 (bv 64 0x4000000000000000) )) (fbits (fneg (/. rna (var frs64) (pow rna (float 1 (bv 64 0x4010000000000000) ) (var N))))))))))
d "nop" f02000 0x0 nop
d "nsa a1, a2" 10e240 0x0 (seq (set ars (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (set sign (& (>> (var ars) (bv 32 0x1f) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false))) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (ite (== (var sign) (& (>> (var ars) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1f)) false))) (bv 32 0x1f) (let b4 (== (var sign) (& (>> (var ars) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0xf)) false))) (let t3 (ite (var b4) (& (>> (var ars) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false)) (& (>> (var ars) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (let b3 (== (var sign) (& (>> (var t3) (bv 32 0x8) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x8)) false))) (let t2 (ite (var b3) (& (>> (var t3) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x8)) false)) (& (>> (var t3) (bv 32 0x8) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x8)) false))) (let b2 (== (var sign) (& (>> (var t2) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false))) (let t1 (ite (var b2) (& (>> (var t2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false)) (& (>> (var t2) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false))) (let b1 (== (var sign) (& (>> (var t1) (bv 32 0x2) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false))) (let b0 (ite (var b1) (== (& (>> (var t1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (var sign)) (== (& (>> (var t1) (bv 32 0x3) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (var sign))) (- (| (<< (ite (var b4) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x4) false) (| (<< (ite (var b3) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x3) false) (| (<< (ite (var b2) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x2) false) (| (<< (ite (var b1) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1) false) (ite (var b0) (bv 32 0x1) (bv 32 0x0)))))) (bv 32 0x1)))))))))))))
d "nsau a1, a2" 10f240 0x0 (seq (set ars (loadw 1 32 (* (bv 32 0x4) (| (bv 32 0x2) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))))) (set sign (bv 32 0x0)) (storew 1 (* (bv 32 0x4) (| (bv 32 0x1) (<< (+ (var windowbase) (bv 32 0x0)) (bv 32 0x2) false))) (ite (== (var sign) (var ars)) (bv 32 0x20) (let b4 (== (var sign) (& (>> (var ars) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (let t3 (ite (var b4) (& (>> (var ars) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false)) (& (>> (var ars) (bv 32 0x10) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (let b3 (== (var sign) (& (>> (var t3) (bv 32 0x8) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x8)) false))) (let t2 (ite (var b3) (& (>> (var t3) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x8)) false)) (& (>> (var t3) (bv 32 0x8) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x8)) false))) (let b2 (== (var sign) (& (>> (var t2) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false))) (let t1 (ite (var b2) (& (>> (var t2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false)) (& (>> (var t2) (bv 32 0x4) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x4)) false))) (let b1 (== (var sign) (& (>> (var t1) (bv 32 0x2) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x2)) false))) (let b0 (ite (var b1) (== (& (>> (var t1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (var sign)) (== (& (>> (var t1) (bv 32 0x3) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x1)) false)) (var sign))) (| (<< (ite (var b4) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x4) false) (| (<< (ite (var b3) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x3) false) (| (<< (ite (var b2) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x2) false) (| (<< (ite (var b1) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1) false) (ite (var b0) (bv 32 0x1) (bv 32 0x0)))))))))))))))))