Add Hexagon register profile (#2490)
Although the reg profile was not really used yet it will be relevant for the RZIL uplifting. Introduces: * Double/quadruple registers now properly overlap with their counterparts. * Registers have correct types assigned (vec, ctr, sys etc. Before, all regs were of type gbr) * Consistent register names (asm name style: c3:2, r31 etc, alias style: lc1:sa1, lr etc.) * Adds _tmp registers in the profile. Later used by uplifted instructions (think of .new registers).
This commit is contained in:
Rot127
GitHub
parent
348ed19ad6
commit
10bedc2b00
14 changed files with 5415 additions and 4740 deletions
File diff suppressed because it is too large
Load diff
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@ -3,7 +3,7 @@
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// LLVM commit: 96e220e6886868d6663d966ecc396befffc355e7
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// LLVM commit date: 2022-01-05 11:01:52 +0000 (ISO 8601 format)
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// Date of code generation: 2022-01-24 07:53:55-05:00
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// Date of code generation: 2022-04-02 10:52:25-04:00
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//========================================
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// The following code is generated.
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// Do not edit. Repository of code generator:
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@ -21,159 +21,154 @@
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#include "hexagon_insn.h"
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#include "hexagon_arch.h"
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char *hex_get_ctr_regs(int opcode_reg) {
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char *hex_get_ctr_regs(int opcode_reg, bool get_alias) {
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switch (opcode_reg) {
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default:
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return "<err>";
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case HEX_REG_CTR_REGS_LC0:
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return "LC0";
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case HEX_REG_CTR_REGS_SA0:
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return "SA0";
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case HEX_REG_CTR_REGS_LC1:
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return "LC1";
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case HEX_REG_CTR_REGS_SA1:
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return "SA1";
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case HEX_REG_CTR_REGS_P3_0:
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return "P3:0";
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default: return "<err>";
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case HEX_REG_CTR_REGS_C1:
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return get_alias ? "LC0" : "C1";
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case HEX_REG_CTR_REGS_C0:
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return get_alias ? "SA0" : "C0";
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case HEX_REG_CTR_REGS_C3:
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return get_alias ? "LC1" : "C3";
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case HEX_REG_CTR_REGS_C2:
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return get_alias ? "SA1" : "C2";
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case HEX_REG_CTR_REGS_C4:
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return get_alias ? "P3:0" : "C4";
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case HEX_REG_CTR_REGS_C5:
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return "C5";
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case HEX_REG_CTR_REGS_PC:
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return "PC";
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case HEX_REG_CTR_REGS_UGP:
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return "UGP";
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case HEX_REG_CTR_REGS_GP:
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return "GP";
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case HEX_REG_CTR_REGS_CS0:
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return "CS0";
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case HEX_REG_CTR_REGS_CS1:
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return "CS1";
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case HEX_REG_CTR_REGS_UPCYCLELO:
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return "UPCYCLELO";
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case HEX_REG_CTR_REGS_UPCYCLEHI:
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return "UPCYCLEHI";
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case HEX_REG_CTR_REGS_FRAMELIMIT:
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return "FRAMELIMIT";
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case HEX_REG_CTR_REGS_FRAMEKEY:
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return "FRAMEKEY";
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case HEX_REG_CTR_REGS_PKTCOUNTLO:
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return "PKTCOUNTLO";
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case HEX_REG_CTR_REGS_PKTCOUNTHI:
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return "PKTCOUNTHI";
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case HEX_REG_CTR_REGS_UTIMERLO:
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return "UTIMERLO";
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case HEX_REG_CTR_REGS_UTIMERHI:
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return "UTIMERHI";
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case HEX_REG_CTR_REGS_M0:
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return "M0";
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case HEX_REG_CTR_REGS_M1:
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return "M1";
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case HEX_REG_CTR_REGS_USR:
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return "USR";
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return get_alias ? "C5" : "C5";
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case HEX_REG_CTR_REGS_C9:
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return get_alias ? "PC" : "C9";
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case HEX_REG_CTR_REGS_C10:
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return get_alias ? "UGP" : "C10";
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case HEX_REG_CTR_REGS_C11:
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return get_alias ? "GP" : "C11";
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case HEX_REG_CTR_REGS_C12:
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return get_alias ? "CS0" : "C12";
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case HEX_REG_CTR_REGS_C13:
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return get_alias ? "CS1" : "C13";
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case HEX_REG_CTR_REGS_C14:
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return get_alias ? "UPCYCLELO" : "C14";
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case HEX_REG_CTR_REGS_C15:
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return get_alias ? "UPCYCLEHI" : "C15";
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case HEX_REG_CTR_REGS_C16:
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return get_alias ? "FRAMELIMIT" : "C16";
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case HEX_REG_CTR_REGS_C17:
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return get_alias ? "FRAMEKEY" : "C17";
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case HEX_REG_CTR_REGS_C18:
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return get_alias ? "PKTCOUNTLO" : "C18";
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case HEX_REG_CTR_REGS_C19:
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return get_alias ? "PKTCOUNTHI" : "C19";
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case HEX_REG_CTR_REGS_C30:
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return get_alias ? "UTIMERLO" : "C30";
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case HEX_REG_CTR_REGS_C31:
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return get_alias ? "UTIMERHI" : "C31";
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case HEX_REG_CTR_REGS_C6:
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return get_alias ? "M0" : "C6";
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case HEX_REG_CTR_REGS_C7:
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return get_alias ? "M1" : "C7";
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case HEX_REG_CTR_REGS_C8:
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return get_alias ? "USR" : "C8";
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}
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}
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char *hex_get_ctr_regs64(int opcode_reg) {
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char *hex_get_ctr_regs64(int opcode_reg, bool get_alias) {
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switch (opcode_reg) {
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default:
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return "<err>";
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default: return "<err>";
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case HEX_REG_CTR_REGS64_C1_0:
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return "C1:0";
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return get_alias ? "LC0:SA0" : "C1:0";
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case HEX_REG_CTR_REGS64_C3_2:
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return "C3:2";
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return get_alias ? "LC1:SA1" : "C3:2";
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case HEX_REG_CTR_REGS64_C5_4:
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return "C5:4";
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case HEX_REG_CTR_REGS64_C7_6:
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return "C7:6";
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return get_alias ? "M1:0" : "C7:6";
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case HEX_REG_CTR_REGS64_C9_8:
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return "C9:8";
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case HEX_REG_CTR_REGS64_C11_10:
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return "C11:10";
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case HEX_REG_CTR_REGS64_CS:
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return "C13:12";
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case HEX_REG_CTR_REGS64_UPCYCLE:
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return "C15:14";
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case HEX_REG_CTR_REGS64_C13_12:
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return get_alias ? "CS1:0" : "C13:12";
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case HEX_REG_CTR_REGS64_C15_14:
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return get_alias ? "UPCYCLE" : "C15:14";
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case HEX_REG_CTR_REGS64_C17_16:
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return "C17:16";
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case HEX_REG_CTR_REGS64_PKTCOUNT:
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return "C19:18";
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case HEX_REG_CTR_REGS64_UTIMER:
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return "C31:30";
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case HEX_REG_CTR_REGS64_C19_18:
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return get_alias ? "PKTCOUNT" : "C19:18";
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case HEX_REG_CTR_REGS64_C31_30:
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return get_alias ? "UTIMER" : "C31:30";
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}
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}
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char *hex_get_double_regs(int opcode_reg) {
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char *hex_get_double_regs(int opcode_reg, bool get_alias) {
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switch (opcode_reg) {
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default:
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return "<err>";
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case HEX_REG_DOUBLE_REGS_D0:
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default: return "<err>";
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case HEX_REG_DOUBLE_REGS_R1_0:
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return "R1:0";
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case HEX_REG_DOUBLE_REGS_D1:
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case HEX_REG_DOUBLE_REGS_R3_2:
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return "R3:2";
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case HEX_REG_DOUBLE_REGS_D2:
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case HEX_REG_DOUBLE_REGS_R5_4:
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return "R5:4";
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case HEX_REG_DOUBLE_REGS_D3:
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case HEX_REG_DOUBLE_REGS_R7_6:
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return "R7:6";
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case HEX_REG_DOUBLE_REGS_D4:
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case HEX_REG_DOUBLE_REGS_R9_8:
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return "R9:8";
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case HEX_REG_DOUBLE_REGS_D6:
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case HEX_REG_DOUBLE_REGS_R13_12:
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return "R13:12";
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case HEX_REG_DOUBLE_REGS_D7:
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case HEX_REG_DOUBLE_REGS_R15_14:
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return "R15:14";
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case HEX_REG_DOUBLE_REGS_D8:
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case HEX_REG_DOUBLE_REGS_R17_16:
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return "R17:16";
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case HEX_REG_DOUBLE_REGS_D9:
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case HEX_REG_DOUBLE_REGS_R19_18:
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return "R19:18";
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case HEX_REG_DOUBLE_REGS_D10:
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case HEX_REG_DOUBLE_REGS_R21_20:
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return "R21:20";
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case HEX_REG_DOUBLE_REGS_D11:
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case HEX_REG_DOUBLE_REGS_R23_22:
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return "R23:22";
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case HEX_REG_DOUBLE_REGS_D12:
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case HEX_REG_DOUBLE_REGS_R25_24:
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return "R25:24";
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case HEX_REG_DOUBLE_REGS_D13:
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case HEX_REG_DOUBLE_REGS_R27_26:
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return "R27:26";
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case HEX_REG_DOUBLE_REGS_D5:
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case HEX_REG_DOUBLE_REGS_R11_10:
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return "R11:10";
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case HEX_REG_DOUBLE_REGS_D14:
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case HEX_REG_DOUBLE_REGS_R29_28:
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return "R29:28";
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case HEX_REG_DOUBLE_REGS_D15:
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return "R31:30";
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case HEX_REG_DOUBLE_REGS_R31_30:
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return get_alias ? "LR:FP" : "R31:30";
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}
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}
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char *hex_get_general_double_low8_regs(int opcode_reg) {
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char *hex_get_general_double_low8_regs(int opcode_reg, bool get_alias) {
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opcode_reg = opcode_reg << 1;
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if (opcode_reg > 6) { // HEX_REG_D3 == 6
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opcode_reg = (opcode_reg & 0x7) | 0x10;
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}
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switch (opcode_reg) {
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default:
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return "<err>";
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case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D11:
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default: return "<err>";
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case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R23_22:
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return "R23:22";
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case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D10:
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case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R21_20:
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return "R21:20";
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case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D9:
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case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R19_18:
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return "R19:18";
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case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D8:
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case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R17_16:
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return "R17:16";
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case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D3:
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case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R7_6:
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return "R7:6";
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case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D2:
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case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R5_4:
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return "R5:4";
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case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D1:
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case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R3_2:
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return "R3:2";
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case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D0:
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case HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R1_0:
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return "R1:0";
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}
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}
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char *hex_get_general_sub_regs(int opcode_reg) {
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char *hex_get_general_sub_regs(int opcode_reg, bool get_alias) {
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if (opcode_reg > 7) { // HEX_REG_R7 == 7
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opcode_reg = (opcode_reg & 0x7) | 0x10;
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}
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switch (opcode_reg) {
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default:
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return "<err>";
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default: return "<err>";
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case HEX_REG_GENERAL_SUB_REGS_R23:
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return "R23";
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case HEX_REG_GENERAL_SUB_REGS_R22:
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@ -209,18 +204,17 @@ char *hex_get_general_sub_regs(int opcode_reg) {
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}
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}
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char *hex_get_guest_regs(int opcode_reg) {
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char *hex_get_guest_regs(int opcode_reg, bool get_alias) {
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switch (opcode_reg) {
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default:
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return "<err>";
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case HEX_REG_GUEST_REGS_GELR:
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return "GELR";
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case HEX_REG_GUEST_REGS_GSR:
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return "GSR";
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case HEX_REG_GUEST_REGS_GOSP:
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return "GOSP";
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default: return "<err>";
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case HEX_REG_GUEST_REGS_G0:
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return get_alias ? "GELR" : "G0";
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case HEX_REG_GUEST_REGS_G1:
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return get_alias ? "GSR" : "G1";
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case HEX_REG_GUEST_REGS_G2:
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return get_alias ? "GOSP" : "G2";
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case HEX_REG_GUEST_REGS_G3:
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return "GBADVA";
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return get_alias ? "GBADVA" : "G3";
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case HEX_REG_GUEST_REGS_G4:
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return "G4";
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case HEX_REG_GUEST_REGS_G5:
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@ -245,14 +239,14 @@ char *hex_get_guest_regs(int opcode_reg) {
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return "G14";
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case HEX_REG_GUEST_REGS_G15:
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return "G15";
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case HEX_REG_GUEST_REGS_GPMUCNT4:
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return "GPMUCNT4";
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case HEX_REG_GUEST_REGS_GPMUCNT5:
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return "GPMUCNT5";
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case HEX_REG_GUEST_REGS_GPMUCNT6:
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return "GPMUCNT6";
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case HEX_REG_GUEST_REGS_GPMUCNT7:
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return "GPMUCNT7";
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case HEX_REG_GUEST_REGS_G16:
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return get_alias ? "GPMUCNT4" : "G16";
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case HEX_REG_GUEST_REGS_G17:
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return get_alias ? "GPMUCNT5" : "G17";
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case HEX_REG_GUEST_REGS_G18:
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return get_alias ? "GPMUCNT6" : "G18";
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case HEX_REG_GUEST_REGS_G19:
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return get_alias ? "GPMUCNT7" : "G19";
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case HEX_REG_GUEST_REGS_G20:
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return "G20";
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case HEX_REG_GUEST_REGS_G21:
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@ -261,18 +255,18 @@ char *hex_get_guest_regs(int opcode_reg) {
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return "G22";
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case HEX_REG_GUEST_REGS_G23:
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return "G23";
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case HEX_REG_GUEST_REGS_GPCYCLELO:
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return "GPCYCLELO";
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case HEX_REG_GUEST_REGS_GPCYCLEHI:
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return "GPCYCLEHI";
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case HEX_REG_GUEST_REGS_GPMUCNT0:
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return "GPMUCNT0";
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case HEX_REG_GUEST_REGS_GPMUCNT1:
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return "GPMUCNT1";
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case HEX_REG_GUEST_REGS_GPMUCNT2:
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return "GPMUCNT2";
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case HEX_REG_GUEST_REGS_GPMUCNT3:
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return "GPMUCNT3";
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case HEX_REG_GUEST_REGS_G24:
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return get_alias ? "GPCYCLELO" : "G24";
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case HEX_REG_GUEST_REGS_G25:
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return get_alias ? "GPCYCLEHI" : "G25";
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case HEX_REG_GUEST_REGS_G26:
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return get_alias ? "GPMUCNT0" : "G26";
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case HEX_REG_GUEST_REGS_G27:
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return get_alias ? "GPMUCNT1" : "G27";
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case HEX_REG_GUEST_REGS_G28:
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return get_alias ? "GPMUCNT2" : "G28";
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case HEX_REG_GUEST_REGS_G29:
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return get_alias ? "GPMUCNT3" : "G29";
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case HEX_REG_GUEST_REGS_G30:
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return "G30";
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case HEX_REG_GUEST_REGS_G31:
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@ -280,10 +274,9 @@ char *hex_get_guest_regs(int opcode_reg) {
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}
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}
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char *hex_get_guest_regs64(int opcode_reg) {
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char *hex_get_guest_regs64(int opcode_reg, bool get_alias) {
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switch (opcode_reg) {
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default:
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return "<err>";
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default: return "<err>";
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case HEX_REG_GUEST_REGS64_G1_0:
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return "G1:0";
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case HEX_REG_GUEST_REGS64_G3_2:
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@ -319,10 +312,9 @@ char *hex_get_guest_regs64(int opcode_reg) {
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}
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}
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char *hex_get_hvx_qr(int opcode_reg) {
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char *hex_get_hvx_qr(int opcode_reg, bool get_alias) {
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switch (opcode_reg) {
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default:
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return "<err>";
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default: return "<err>";
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case HEX_REG_HVX_QR_Q0:
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return "Q0";
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case HEX_REG_HVX_QR_Q1:
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@ -334,33 +326,31 @@ char *hex_get_hvx_qr(int opcode_reg) {
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}
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||||
}
|
||||
|
||||
char *hex_get_hvx_vqr(int opcode_reg) {
|
||||
char *hex_get_hvx_vqr(int opcode_reg, bool get_alias) {
|
||||
switch (opcode_reg) {
|
||||
default:
|
||||
return "<err>";
|
||||
case HEX_REG_HVX_VQR_VQ0:
|
||||
default: return "<err>";
|
||||
case HEX_REG_HVX_VQR_V3_0:
|
||||
return "V3:0";
|
||||
case HEX_REG_HVX_VQR_VQ1:
|
||||
case HEX_REG_HVX_VQR_V7_4:
|
||||
return "V7:4";
|
||||
case HEX_REG_HVX_VQR_VQ2:
|
||||
case HEX_REG_HVX_VQR_V11_8:
|
||||
return "V11:8";
|
||||
case HEX_REG_HVX_VQR_VQ3:
|
||||
case HEX_REG_HVX_VQR_V15_12:
|
||||
return "V15:12";
|
||||
case HEX_REG_HVX_VQR_VQ4:
|
||||
case HEX_REG_HVX_VQR_V19_16:
|
||||
return "V19:16";
|
||||
case HEX_REG_HVX_VQR_VQ5:
|
||||
case HEX_REG_HVX_VQR_V23_20:
|
||||
return "V23:20";
|
||||
case HEX_REG_HVX_VQR_VQ6:
|
||||
case HEX_REG_HVX_VQR_V27_24:
|
||||
return "V27:24";
|
||||
case HEX_REG_HVX_VQR_VQ7:
|
||||
case HEX_REG_HVX_VQR_V31_28:
|
||||
return "V31:28";
|
||||
}
|
||||
}
|
||||
|
||||
char *hex_get_hvx_vr(int opcode_reg) {
|
||||
char *hex_get_hvx_vr(int opcode_reg, bool get_alias) {
|
||||
switch (opcode_reg) {
|
||||
default:
|
||||
return "<err>";
|
||||
default: return "<err>";
|
||||
case HEX_REG_HVX_VR_V0:
|
||||
return "V0";
|
||||
case HEX_REG_HVX_VR_V1:
|
||||
|
|
@ -428,49 +418,47 @@ char *hex_get_hvx_vr(int opcode_reg) {
|
|||
}
|
||||
}
|
||||
|
||||
char *hex_get_hvx_wr(int opcode_reg) {
|
||||
char *hex_get_hvx_wr(int opcode_reg, bool get_alias) {
|
||||
switch (opcode_reg) {
|
||||
default:
|
||||
return "<err>";
|
||||
case HEX_REG_HVX_WR_W0:
|
||||
default: return "<err>";
|
||||
case HEX_REG_HVX_WR_V1_0:
|
||||
return "V1:0";
|
||||
case HEX_REG_HVX_WR_W1:
|
||||
case HEX_REG_HVX_WR_V3_2:
|
||||
return "V3:2";
|
||||
case HEX_REG_HVX_WR_W2:
|
||||
case HEX_REG_HVX_WR_V5_4:
|
||||
return "V5:4";
|
||||
case HEX_REG_HVX_WR_W3:
|
||||
case HEX_REG_HVX_WR_V7_6:
|
||||
return "V7:6";
|
||||
case HEX_REG_HVX_WR_W4:
|
||||
case HEX_REG_HVX_WR_V9_8:
|
||||
return "V9:8";
|
||||
case HEX_REG_HVX_WR_W5:
|
||||
case HEX_REG_HVX_WR_V11_10:
|
||||
return "V11:10";
|
||||
case HEX_REG_HVX_WR_W6:
|
||||
case HEX_REG_HVX_WR_V13_12:
|
||||
return "V13:12";
|
||||
case HEX_REG_HVX_WR_W7:
|
||||
case HEX_REG_HVX_WR_V15_14:
|
||||
return "V15:14";
|
||||
case HEX_REG_HVX_WR_W8:
|
||||
case HEX_REG_HVX_WR_V17_16:
|
||||
return "V17:16";
|
||||
case HEX_REG_HVX_WR_W9:
|
||||
case HEX_REG_HVX_WR_V19_18:
|
||||
return "V19:18";
|
||||
case HEX_REG_HVX_WR_W10:
|
||||
case HEX_REG_HVX_WR_V21_20:
|
||||
return "V21:20";
|
||||
case HEX_REG_HVX_WR_W11:
|
||||
case HEX_REG_HVX_WR_V23_22:
|
||||
return "V23:22";
|
||||
case HEX_REG_HVX_WR_W12:
|
||||
case HEX_REG_HVX_WR_V25_24:
|
||||
return "V25:24";
|
||||
case HEX_REG_HVX_WR_W13:
|
||||
case HEX_REG_HVX_WR_V27_26:
|
||||
return "V27:26";
|
||||
case HEX_REG_HVX_WR_W14:
|
||||
case HEX_REG_HVX_WR_V29_28:
|
||||
return "V29:28";
|
||||
case HEX_REG_HVX_WR_W15:
|
||||
case HEX_REG_HVX_WR_V31_30:
|
||||
return "V31:30";
|
||||
}
|
||||
}
|
||||
|
||||
char *hex_get_int_regs(int opcode_reg) {
|
||||
char *hex_get_int_regs(int opcode_reg, bool get_alias) {
|
||||
switch (opcode_reg) {
|
||||
default:
|
||||
return "<err>";
|
||||
default: return "<err>";
|
||||
case HEX_REG_INT_REGS_R0:
|
||||
return "R0";
|
||||
case HEX_REG_INT_REGS_R1:
|
||||
|
|
@ -530,18 +518,17 @@ char *hex_get_int_regs(int opcode_reg) {
|
|||
case HEX_REG_INT_REGS_R11:
|
||||
return "R11";
|
||||
case HEX_REG_INT_REGS_R29:
|
||||
return "R29";
|
||||
return get_alias ? "SP" : "R29";
|
||||
case HEX_REG_INT_REGS_R30:
|
||||
return "R30";
|
||||
return get_alias ? "FP" : "R30";
|
||||
case HEX_REG_INT_REGS_R31:
|
||||
return "R31";
|
||||
return get_alias ? "LR" : "R31";
|
||||
}
|
||||
}
|
||||
|
||||
char *hex_get_int_regs_low8(int opcode_reg) {
|
||||
char *hex_get_int_regs_low8(int opcode_reg, bool get_alias) {
|
||||
switch (opcode_reg) {
|
||||
default:
|
||||
return "<err>";
|
||||
default: return "<err>";
|
||||
case HEX_REG_INT_REGS_LOW8_R7:
|
||||
return "R7";
|
||||
case HEX_REG_INT_REGS_LOW8_R6:
|
||||
|
|
@ -561,23 +548,20 @@ char *hex_get_int_regs_low8(int opcode_reg) {
|
|||
}
|
||||
}
|
||||
|
||||
char *hex_get_mod_regs(int opcode_reg) {
|
||||
char *hex_get_mod_regs(int opcode_reg, bool get_alias) {
|
||||
opcode_reg |= 6;
|
||||
|
||||
switch (opcode_reg) {
|
||||
default:
|
||||
return "<err>";
|
||||
case HEX_REG_MOD_REGS_M0:
|
||||
return "M0";
|
||||
case HEX_REG_MOD_REGS_M1:
|
||||
return "M1";
|
||||
default: return "<err>";
|
||||
case HEX_REG_MOD_REGS_C6:
|
||||
return get_alias ? "M0" : "C6";
|
||||
case HEX_REG_MOD_REGS_C7:
|
||||
return get_alias ? "M1" : "C7";
|
||||
}
|
||||
}
|
||||
|
||||
char *hex_get_pred_regs(int opcode_reg) {
|
||||
char *hex_get_pred_regs(int opcode_reg, bool get_alias) {
|
||||
switch (opcode_reg) {
|
||||
default:
|
||||
return "<err>";
|
||||
default: return "<err>";
|
||||
case HEX_REG_PRED_REGS_P0:
|
||||
return "P0";
|
||||
case HEX_REG_PRED_REGS_P1:
|
||||
|
|
@ -589,32 +573,31 @@ char *hex_get_pred_regs(int opcode_reg) {
|
|||
}
|
||||
}
|
||||
|
||||
char *hex_get_sys_regs(int opcode_reg) {
|
||||
char *hex_get_sys_regs(int opcode_reg, bool get_alias) {
|
||||
switch (opcode_reg) {
|
||||
default:
|
||||
return "<err>";
|
||||
case HEX_REG_SYS_REGS_SGP0:
|
||||
return "SGP0";
|
||||
case HEX_REG_SYS_REGS_SGP1:
|
||||
return "SGP1";
|
||||
case HEX_REG_SYS_REGS_STID:
|
||||
return "STID";
|
||||
case HEX_REG_SYS_REGS_ELR:
|
||||
return "ELR";
|
||||
case HEX_REG_SYS_REGS_BADVA0:
|
||||
return "BADVA0";
|
||||
case HEX_REG_SYS_REGS_BADVA1:
|
||||
return "BADVA1";
|
||||
case HEX_REG_SYS_REGS_SSR:
|
||||
return "SSR";
|
||||
case HEX_REG_SYS_REGS_CCR:
|
||||
return "CCR";
|
||||
case HEX_REG_SYS_REGS_HTID:
|
||||
return "HTID";
|
||||
case HEX_REG_SYS_REGS_BADVA:
|
||||
return "BADVA";
|
||||
case HEX_REG_SYS_REGS_IMASK:
|
||||
return "IMASK";
|
||||
default: return "<err>";
|
||||
case HEX_REG_SYS_REGS_S0:
|
||||
return get_alias ? "SGP0" : "S0";
|
||||
case HEX_REG_SYS_REGS_S1:
|
||||
return get_alias ? "SGP1" : "S1";
|
||||
case HEX_REG_SYS_REGS_S2:
|
||||
return get_alias ? "STID" : "S2";
|
||||
case HEX_REG_SYS_REGS_S3:
|
||||
return get_alias ? "ELR" : "S3";
|
||||
case HEX_REG_SYS_REGS_S4:
|
||||
return get_alias ? "BADVA0" : "S4";
|
||||
case HEX_REG_SYS_REGS_S5:
|
||||
return get_alias ? "BADVA1" : "S5";
|
||||
case HEX_REG_SYS_REGS_S6:
|
||||
return get_alias ? "SSR" : "S6";
|
||||
case HEX_REG_SYS_REGS_S7:
|
||||
return get_alias ? "CCR" : "S7";
|
||||
case HEX_REG_SYS_REGS_S8:
|
||||
return get_alias ? "HTID" : "S8";
|
||||
case HEX_REG_SYS_REGS_S9:
|
||||
return get_alias ? "BADVA" : "S9";
|
||||
case HEX_REG_SYS_REGS_S10:
|
||||
return get_alias ? "IMASK" : "S10";
|
||||
case HEX_REG_SYS_REGS_S11:
|
||||
return "S11";
|
||||
case HEX_REG_SYS_REGS_S12:
|
||||
|
|
@ -626,61 +609,61 @@ char *hex_get_sys_regs(int opcode_reg) {
|
|||
case HEX_REG_SYS_REGS_S15:
|
||||
return "S15";
|
||||
case HEX_REG_SYS_REGS_S19:
|
||||
return "S19";
|
||||
return get_alias ? "S19" : "S19";
|
||||
case HEX_REG_SYS_REGS_S23:
|
||||
return "S23";
|
||||
case HEX_REG_SYS_REGS_S25:
|
||||
return "S25";
|
||||
case HEX_REG_SYS_REGS_EVB:
|
||||
return "EVB";
|
||||
case HEX_REG_SYS_REGS_MODECTL:
|
||||
return "MODECTL";
|
||||
case HEX_REG_SYS_REGS_SYSCFG:
|
||||
return "SYSCFG";
|
||||
case HEX_REG_SYS_REGS_S16:
|
||||
return get_alias ? "EVB" : "S16";
|
||||
case HEX_REG_SYS_REGS_S17:
|
||||
return get_alias ? "MODECTL" : "S17";
|
||||
case HEX_REG_SYS_REGS_S18:
|
||||
return get_alias ? "SYSCFG" : "S18";
|
||||
case HEX_REG_SYS_REGS_S20:
|
||||
return "S20";
|
||||
case HEX_REG_SYS_REGS_VID:
|
||||
return "VID";
|
||||
return get_alias ? "S20" : "S20";
|
||||
case HEX_REG_SYS_REGS_S21:
|
||||
return get_alias ? "VID" : "S21";
|
||||
case HEX_REG_SYS_REGS_S22:
|
||||
return "S22";
|
||||
return get_alias ? "S22" : "S22";
|
||||
case HEX_REG_SYS_REGS_S24:
|
||||
return "S24";
|
||||
case HEX_REG_SYS_REGS_S26:
|
||||
return "S26";
|
||||
case HEX_REG_SYS_REGS_CFGBASE:
|
||||
return "CFGBASE";
|
||||
case HEX_REG_SYS_REGS_DIAG:
|
||||
return "DIAG";
|
||||
case HEX_REG_SYS_REGS_REV:
|
||||
return "REV";
|
||||
case HEX_REG_SYS_REGS_PCYCLEHI:
|
||||
return "PCYCLEHI";
|
||||
case HEX_REG_SYS_REGS_PCYCLELO:
|
||||
return "PCYCLELO";
|
||||
case HEX_REG_SYS_REGS_ISDBST:
|
||||
return "ISDBST";
|
||||
case HEX_REG_SYS_REGS_ISDBCFG0:
|
||||
return "ISDBCFG0";
|
||||
case HEX_REG_SYS_REGS_ISDBCFG1:
|
||||
return "ISDBCFG1";
|
||||
case HEX_REG_SYS_REGS_S27:
|
||||
return get_alias ? "CFGBASE" : "S27";
|
||||
case HEX_REG_SYS_REGS_S28:
|
||||
return get_alias ? "DIAG" : "S28";
|
||||
case HEX_REG_SYS_REGS_S29:
|
||||
return get_alias ? "REV" : "S29";
|
||||
case HEX_REG_SYS_REGS_S31:
|
||||
return get_alias ? "PCYCLEHI" : "S31";
|
||||
case HEX_REG_SYS_REGS_S30:
|
||||
return get_alias ? "PCYCLELO" : "S30";
|
||||
case HEX_REG_SYS_REGS_S32:
|
||||
return get_alias ? "ISDBST" : "S32";
|
||||
case HEX_REG_SYS_REGS_S33:
|
||||
return get_alias ? "ISDBCFG0" : "S33";
|
||||
case HEX_REG_SYS_REGS_S34:
|
||||
return get_alias ? "ISDBCFG1" : "S34";
|
||||
case HEX_REG_SYS_REGS_S35:
|
||||
return "S35";
|
||||
case HEX_REG_SYS_REGS_BRKPTPC0:
|
||||
return "BRKPTPC0";
|
||||
case HEX_REG_SYS_REGS_BRKPTCFG0:
|
||||
return "BRKPTCFG0";
|
||||
case HEX_REG_SYS_REGS_BRKPTPC1:
|
||||
return "BRKPTPC1";
|
||||
case HEX_REG_SYS_REGS_BRKPTCFG1:
|
||||
return "BRKPTCFG1";
|
||||
case HEX_REG_SYS_REGS_ISDBMBXIN:
|
||||
return "ISDBMBXIN";
|
||||
case HEX_REG_SYS_REGS_ISDBMBXOUT:
|
||||
return "ISDBMBXOUT";
|
||||
case HEX_REG_SYS_REGS_ISDBEN:
|
||||
return "ISDBEN";
|
||||
case HEX_REG_SYS_REGS_ISDBGPR:
|
||||
return "ISDBGPR";
|
||||
case HEX_REG_SYS_REGS_S36:
|
||||
return get_alias ? "BRKPTPC0" : "S36";
|
||||
case HEX_REG_SYS_REGS_S37:
|
||||
return get_alias ? "BRKPTCFG0" : "S37";
|
||||
case HEX_REG_SYS_REGS_S38:
|
||||
return get_alias ? "BRKPTPC1" : "S38";
|
||||
case HEX_REG_SYS_REGS_S39:
|
||||
return get_alias ? "BRKPTCFG1" : "S39";
|
||||
case HEX_REG_SYS_REGS_S40:
|
||||
return get_alias ? "ISDBMBXIN" : "S40";
|
||||
case HEX_REG_SYS_REGS_S41:
|
||||
return get_alias ? "ISDBMBXOUT" : "S41";
|
||||
case HEX_REG_SYS_REGS_S42:
|
||||
return get_alias ? "ISDBEN" : "S42";
|
||||
case HEX_REG_SYS_REGS_S43:
|
||||
return get_alias ? "ISDBGPR" : "S43";
|
||||
case HEX_REG_SYS_REGS_S44:
|
||||
return "S44";
|
||||
case HEX_REG_SYS_REGS_S45:
|
||||
|
|
@ -689,18 +672,18 @@ char *hex_get_sys_regs(int opcode_reg) {
|
|||
return "S46";
|
||||
case HEX_REG_SYS_REGS_S47:
|
||||
return "S47";
|
||||
case HEX_REG_SYS_REGS_PMUCNT0:
|
||||
return "PMUCNT0";
|
||||
case HEX_REG_SYS_REGS_PMUCNT1:
|
||||
return "PMUCNT1";
|
||||
case HEX_REG_SYS_REGS_PMUCNT2:
|
||||
return "PMUCNT2";
|
||||
case HEX_REG_SYS_REGS_PMUCNT3:
|
||||
return "PMUCNT3";
|
||||
case HEX_REG_SYS_REGS_PMUEVTCFG:
|
||||
return "PMUEVTCFG";
|
||||
case HEX_REG_SYS_REGS_PMUCFG:
|
||||
return "PMUCFG";
|
||||
case HEX_REG_SYS_REGS_S48:
|
||||
return get_alias ? "PMUCNT0" : "S48";
|
||||
case HEX_REG_SYS_REGS_S49:
|
||||
return get_alias ? "PMUCNT1" : "S49";
|
||||
case HEX_REG_SYS_REGS_S50:
|
||||
return get_alias ? "PMUCNT2" : "S50";
|
||||
case HEX_REG_SYS_REGS_S51:
|
||||
return get_alias ? "PMUCNT3" : "S51";
|
||||
case HEX_REG_SYS_REGS_S52:
|
||||
return get_alias ? "PMUEVTCFG" : "S52";
|
||||
case HEX_REG_SYS_REGS_S53:
|
||||
return get_alias ? "PMUCFG" : "S53";
|
||||
case HEX_REG_SYS_REGS_S54:
|
||||
return "S54";
|
||||
case HEX_REG_SYS_REGS_S55:
|
||||
|
|
@ -758,18 +741,17 @@ char *hex_get_sys_regs(int opcode_reg) {
|
|||
}
|
||||
}
|
||||
|
||||
char *hex_get_sys_regs64(int opcode_reg) {
|
||||
char *hex_get_sys_regs64(int opcode_reg, bool get_alias) {
|
||||
switch (opcode_reg) {
|
||||
default:
|
||||
return "<err>";
|
||||
case HEX_REG_SYS_REGS64_SGP1_0:
|
||||
return "S1:0";
|
||||
default: return "<err>";
|
||||
case HEX_REG_SYS_REGS64_S1_0:
|
||||
return get_alias ? "SGP1:0" : "S1:0";
|
||||
case HEX_REG_SYS_REGS64_S3_2:
|
||||
return "S3:2";
|
||||
case HEX_REG_SYS_REGS64_S5_4:
|
||||
return "S5:4";
|
||||
return get_alias ? "BADVA1:0" : "S5:4";
|
||||
case HEX_REG_SYS_REGS64_S7_6:
|
||||
return "S7:6";
|
||||
return get_alias ? "CCR:SSR" : "S7:6";
|
||||
case HEX_REG_SYS_REGS64_S9_8:
|
||||
return "S9:8";
|
||||
case HEX_REG_SYS_REGS64_S11_10:
|
||||
|
|
@ -793,7 +775,7 @@ char *hex_get_sys_regs64(int opcode_reg) {
|
|||
case HEX_REG_SYS_REGS64_S29_28:
|
||||
return "S29:28";
|
||||
case HEX_REG_SYS_REGS64_S31_30:
|
||||
return "S31:30";
|
||||
return get_alias ? "PCYCLE" : "S31:30";
|
||||
case HEX_REG_SYS_REGS64_S33_32:
|
||||
return "S33:32";
|
||||
case HEX_REG_SYS_REGS64_S35_34:
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
|
||||
// LLVM commit: 96e220e6886868d6663d966ecc396befffc355e7
|
||||
// LLVM commit date: 2022-01-05 11:01:52 +0000 (ISO 8601 format)
|
||||
// Date of code generation: 2022-04-02 06:42:08-04:00
|
||||
// Date of code generation: 2022-04-02 10:48:34-04:00
|
||||
//========================================
|
||||
// The following code is generated.
|
||||
// Do not edit. Repository of code generator:
|
||||
|
|
@ -134,28 +134,28 @@ typedef struct {
|
|||
RzConfig *cfg;
|
||||
} HexState;
|
||||
typedef enum {
|
||||
HEX_REG_CTR_REGS_SA0 = 0, // c0
|
||||
HEX_REG_CTR_REGS_LC0 = 1, // c1
|
||||
HEX_REG_CTR_REGS_SA1 = 2, // c2
|
||||
HEX_REG_CTR_REGS_LC1 = 3, // c3
|
||||
HEX_REG_CTR_REGS_P3_0 = 4, // c4
|
||||
HEX_REG_CTR_REGS_C0 = 0, // sa0
|
||||
HEX_REG_CTR_REGS_C1 = 1, // lc0
|
||||
HEX_REG_CTR_REGS_C2 = 2, // sa1
|
||||
HEX_REG_CTR_REGS_C3 = 3, // lc1
|
||||
HEX_REG_CTR_REGS_C4 = 4, // p3:0
|
||||
HEX_REG_CTR_REGS_C5 = 5, // c5
|
||||
HEX_REG_CTR_REGS_M0 = 6, // c6
|
||||
HEX_REG_CTR_REGS_M1 = 7, // c7
|
||||
HEX_REG_CTR_REGS_USR = 8, // c8
|
||||
HEX_REG_CTR_REGS_PC = 9, // c9
|
||||
HEX_REG_CTR_REGS_UGP = 10, // c10
|
||||
HEX_REG_CTR_REGS_GP = 11, // c11
|
||||
HEX_REG_CTR_REGS_CS0 = 12, // c12
|
||||
HEX_REG_CTR_REGS_CS1 = 13, // c13
|
||||
HEX_REG_CTR_REGS_UPCYCLELO = 14, // c14
|
||||
HEX_REG_CTR_REGS_UPCYCLEHI = 15, // c15
|
||||
HEX_REG_CTR_REGS_FRAMELIMIT = 16, // c16
|
||||
HEX_REG_CTR_REGS_FRAMEKEY = 17, // c17
|
||||
HEX_REG_CTR_REGS_PKTCOUNTLO = 18, // c18
|
||||
HEX_REG_CTR_REGS_PKTCOUNTHI = 19, // c19
|
||||
HEX_REG_CTR_REGS_UTIMERLO = 30, // c30
|
||||
HEX_REG_CTR_REGS_UTIMERHI = 31, // c31
|
||||
HEX_REG_CTR_REGS_C6 = 6, // m0
|
||||
HEX_REG_CTR_REGS_C7 = 7, // m1
|
||||
HEX_REG_CTR_REGS_C8 = 8, // usr
|
||||
HEX_REG_CTR_REGS_C9 = 9, // pc
|
||||
HEX_REG_CTR_REGS_C10 = 10, // ugp
|
||||
HEX_REG_CTR_REGS_C11 = 11, // gp
|
||||
HEX_REG_CTR_REGS_C12 = 12, // cs0
|
||||
HEX_REG_CTR_REGS_C13 = 13, // cs1
|
||||
HEX_REG_CTR_REGS_C14 = 14, // upcyclelo
|
||||
HEX_REG_CTR_REGS_C15 = 15, // upcyclehi
|
||||
HEX_REG_CTR_REGS_C16 = 16, // framelimit
|
||||
HEX_REG_CTR_REGS_C17 = 17, // framekey
|
||||
HEX_REG_CTR_REGS_C18 = 18, // pktcountlo
|
||||
HEX_REG_CTR_REGS_C19 = 19, // pktcounthi
|
||||
HEX_REG_CTR_REGS_C30 = 30, // utimerlo
|
||||
HEX_REG_CTR_REGS_C31 = 31, // utimerhi
|
||||
} HEX_CTR_REGS; // CtrRegs
|
||||
|
||||
typedef enum {
|
||||
|
|
@ -165,41 +165,41 @@ typedef enum {
|
|||
HEX_REG_CTR_REGS64_C7_6 = 6, // m1:0
|
||||
HEX_REG_CTR_REGS64_C9_8 = 8,
|
||||
HEX_REG_CTR_REGS64_C11_10 = 10,
|
||||
HEX_REG_CTR_REGS64_CS = 12, // cs1:0
|
||||
HEX_REG_CTR_REGS64_UPCYCLE = 14, // upcycle
|
||||
HEX_REG_CTR_REGS64_C13_12 = 12, // cs1:0
|
||||
HEX_REG_CTR_REGS64_C15_14 = 14, // upcycle
|
||||
HEX_REG_CTR_REGS64_C17_16 = 16,
|
||||
HEX_REG_CTR_REGS64_PKTCOUNT = 18, // pktcount
|
||||
HEX_REG_CTR_REGS64_UTIMER = 30, // utimer
|
||||
HEX_REG_CTR_REGS64_C19_18 = 18, // pktcount
|
||||
HEX_REG_CTR_REGS64_C31_30 = 30, // utimer
|
||||
} HEX_CTR_REGS64; // CtrRegs64
|
||||
|
||||
typedef enum {
|
||||
HEX_REG_DOUBLE_REGS_D0 = 0,
|
||||
HEX_REG_DOUBLE_REGS_D1 = 2,
|
||||
HEX_REG_DOUBLE_REGS_D2 = 4,
|
||||
HEX_REG_DOUBLE_REGS_D3 = 6,
|
||||
HEX_REG_DOUBLE_REGS_D4 = 8,
|
||||
HEX_REG_DOUBLE_REGS_D5 = 10,
|
||||
HEX_REG_DOUBLE_REGS_D6 = 12,
|
||||
HEX_REG_DOUBLE_REGS_D7 = 14,
|
||||
HEX_REG_DOUBLE_REGS_D8 = 16,
|
||||
HEX_REG_DOUBLE_REGS_D9 = 18,
|
||||
HEX_REG_DOUBLE_REGS_D10 = 20,
|
||||
HEX_REG_DOUBLE_REGS_D11 = 22,
|
||||
HEX_REG_DOUBLE_REGS_D12 = 24,
|
||||
HEX_REG_DOUBLE_REGS_D13 = 26,
|
||||
HEX_REG_DOUBLE_REGS_D14 = 28,
|
||||
HEX_REG_DOUBLE_REGS_D15 = 30, // lr:fp
|
||||
HEX_REG_DOUBLE_REGS_R1_0 = 0,
|
||||
HEX_REG_DOUBLE_REGS_R3_2 = 2,
|
||||
HEX_REG_DOUBLE_REGS_R5_4 = 4,
|
||||
HEX_REG_DOUBLE_REGS_R7_6 = 6,
|
||||
HEX_REG_DOUBLE_REGS_R9_8 = 8,
|
||||
HEX_REG_DOUBLE_REGS_R11_10 = 10,
|
||||
HEX_REG_DOUBLE_REGS_R13_12 = 12,
|
||||
HEX_REG_DOUBLE_REGS_R15_14 = 14,
|
||||
HEX_REG_DOUBLE_REGS_R17_16 = 16,
|
||||
HEX_REG_DOUBLE_REGS_R19_18 = 18,
|
||||
HEX_REG_DOUBLE_REGS_R21_20 = 20,
|
||||
HEX_REG_DOUBLE_REGS_R23_22 = 22,
|
||||
HEX_REG_DOUBLE_REGS_R25_24 = 24,
|
||||
HEX_REG_DOUBLE_REGS_R27_26 = 26,
|
||||
HEX_REG_DOUBLE_REGS_R29_28 = 28,
|
||||
HEX_REG_DOUBLE_REGS_R31_30 = 30, // lr:fp
|
||||
} HEX_DOUBLE_REGS; // DoubleRegs
|
||||
|
||||
typedef enum {
|
||||
HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D0 = 0,
|
||||
HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D1 = 2,
|
||||
HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D2 = 4,
|
||||
HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D3 = 6,
|
||||
HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D8 = 16,
|
||||
HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D9 = 18,
|
||||
HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D10 = 20,
|
||||
HEX_REG_GENERAL_DOUBLE_LOW8_REGS_D11 = 22,
|
||||
HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R1_0 = 0,
|
||||
HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R3_2 = 2,
|
||||
HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R5_4 = 4,
|
||||
HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R7_6 = 6,
|
||||
HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R17_16 = 16,
|
||||
HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R19_18 = 18,
|
||||
HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R21_20 = 20,
|
||||
HEX_REG_GENERAL_DOUBLE_LOW8_REGS_R23_22 = 22,
|
||||
} HEX_GENERAL_DOUBLE_LOW8_REGS; // GeneralDoubleLow8Regs
|
||||
|
||||
typedef enum {
|
||||
|
|
@ -222,10 +222,10 @@ typedef enum {
|
|||
} HEX_GENERAL_SUB_REGS; // GeneralSubRegs
|
||||
|
||||
typedef enum {
|
||||
HEX_REG_GUEST_REGS_GELR = 0, // g0
|
||||
HEX_REG_GUEST_REGS_GSR = 1, // g1
|
||||
HEX_REG_GUEST_REGS_GOSP = 2, // g2
|
||||
HEX_REG_GUEST_REGS_G3 = 3, // g3
|
||||
HEX_REG_GUEST_REGS_G0 = 0, // gelr
|
||||
HEX_REG_GUEST_REGS_G1 = 1, // gsr
|
||||
HEX_REG_GUEST_REGS_G2 = 2, // gosp
|
||||
HEX_REG_GUEST_REGS_G3 = 3, // gbadva
|
||||
HEX_REG_GUEST_REGS_G4 = 4,
|
||||
HEX_REG_GUEST_REGS_G5 = 5,
|
||||
HEX_REG_GUEST_REGS_G6 = 6,
|
||||
|
|
@ -238,20 +238,20 @@ typedef enum {
|
|||
HEX_REG_GUEST_REGS_G13 = 13,
|
||||
HEX_REG_GUEST_REGS_G14 = 14,
|
||||
HEX_REG_GUEST_REGS_G15 = 15,
|
||||
HEX_REG_GUEST_REGS_GPMUCNT4 = 16, // g16
|
||||
HEX_REG_GUEST_REGS_GPMUCNT5 = 17, // g17
|
||||
HEX_REG_GUEST_REGS_GPMUCNT6 = 18, // g18
|
||||
HEX_REG_GUEST_REGS_GPMUCNT7 = 19, // g19
|
||||
HEX_REG_GUEST_REGS_G16 = 16, // gpmucnt4
|
||||
HEX_REG_GUEST_REGS_G17 = 17, // gpmucnt5
|
||||
HEX_REG_GUEST_REGS_G18 = 18, // gpmucnt6
|
||||
HEX_REG_GUEST_REGS_G19 = 19, // gpmucnt7
|
||||
HEX_REG_GUEST_REGS_G20 = 20,
|
||||
HEX_REG_GUEST_REGS_G21 = 21,
|
||||
HEX_REG_GUEST_REGS_G22 = 22,
|
||||
HEX_REG_GUEST_REGS_G23 = 23,
|
||||
HEX_REG_GUEST_REGS_GPCYCLELO = 24, // g24
|
||||
HEX_REG_GUEST_REGS_GPCYCLEHI = 25, // g25
|
||||
HEX_REG_GUEST_REGS_GPMUCNT0 = 26, // g26
|
||||
HEX_REG_GUEST_REGS_GPMUCNT1 = 27, // g27
|
||||
HEX_REG_GUEST_REGS_GPMUCNT2 = 28, // g28
|
||||
HEX_REG_GUEST_REGS_GPMUCNT3 = 29, // g29
|
||||
HEX_REG_GUEST_REGS_G24 = 24, // gpcyclelo
|
||||
HEX_REG_GUEST_REGS_G25 = 25, // gpcyclehi
|
||||
HEX_REG_GUEST_REGS_G26 = 26, // gpmucnt0
|
||||
HEX_REG_GUEST_REGS_G27 = 27, // gpmucnt1
|
||||
HEX_REG_GUEST_REGS_G28 = 28, // gpmucnt2
|
||||
HEX_REG_GUEST_REGS_G29 = 29, // gpmucnt3
|
||||
HEX_REG_GUEST_REGS_G30 = 30,
|
||||
HEX_REG_GUEST_REGS_G31 = 31,
|
||||
} HEX_GUEST_REGS; // GuestRegs
|
||||
|
|
@ -283,14 +283,14 @@ typedef enum {
|
|||
} HEX_HVX_QR; // HvxQR
|
||||
|
||||
typedef enum {
|
||||
HEX_REG_HVX_VQR_VQ0 = 0,
|
||||
HEX_REG_HVX_VQR_VQ1 = 4,
|
||||
HEX_REG_HVX_VQR_VQ2 = 8,
|
||||
HEX_REG_HVX_VQR_VQ3 = 12,
|
||||
HEX_REG_HVX_VQR_VQ4 = 16,
|
||||
HEX_REG_HVX_VQR_VQ5 = 20,
|
||||
HEX_REG_HVX_VQR_VQ6 = 24,
|
||||
HEX_REG_HVX_VQR_VQ7 = 28,
|
||||
HEX_REG_HVX_VQR_V3_0 = 0,
|
||||
HEX_REG_HVX_VQR_V7_4 = 4,
|
||||
HEX_REG_HVX_VQR_V11_8 = 8,
|
||||
HEX_REG_HVX_VQR_V15_12 = 12,
|
||||
HEX_REG_HVX_VQR_V19_16 = 16,
|
||||
HEX_REG_HVX_VQR_V23_20 = 20,
|
||||
HEX_REG_HVX_VQR_V27_24 = 24,
|
||||
HEX_REG_HVX_VQR_V31_28 = 28,
|
||||
} HEX_HVX_VQR; // HvxVQR
|
||||
|
||||
typedef enum {
|
||||
|
|
@ -329,22 +329,22 @@ typedef enum {
|
|||
} HEX_HVX_VR; // HvxVR
|
||||
|
||||
typedef enum {
|
||||
HEX_REG_HVX_WR_W0 = 0,
|
||||
HEX_REG_HVX_WR_W1 = 2,
|
||||
HEX_REG_HVX_WR_W2 = 4,
|
||||
HEX_REG_HVX_WR_W3 = 6,
|
||||
HEX_REG_HVX_WR_W4 = 8,
|
||||
HEX_REG_HVX_WR_W5 = 10,
|
||||
HEX_REG_HVX_WR_W6 = 12,
|
||||
HEX_REG_HVX_WR_W7 = 14,
|
||||
HEX_REG_HVX_WR_W8 = 16,
|
||||
HEX_REG_HVX_WR_W9 = 18,
|
||||
HEX_REG_HVX_WR_W10 = 20,
|
||||
HEX_REG_HVX_WR_W11 = 22,
|
||||
HEX_REG_HVX_WR_W12 = 24,
|
||||
HEX_REG_HVX_WR_W13 = 26,
|
||||
HEX_REG_HVX_WR_W14 = 28,
|
||||
HEX_REG_HVX_WR_W15 = 30,
|
||||
HEX_REG_HVX_WR_V1_0 = 0,
|
||||
HEX_REG_HVX_WR_V3_2 = 2,
|
||||
HEX_REG_HVX_WR_V5_4 = 4,
|
||||
HEX_REG_HVX_WR_V7_6 = 6,
|
||||
HEX_REG_HVX_WR_V9_8 = 8,
|
||||
HEX_REG_HVX_WR_V11_10 = 10,
|
||||
HEX_REG_HVX_WR_V13_12 = 12,
|
||||
HEX_REG_HVX_WR_V15_14 = 14,
|
||||
HEX_REG_HVX_WR_V17_16 = 16,
|
||||
HEX_REG_HVX_WR_V19_18 = 18,
|
||||
HEX_REG_HVX_WR_V21_20 = 20,
|
||||
HEX_REG_HVX_WR_V23_22 = 22,
|
||||
HEX_REG_HVX_WR_V25_24 = 24,
|
||||
HEX_REG_HVX_WR_V27_26 = 26,
|
||||
HEX_REG_HVX_WR_V29_28 = 28,
|
||||
HEX_REG_HVX_WR_V31_30 = 30,
|
||||
} HEX_HVX_WR; // HvxWR
|
||||
|
||||
typedef enum {
|
||||
|
|
@ -394,8 +394,8 @@ typedef enum {
|
|||
} HEX_INT_REGS_LOW8; // IntRegsLow8
|
||||
|
||||
typedef enum {
|
||||
HEX_REG_MOD_REGS_M0 = 6, // c6
|
||||
HEX_REG_MOD_REGS_M1 = 7, // c7
|
||||
HEX_REG_MOD_REGS_C6 = 6, // m0
|
||||
HEX_REG_MOD_REGS_C7 = 7, // m1
|
||||
} HEX_MOD_REGS; // ModRegs
|
||||
|
||||
typedef enum {
|
||||
|
|
@ -406,60 +406,60 @@ typedef enum {
|
|||
} HEX_PRED_REGS; // PredRegs
|
||||
|
||||
typedef enum {
|
||||
HEX_REG_SYS_REGS_SGP0 = 0, // s0
|
||||
HEX_REG_SYS_REGS_SGP1 = 1, // s1
|
||||
HEX_REG_SYS_REGS_STID = 2, // s2
|
||||
HEX_REG_SYS_REGS_ELR = 3, // s3
|
||||
HEX_REG_SYS_REGS_BADVA0 = 4, // s4
|
||||
HEX_REG_SYS_REGS_BADVA1 = 5, // s5
|
||||
HEX_REG_SYS_REGS_SSR = 6, // s6
|
||||
HEX_REG_SYS_REGS_CCR = 7, // s7
|
||||
HEX_REG_SYS_REGS_HTID = 8, // s8
|
||||
HEX_REG_SYS_REGS_BADVA = 9, // s9
|
||||
HEX_REG_SYS_REGS_IMASK = 10, // s10
|
||||
HEX_REG_SYS_REGS_S0 = 0, // sgp0
|
||||
HEX_REG_SYS_REGS_S1 = 1, // sgp1
|
||||
HEX_REG_SYS_REGS_S2 = 2, // stid
|
||||
HEX_REG_SYS_REGS_S3 = 3, // elr
|
||||
HEX_REG_SYS_REGS_S4 = 4, // badva0
|
||||
HEX_REG_SYS_REGS_S5 = 5, // badva1
|
||||
HEX_REG_SYS_REGS_S6 = 6, // ssr
|
||||
HEX_REG_SYS_REGS_S7 = 7, // ccr
|
||||
HEX_REG_SYS_REGS_S8 = 8, // htid
|
||||
HEX_REG_SYS_REGS_S9 = 9, // badva
|
||||
HEX_REG_SYS_REGS_S10 = 10, // imask
|
||||
HEX_REG_SYS_REGS_S11 = 11,
|
||||
HEX_REG_SYS_REGS_S12 = 12,
|
||||
HEX_REG_SYS_REGS_S13 = 13,
|
||||
HEX_REG_SYS_REGS_S14 = 14,
|
||||
HEX_REG_SYS_REGS_S15 = 15,
|
||||
HEX_REG_SYS_REGS_EVB = 16, // s16
|
||||
HEX_REG_SYS_REGS_MODECTL = 17, // s17
|
||||
HEX_REG_SYS_REGS_SYSCFG = 18, // s18
|
||||
HEX_REG_SYS_REGS_S16 = 16, // evb
|
||||
HEX_REG_SYS_REGS_S17 = 17, // modectl
|
||||
HEX_REG_SYS_REGS_S18 = 18, // syscfg
|
||||
HEX_REG_SYS_REGS_S19 = 19, // s19
|
||||
HEX_REG_SYS_REGS_S20 = 20, // s20
|
||||
HEX_REG_SYS_REGS_VID = 21, // s21
|
||||
HEX_REG_SYS_REGS_S21 = 21, // vid
|
||||
HEX_REG_SYS_REGS_S22 = 22, // s22
|
||||
HEX_REG_SYS_REGS_S23 = 23,
|
||||
HEX_REG_SYS_REGS_S24 = 24,
|
||||
HEX_REG_SYS_REGS_S25 = 25,
|
||||
HEX_REG_SYS_REGS_S26 = 26,
|
||||
HEX_REG_SYS_REGS_CFGBASE = 27, // s27
|
||||
HEX_REG_SYS_REGS_DIAG = 28, // s28
|
||||
HEX_REG_SYS_REGS_REV = 29, // s29
|
||||
HEX_REG_SYS_REGS_PCYCLELO = 30, // s30
|
||||
HEX_REG_SYS_REGS_PCYCLEHI = 31, // s31
|
||||
HEX_REG_SYS_REGS_ISDBST = 32, // s32
|
||||
HEX_REG_SYS_REGS_ISDBCFG0 = 33, // s33
|
||||
HEX_REG_SYS_REGS_ISDBCFG1 = 34, // s34
|
||||
HEX_REG_SYS_REGS_S27 = 27, // cfgbase
|
||||
HEX_REG_SYS_REGS_S28 = 28, // diag
|
||||
HEX_REG_SYS_REGS_S29 = 29, // rev
|
||||
HEX_REG_SYS_REGS_S30 = 30, // pcyclelo
|
||||
HEX_REG_SYS_REGS_S31 = 31, // pcyclehi
|
||||
HEX_REG_SYS_REGS_S32 = 32, // isdbst
|
||||
HEX_REG_SYS_REGS_S33 = 33, // isdbcfg0
|
||||
HEX_REG_SYS_REGS_S34 = 34, // isdbcfg1
|
||||
HEX_REG_SYS_REGS_S35 = 35,
|
||||
HEX_REG_SYS_REGS_BRKPTPC0 = 36, // s36
|
||||
HEX_REG_SYS_REGS_BRKPTCFG0 = 37, // s37
|
||||
HEX_REG_SYS_REGS_BRKPTPC1 = 38, // s38
|
||||
HEX_REG_SYS_REGS_BRKPTCFG1 = 39, // s39
|
||||
HEX_REG_SYS_REGS_ISDBMBXIN = 40, // s40
|
||||
HEX_REG_SYS_REGS_ISDBMBXOUT = 41, // s41
|
||||
HEX_REG_SYS_REGS_ISDBEN = 42, // s42
|
||||
HEX_REG_SYS_REGS_ISDBGPR = 43, // s43
|
||||
HEX_REG_SYS_REGS_S36 = 36, // brkptpc0
|
||||
HEX_REG_SYS_REGS_S37 = 37, // brkptcfg0
|
||||
HEX_REG_SYS_REGS_S38 = 38, // brkptpc1
|
||||
HEX_REG_SYS_REGS_S39 = 39, // brkptcfg1
|
||||
HEX_REG_SYS_REGS_S40 = 40, // isdbmbxin
|
||||
HEX_REG_SYS_REGS_S41 = 41, // isdbmbxout
|
||||
HEX_REG_SYS_REGS_S42 = 42, // isdben
|
||||
HEX_REG_SYS_REGS_S43 = 43, // isdbgpr
|
||||
HEX_REG_SYS_REGS_S44 = 44,
|
||||
HEX_REG_SYS_REGS_S45 = 45,
|
||||
HEX_REG_SYS_REGS_S46 = 46,
|
||||
HEX_REG_SYS_REGS_S47 = 47,
|
||||
HEX_REG_SYS_REGS_PMUCNT0 = 48, // s48
|
||||
HEX_REG_SYS_REGS_PMUCNT1 = 49, // s49
|
||||
HEX_REG_SYS_REGS_PMUCNT2 = 50, // s50
|
||||
HEX_REG_SYS_REGS_PMUCNT3 = 51, // s51
|
||||
HEX_REG_SYS_REGS_PMUEVTCFG = 52, // s52
|
||||
HEX_REG_SYS_REGS_PMUCFG = 53, // s53
|
||||
HEX_REG_SYS_REGS_S48 = 48, // pmucnt0
|
||||
HEX_REG_SYS_REGS_S49 = 49, // pmucnt1
|
||||
HEX_REG_SYS_REGS_S50 = 50, // pmucnt2
|
||||
HEX_REG_SYS_REGS_S51 = 51, // pmucnt3
|
||||
HEX_REG_SYS_REGS_S52 = 52, // pmuevtcfg
|
||||
HEX_REG_SYS_REGS_S53 = 53, // pmucfg
|
||||
HEX_REG_SYS_REGS_S54 = 54,
|
||||
HEX_REG_SYS_REGS_S55 = 55,
|
||||
HEX_REG_SYS_REGS_S56 = 56,
|
||||
|
|
@ -490,7 +490,7 @@ typedef enum {
|
|||
} HEX_SYS_REGS; // SysRegs
|
||||
|
||||
typedef enum {
|
||||
HEX_REG_SYS_REGS64_SGP1_0 = 0, // sgp1:0
|
||||
HEX_REG_SYS_REGS64_S1_0 = 0, // sgp1:0
|
||||
HEX_REG_SYS_REGS64_S3_2 = 2,
|
||||
HEX_REG_SYS_REGS64_S5_4 = 4, // badva1:0
|
||||
HEX_REG_SYS_REGS64_S7_6 = 6, // ccr:ssr
|
||||
|
|
@ -538,23 +538,23 @@ typedef enum {
|
|||
#define BF_GET(y, start, len) (((y) >> (start)) & BIT_MASK(len))
|
||||
#define BF_GETB(y, start, end) (BF_GET((y), (start), (end) - (start) + 1)
|
||||
|
||||
char *hex_get_ctr_regs(int opcode_reg);
|
||||
char *hex_get_ctr_regs64(int opcode_reg);
|
||||
char *hex_get_double_regs(int opcode_reg);
|
||||
char *hex_get_general_double_low8_regs(int opcode_reg);
|
||||
char *hex_get_general_sub_regs(int opcode_reg);
|
||||
char *hex_get_guest_regs(int opcode_reg);
|
||||
char *hex_get_guest_regs64(int opcode_reg);
|
||||
char *hex_get_hvx_qr(int opcode_reg);
|
||||
char *hex_get_hvx_vqr(int opcode_reg);
|
||||
char *hex_get_hvx_vr(int opcode_reg);
|
||||
char *hex_get_hvx_wr(int opcode_reg);
|
||||
char *hex_get_int_regs(int opcode_reg);
|
||||
char *hex_get_int_regs_low8(int opcode_reg);
|
||||
char *hex_get_mod_regs(int opcode_reg);
|
||||
char *hex_get_pred_regs(int opcode_reg);
|
||||
char *hex_get_sys_regs(int opcode_reg);
|
||||
char *hex_get_sys_regs64(int opcode_reg);
|
||||
char *hex_get_ctr_regs(int opcode_reg, bool get_alias);
|
||||
char *hex_get_ctr_regs64(int opcode_reg, bool get_alias);
|
||||
char *hex_get_double_regs(int opcode_reg, bool get_alias);
|
||||
char *hex_get_general_double_low8_regs(int opcode_reg, bool get_alias);
|
||||
char *hex_get_general_sub_regs(int opcode_reg, bool get_alias);
|
||||
char *hex_get_guest_regs(int opcode_reg, bool get_alias);
|
||||
char *hex_get_guest_regs64(int opcode_reg, bool get_alias);
|
||||
char *hex_get_hvx_qr(int opcode_reg, bool get_alias);
|
||||
char *hex_get_hvx_vqr(int opcode_reg, bool get_alias);
|
||||
char *hex_get_hvx_vr(int opcode_reg, bool get_alias);
|
||||
char *hex_get_hvx_wr(int opcode_reg, bool get_alias);
|
||||
char *hex_get_int_regs(int opcode_reg, bool get_alias);
|
||||
char *hex_get_int_regs_low8(int opcode_reg, bool get_alias);
|
||||
char *hex_get_mod_regs(int opcode_reg, bool get_alias);
|
||||
char *hex_get_pred_regs(int opcode_reg, bool get_alias);
|
||||
char *hex_get_sys_regs(int opcode_reg, bool get_alias);
|
||||
char *hex_get_sys_regs64(int opcode_reg, bool get_alias);
|
||||
|
||||
RZ_API RZ_BORROW RzConfig *hexagon_get_config();
|
||||
RZ_API void hex_extend_op(HexState *state, RZ_INOUT HexOp *op, const bool set_new_extender, const ut32 addr);
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -3,7 +3,7 @@
|
|||
|
||||
// LLVM commit: 96e220e6886868d6663d966ecc396befffc355e7
|
||||
// LLVM commit date: 2022-01-05 11:01:52 +0000 (ISO 8601 format)
|
||||
// Date of code generation: 2022-04-02 05:15:46-04:00
|
||||
// Date of code generation: 2022-04-02 09:49:53-04:00
|
||||
//========================================
|
||||
// The following code is generated.
|
||||
// Do not edit. Repository of code generator:
|
||||
|
|
@ -78,6 +78,7 @@ static bool hexagon_init(void **user) {
|
|||
SETCB("plugins.hexagon.imm.hash", "true", &hex_cfg_set, "Display ## before 32bit immediates and # before immidiates with other width.");
|
||||
SETCB("plugins.hexagon.imm.sign", "true", &hex_cfg_set, "True: Print them with sign. False: Print signed immediates in unsigned representation.");
|
||||
SETCB("plugins.hexagon.sdk", "false", &hex_cfg_set, "Print packet syntax in objdump style.");
|
||||
SETCB("plugins.hexagon.reg.alias", "true", &hex_cfg_set, "Print the alias of registers (Alias from C0 = SA0).");
|
||||
|
||||
return true;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -590,7 +590,7 @@ static bool deserialize_checkpoints_cb(void *user, const char *cnum, const char
|
|||
baby = rz_json_get(child, "arena");
|
||||
CHECK_TYPE(baby, RZ_JSON_INTEGER);
|
||||
int arena = baby->num.s_value;
|
||||
if (arena < RZ_REG_TYPE_GPR || arena > RZ_REG_TYPE_SEG) {
|
||||
if (arena < RZ_REG_TYPE_GPR || arena >= RZ_REG_TYPE_LAST) {
|
||||
continue;
|
||||
}
|
||||
baby = rz_json_get(child, "size");
|
||||
|
|
|
|||
|
|
@ -18,16 +18,19 @@ RZ_LIB_VERSION_HEADER(rz_reg);
|
|||
* this enum aims to cover them all.
|
||||
*/
|
||||
typedef enum {
|
||||
RZ_REG_TYPE_GPR,
|
||||
RZ_REG_TYPE_GPR, //< General purpose
|
||||
RZ_REG_TYPE_DRX,
|
||||
RZ_REG_TYPE_FPU,
|
||||
RZ_REG_TYPE_FPU, //< Floating point
|
||||
RZ_REG_TYPE_MMX,
|
||||
RZ_REG_TYPE_XMM,
|
||||
RZ_REG_TYPE_YMM,
|
||||
RZ_REG_TYPE_FLG,
|
||||
RZ_REG_TYPE_SEG,
|
||||
RZ_REG_TYPE_SYS,
|
||||
RZ_REG_TYPE_SYS, //< System
|
||||
RZ_REG_TYPE_SEC,
|
||||
RZ_REG_TYPE_VC, //< Vector
|
||||
RZ_REG_TYPE_VCC, //< Vector control
|
||||
RZ_REG_TYPE_CTR, //< Control
|
||||
RZ_REG_TYPE_LAST,
|
||||
RZ_REG_TYPE_ANY = -1
|
||||
} RzRegisterType;
|
||||
|
|
|
|||
|
|
@ -7,7 +7,7 @@
|
|||
RZ_LIB_VERSION(rz_reg);
|
||||
|
||||
static const char *types[RZ_REG_TYPE_LAST + 1] = {
|
||||
"gpr", "drx", "fpu", "mmx", "xmm", "ymm", "flg", "seg", "sys", "sec", NULL
|
||||
"gpr", "drx", "fpu", "mmx", "xmm", "ymm", "flg", "seg", "sys", "sec", "vc", "vcc", "ctr", NULL
|
||||
};
|
||||
|
||||
// Take the 32bits name of a register, and return the 64 bit name of it.
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -13,6 +13,9 @@ flg
|
|||
seg
|
||||
sys
|
||||
sec
|
||||
vc
|
||||
vcc
|
||||
ctr
|
||||
EOF
|
||||
RUN
|
||||
|
||||
|
|
|
|||
|
|
@ -3,11 +3,11 @@ d "? immext(##0x40)" 01400000 0x0
|
|||
d "? immext(##0xffffffc0)" ff7fff0f 0x0
|
||||
|
||||
d "? R0 = ##0x101" 20e00078 0x0
|
||||
d "? R5 = add(clb(R31),#-0x1)" 05ff3f8c 0x0
|
||||
d "? R5 = add(clb(LR),#-0x1)" 05ff3f8c 0x0
|
||||
d "? R4 = add(R19,##0x33)" 64c613b0 0x0
|
||||
|
||||
d "? nop" 00c0007f 0x10000000
|
||||
d "? R31 = add(R0,##0x2)" 5f4000b0 0x0
|
||||
d "? LR = add(R0,##0x2)" 5f4000b0 0x0
|
||||
|
||||
d "? P0 = tstbit(R6,#0); if (!P0.new) jump:t 0x14" 04e3c611 0xc
|
||||
d "? P0 = tstbit(R6,#0); if (!P0.new) jump:t 0x8" fce3f611 0x10
|
||||
|
|
@ -19,13 +19,13 @@ d "? R23:22 = combine(#0,#0x2) ; R17:16 = memd(R29+#0x40)" 443e475c 0x0
|
|||
d "? if (!P0.new) R23 = #0 ; jumpr R31" c03f5f5a 0x0
|
||||
|
||||
d "? G9:8 = R9:8" 08c00863 0x0
|
||||
d "? GELR = R31" 00c01f62 0x0
|
||||
d "? GELR = LR" 00c01f62 0x0
|
||||
|
||||
d "? R11:10 = memb_fifo(R12++M0:brev)" 0a408c9e 0x0
|
||||
d "? R15:14 = memb_fifo(R7=##0x3)" 6ed0879a 0x0
|
||||
dB "? C21:20 = R19:18" 14c03263 0x0
|
||||
d "? C17:16 = R19:18" 10c03263 0x0
|
||||
d "? C19:18 = R31:30" 12c03e63 0x0
|
||||
d "? PKTCOUNT = LR:FP" 12c03e63 0x0
|
||||
|
||||
d "? V31.h = vsat(V0.w,V13.w)" 7fc06d1f 0x0
|
||||
|
||||
|
|
@ -38,18 +38,18 @@ d "? R1 = ##0x3 ; R23 = -1" 0f3a3128 0x0
|
|||
d "? R23 = -1 ; R0 = -1" 003a0f3a 0x0
|
||||
d "? R6 = ##0x4 ; R4 = #0x0" 04284628 0x0
|
||||
d "? CSwi(R0)" 20400064 0x0
|
||||
d "? SGP0 = R29" 00401d67 0x0
|
||||
d "? SGP0 = SP" 00401d67 0x0
|
||||
d "? EVB = R0" 10400067 0x0
|
||||
d "? S60 = R0" 3c400067 0x0
|
||||
d "? R31 = S80" 1f40d06e 0x0
|
||||
d "? LR = S80" 1f40d06e 0x0
|
||||
d "? S35 = R0" 23400067 0x0
|
||||
d "? ISDBEN = R2" 2a400267 0x0
|
||||
d "? S61:60 = R1:0" 3c40006d 0x0
|
||||
d "? S79:78 = R1:0" 4e40006d 0x0
|
||||
d "? S1:0 = R1:0" 004c006d 0x0
|
||||
d "? R1:0 = S1:0" 0040006f 0x0
|
||||
d "? SGP1:0 = R1:0" 004c006d 0x0
|
||||
d "? R1:0 = SGP1:0" 0040006f 0x0
|
||||
d "? R1:0 = S79:78" 00404e6f 0x0
|
||||
|
||||
d "? R1:0 = combine(##0x1b,#0x3)" 6063017c 0x0
|
||||
d "? if (!P0) R5:4 = memd(R0+R2<<#0x0)" 04c2c031 0x0
|
||||
d "? if (!P0.new) R2 = add(R2,##0x8)" 02618274 0x0
|
||||
d "? if (!P0.new) R2 = add(R2,##0x8)" 02618274 0x0
|
||||
|
|
@ -334,6 +334,9 @@ flg
|
|||
seg
|
||||
sys
|
||||
sec
|
||||
vc
|
||||
vcc
|
||||
ctr
|
||||
EOF
|
||||
RUN
|
||||
|
||||
|
|
|
|||
|
|
@ -45,8 +45,8 @@ ara+
|
|||
ara~?
|
||||
EOF
|
||||
EXPECT=<<EOF
|
||||
20
|
||||
30
|
||||
26
|
||||
39
|
||||
EOF
|
||||
RUN
|
||||
|
||||
|
|
@ -66,11 +66,11 @@ ara-
|
|||
ara~?
|
||||
EOF
|
||||
EXPECT=<<EOF
|
||||
20
|
||||
30
|
||||
20
|
||||
10
|
||||
10
|
||||
26
|
||||
39
|
||||
26
|
||||
13
|
||||
13
|
||||
EOF
|
||||
RUN
|
||||
|
||||
|
|
|
|||
|
|
@ -30,7 +30,10 @@ Sdb *ref_db() {
|
|||
"{\"arena\":6,\"bytes\":\"BgYGBgYGBgYGBgYGBgYGBg==\",\"size\":16},"
|
||||
"{\"arena\":7,\"bytes\":\"BwcHBwcHBwcHBwcHBwcHBw==\",\"size\":16},"
|
||||
"{\"arena\":8,\"bytes\":\"CAgICAgICAgICAgICAgICA==\",\"size\":16},"
|
||||
"{\"arena\":9,\"bytes\":\"CQkJCQkJCQkJCQkJCQkJCQ==\",\"size\":16}"
|
||||
"{\"arena\":9,\"bytes\":\"CQkJCQkJCQkJCQkJCQkJCQ==\",\"size\":16},"
|
||||
"{\"arena\":10,\"bytes\":\"CgoKCgoKCgoKCgoKCgoKCg==\",\"size\":16},"
|
||||
"{\"arena\":11,\"bytes\":\"CwsLCwsLCwsLCwsLCwsLCw==\",\"size\":16},"
|
||||
"{\"arena\":12,\"bytes\":\"DAwMDAwMDAwMDAwMDAwMDA==\",\"size\":16}"
|
||||
"],"
|
||||
"\"snaps\":["
|
||||
"{\"name\":\"[stack]\",\"addr\":8796092882944,\"addr_end\":8796092883200,\"size\":256,\"data\":\"8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8PDw8A==\",\"perm\":7,\"user\":0,\"shared\":true}"
|
||||
|
|
|
|||
Loading…
Reference in a new issue