diff --git a/librz/analysis/p/analysis_tms320.c b/librz/analysis/p/analysis_tms320.c
index cafd19022a..0c39fd47c9 100644
--- a/librz/analysis/p/analysis_tms320.c
+++ b/librz/analysis/p/analysis_tms320.c
@@ -112,6 +112,248 @@ static bool tms320_fini(void *user) {
 	return true;
 }
 
+static bool is_c5000(const char *cpu) {
+	if (!cpu) {
+		return false;
+	}
+	return (rz_str_casecmp(cpu, "c55x+") == 0) || (rz_str_casecmp(cpu, "c55x") == 0);
+}
+
+static char *get_reg_profile(RZ_BORROW RzAnalysis *a) {
+	const char *p;
+	if (is_c5000(a->cpu)) {
+		p =
+			"=PC	pc\n"
+			"=A0	ar0\n"
+			"=A1	ar1\n"
+			"=A2	ar2\n"
+			"=A3	ar3\n"
+			"=A4	ar4\n"
+			"=R0	ar0\n"
+			"ctr ac0    .40 496 0 # Accumulator 0\n"
+			"ctr ac1    .40 498 0 # Accumulator 1\n"
+			"ctr ac2    .40 500 0 # Accumulator 2\n"
+			"ctr ac3    .40 502 0 # Accumulator 3\n"
+			"gpr ar0    .16 504 0 # Auxiliary registers 0\n"
+			"gpr ar1    .16 505 0 # Auxiliary registers 1\n"
+			"gpr ar2    .16 506 0 # Auxiliary registers 2\n"
+			"gpr ar3    .16 507 0 # Auxiliary registers 3\n"
+			"gpr ar4    .16 508 0 # Auxiliary registers 4\n"
+			"gpr ar5    .16 509 0 # Auxiliary registers 5\n"
+			"gpr ar6    .16 510 0 # Auxiliary registers 6\n"
+			"gpr ar7    .16 511 0 # Auxiliary registers 7\n"
+			"gpr xar0   .23 512 0 # Extended auxiliary registers 0\n"
+			"gpr xar1   .23 513 0 # Extended auxiliary registers 1\n"
+			"gpr xar2   .23 514 0 # Extended auxiliary registers 2\n"
+			"gpr xar3   .23 515 0 # Extended auxiliary registers 3\n"
+			"gpr xar4   .23 516 0 # Extended auxiliary registers 4\n"
+			"gpr xar5   .23 517 0 # Extended auxiliary registers 5\n"
+			"gpr xar6   .23 518 0 # Extended auxiliary registers 6\n"
+			"gpr xar7   .23 519 0 # Extended auxiliary registers 7\n"
+			"ctr bk03   .16 520 0 # Circular buffer size registers\n"
+			"ctr bk47   .16 521 0 # Circular buffer size registers\n"
+			"ctr bkc    .16 522 0 # Circular buffer size registers\n"
+			"ctr brc0   .16 523 0 # Block-repeat counters 0\n"
+			"ctr brc1   .16 524 0 # Block-repeat counters 1\n"
+			"ctr brs1   .16 525 0 # BRC1 save register\n"
+			"ctr bsa01  .16 526 0 # Circular buffer start address registers\n"
+			"ctr bsa23  .16 527 0 # Circular buffer start address registers\n"
+			"ctr bsa45  .16 528 0 # Circular buffer start address registers\n"
+			"ctr bsa67  .16 529 0 # Circular buffer start address registers\n"
+			"ctr bsac   .16 530 0 # Circular buffer start address registers\n"
+			"ctr cdp    .16 531 0 # Coefficient data pointer (low part of XCDP)\n"
+			"ctr cdph   .7  532 0 # High part of XCDP\n"
+			"ctr cfct   .8  533 0 # Control-flow context register\n"
+			"ctr csr    .16 534 0 # Computed single-repeat register\n"
+			"ctr dbier0 .16 535 0 # Debug interrupt enable registers 0\n"
+			"ctr dbier1 .16 536 0 # Debug interrupt enable registers 1\n"
+			"ctr dp     .16 537 0 # Data page register (low part of XDP)\n"
+			"ctr dph    .7  538 0 # High part of XDP\n"
+			"ctr ier0   .16 539 0 # Interrupt enable registers 0\n"
+			"ctr ier1   .16 540 0 # Interrupt enable registers 1\n"
+			"ctr ifr0   .16 541 0 # Interrupt flag registers 0\n"
+			"ctr ifr1   .16 542 0 # Interrupt flag registers 1\n"
+			"ctr ivpd   .16 543 0 # Interrupt vector pointers\n"
+			"ctr ivph   .16 544 0 # Interrupt vector pointers\n"
+			"ctr pc     .24 545 0 # Program counter\n"
+			"ctr pdp    .9  546 0 # Peripheral data page register\n"
+			"ctr rea0   .24 547 0 # Block-repeat end address registers 0\n"
+			"ctr rea1   .24 548 0 # Block-repeat end address registers 1\n"
+			"ctr reta   .24 549 0 # Return address register\n"
+			"ctr rptc   .16 550 0 # Single-repeat counter\n"
+			"ctr rsa0   .24 551 0 # Block-repeat start address registers 0\n"
+			"ctr rsa1   .24 552 0 # Block-repeat start address registers 1\n"
+			"ctr sp     .16 553 0 # Data stack pointer (low part of XSP)\n"
+			"ctr sph    .7  554 0 # High part of XSP and XSSP\n"
+			"ctr ssp    .16 555 0 # System stack pointer (low part of XSSP)\n"
+			"ctr st0_55 .16 556 0 # Status registers 0\n"
+			"ctr st1_55 .16 557 0 # Status registers 1\n"
+			"ctr st2_55 .16 558 0 # Status registers 2\n"
+			"ctr st3_55 .16 559 0 # Status registers 3\n"
+			"ctr t0     .16 560 0 # Temporary register 0\n"
+			"ctr t1     .16 561 0 # Temporary register 1\n"
+			"ctr t2     .16 562 0 # Temporary register 2\n"
+			"ctr t3     .16 563 0 # Temporary register 3\n"
+			"ctr trn0   .16 564 0 # Transition registers 1\n"
+			"ctr trn1   .16 565 0 # Transition registers 1\n"
+			"ctr xcdp   .23 566 0 # Extended coefficient data pointer\n"
+			"ctr xdp    .23 567 0 # Extended data page register\n"
+			"ctr xsp    .23 568 0 # Extended data stack pointer\n"
+			"ctr xssp   .23 569 0 # Extended system stack pointer\n";
+	} else {
+		p =
+			"=PC	pc\n"
+			"=A0	a4\n"
+			"=A1	b4\n"
+			"=A2	a6\n"
+			"=A3	a6\n"
+			"=A4	a8\n"
+			"=A5	b8\n"
+			"=A6	a10\n"
+			"=A7	b10\n"
+			"=A8	a12\n"
+			"=A9	b12\n"
+			"=R0	a4\n"
+			"gpr	a0	.32	0 		0\n"
+			"gpr	a1	.32	4 		0\n"
+			"gpr	a2	.32	8 		0\n"
+			"gpr	a3	.32	12 		0\n"
+			"gpr	a4	.32	16 		0\n"
+			"gpr	a5	.32	20 		0\n"
+			"gpr	a6	.32	24 		0\n"
+			"gpr	a7	.32	28 		0\n"
+			"gpr	a8	.32	32 		0\n"
+			"gpr	a9	.32	36 		0\n"
+			"gpr	a10	.32	40 		0\n"
+			"gpr	a11	.32	44 		0\n"
+			"gpr	a12	.32	48 		0\n"
+			"gpr	a13	.32	52 		0\n"
+			"gpr	a14	.32	56 		0\n"
+			"gpr	a15	.32	60 		0\n"
+#ifdef CAPSTONE_TMS320C64X_H
+			"gpr	a16	.32	64 		0\n"
+			"gpr	a17	.32	68 		0\n"
+			"gpr	a18	.32	72 		0\n"
+			"gpr	a19	.32	76 		0\n"
+			"gpr	a20	.32	80 		0\n"
+			"gpr	a21	.32	84 		0\n"
+			"gpr	a22	.32	88 		0\n"
+			"gpr	a23	.32	92 		0\n"
+			"gpr	a24	.32	96 		0\n"
+			"gpr	a25	.32	100 	0\n"
+			"gpr	a26	.32	104 	0\n"
+			"gpr	a27	.32	108 	0\n"
+			"gpr	a28	.32	112 	0\n"
+			"gpr	a29	.32	116 	0\n"
+			"gpr	a30	.32	120 	0\n"
+			"gpr	a31	.32	124 	0\n"
+#endif
+			"gpr	b0	.32	128 	0\n"
+			"gpr	b1	.32	132 	0\n"
+			"gpr	b2	.32	136 	0\n"
+			"gpr	b3	.32	140 	0\n"
+			"gpr	b4	.32	144 	0\n"
+			"gpr	b5	.32	148 	0\n"
+			"gpr	b6	.32	152 	0\n"
+			"gpr	b7	.32	156 	0\n"
+			"gpr	b8	.32	160 	0\n"
+			"gpr	b9	.32	164 	0\n"
+			"gpr	b10	.32	168 	0\n"
+			"gpr	b11	.32	172 	0\n"
+			"gpr	b12	.32	176 	0\n"
+			"gpr	b13	.32	180 	0\n"
+			"gpr	b14	.32	184 	0\n"
+			"gpr	b15	.32	188 	0\n"
+#ifdef CAPSTONE_TMS320C64X_H
+			"gpr	b16	.32	192 	0\n"
+			"gpr	b17	.32	196 	0\n"
+			"gpr	b18	.32	200 	0\n"
+			"gpr	b19	.32	204 	0\n"
+			"gpr	b20	.32	208 	0\n"
+			"gpr	b21	.32	212 	0\n"
+			"gpr	b22	.32	216 	0\n"
+			"gpr	b23	.32	220 	0\n"
+			"gpr	b24	.32	224 	0\n"
+			"gpr	b25	.32	228 	0\n"
+			"gpr	b26	.32	232 	0\n"
+			"gpr	b27	.32	236 	0\n"
+			"gpr	b28	.32	240 	0\n"
+			"gpr	b29	.32	244 	0\n"
+			"gpr	b30	.32	248 	0\n"
+			"gpr	b31	.32	252 	0\n"
+#endif
+			"ctr amr     .32 256 0  # Addressing mode register\n"
+			"ctr csr     .32 260 0  # Control status register\n"
+			"ctr gfpgfr  .32 264 0  # Galois field multiply control register\n"
+			"ctr icr     .32 268 0  # Interrupt clear register\n"
+			"ctr ier     .32 272 0  # Interrupt enable register\n"
+			"ctr ifr     .32 276 0  # Interrupt flag register\n"
+			"ctr irp     .32 280 0  # Interrupt return pointer register\n"
+			"ctr isr     .32 284 0  # Interrupt set register\n"
+			"ctr istp    .32 288 0  # Interrupt service table pointer register\n"
+			"ctr nrp     .32 292 0  # Nonmaskable interrupt return pointer register\n"
+			"ctr pce1    .32 296 0  # Program counter, E1 phase\n"
+#ifdef CAPSTONE_TMS320C64X_H
+			// Control Register File Extensions (C64x+ DSP)
+			"ctr dier    .32 300 0  # (C64x+ only) Debug interrupt enable register\n"
+			"ctr dnum    .32 304 0  # (C64x+ only) DSP core number register\n"
+			"ctr ecr     .32 308 0  # (C64x+ only) Exception clear register\n"
+			"ctr efr     .32 312 0  # (C64x+ only) Exception flag register\n"
+			"ctr gplya   .32 316 0  # (C64x+ only) GMPY A-side polynomial register\n"
+			"ctr gplyb   .32 320 0  # (C64x+ only) GMPY B-side polynomial register\n"
+			"ctr ierr    .32 324 0  # (C64x+ only) Internal exception report register\n"
+			"ctr ilc     .32 328 0  # (C64x+ only) Inner loop count register\n"
+			"ctr itsr    .32 332 0  # (C64x+ only) Interrupt task state register\n"
+			"ctr ntsr    .32 336 0  # (C64x+ only) NMI/Exception task state register\n"
+			"ctr rep     .32 340 0  # (C64x+ only) Restricted entry point address register\n"
+			"ctr rilc    .32 344 0  # (C64x+ only) Reload inner loop count register\n"
+			"ctr ssr     .32 348 0  # (C64x+ only) Saturation status register\n"
+			"ctr tsch    .32 352 0  # (C64x+ only) Time-stamp counter (high 32) register\n"
+			"ctr tscl    .32 356 0  # (C64x+ only) Time-stamp counter (low 32) register\n"
+			"ctr tsr     .32 360 0  # (C64x+ only) Task state register\n"
+#endif
+			"gpr	a0:a1 	.64	364	0\n"
+			"gpr	a2:a3 	.64	368	0\n"
+			"gpr	a4:a5 	.64	372	0\n"
+			"gpr	a6:a7 	.64	376	0\n"
+			"gpr	a8:a9 	.64	380	0\n"
+			"gpr	a10:a11	.64	384	0\n"
+			"gpr	a12:a13	.64	388	0\n"
+			"gpr	a14:a15	.64	392	0\n"
+#ifdef CAPSTONE_TMS320C64X_H
+			"gpr	a16:a17	.64	396	0\n"
+			"gpr	a18:a19	.64	400	0\n"
+			"gpr	a20:a21	.64	404	0\n"
+			"gpr	a22:a23	.64	408	0\n"
+			"gpr	a24:a25	.64	412	0\n"
+			"gpr	a26:a27	.64	416	0\n"
+			"gpr	a28:a29	.64	420	0\n"
+			"gpr	a30:a31	.64	424	0\n"
+#endif
+			"gpr	b0:b1 	.64	428	0\n"
+			"gpr	b2:b3 	.64	432	0\n"
+			"gpr	b4:b5 	.64	436	0\n"
+			"gpr	b6:b7 	.64	440	0\n"
+			"gpr	b8:b9 	.64	444	0\n"
+			"gpr	b10:b11	.64	448	0\n"
+			"gpr	b12:b13	.64	452	0\n"
+			"gpr	b14:b15	.64	456	0\n"
+#ifdef CAPSTONE_TMS320C64X_H
+			"gpr	b16:b17	.64	460	0\n"
+			"gpr	b18:b19	.64	464	0\n"
+			"gpr	b20:b21	.64	468	0\n"
+			"gpr	b22:b23	.64	472	0\n"
+			"gpr	b24:b25	.64	476	0\n"
+			"gpr	b26:b27	.64	480	0\n"
+			"gpr	b28:b29	.64	484	0\n"
+			"gpr	b30:b31	.64	488	0\n"
+#endif
+			;
+	}
+
+	return strdup(p);
+}
+
 RzAnalysisPlugin rz_analysis_plugin_tms320 = {
 	.name = "tms320",
 	.arch = "tms320",
@@ -121,6 +363,7 @@ RzAnalysisPlugin rz_analysis_plugin_tms320 = {
 	.fini = tms320_fini,
 	.license = "LGPLv3",
 	.op = &tms320_op,
+	.get_reg_profile = get_reg_profile,
 };
 
 #ifndef RZ_PLUGIN_INCORE
diff --git a/librz/analysis/p/analysis_tms320c64x.c b/librz/analysis/p/analysis_tms320c64x.c
index cb43ddb386..07053d2a79 100644
--- a/librz/analysis/p/analysis_tms320c64x.c
+++ b/librz/analysis/p/analysis_tms320c64x.c
@@ -186,38 +186,3 @@ static int tms320c64x_analop(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const u
 	return op->size;
 }
 #endif
-
-/*
-
-static int archinfo(RzAnalysis *analysis, int q) {
-	return 4; // :D
-}
-
-RzAnalysisPlugin rz_analysis_plugin_tms320c64x = {
-	.name = "tms320c64x",
-	.desc = "Capstone TMS320C64X analysis",
-	.license = "BSD",
-	.arch = "tms320c64x",
-	.bits = 32,
-	.archinfo = archinfo,
-	.op = &analop
-};
-
-#else
-RzAnalysisPlugin rz_analysis_plugin_tms320c64x = {
-	.name = "tms320c64x",
-	.desc = "Capstone TMS320C64X analysis (unsupported)",
-	.license = "BSD",
-	.arch = "tms320c64x",
-	.bits = 32
-};
-#endif
-
-#ifndef RZ_PLUGIN_INCORE
-RZ_API RzLibStruct rizin_plugin = {
-	.type = RZ_LIB_TYPE_ANALYSIS,
-	.data = &rz_analysis_plugin_tms320c64x,
-	.version = RZ_VERSION
-};
-#endif
-*/
diff --git a/test/db/analysis/tms320 b/test/db/analysis/tms320
new file mode 100644
index 0000000000..eed0ad5d64
--- /dev/null
+++ b/test/db/analysis/tms320
@@ -0,0 +1,107 @@
+
+NAME=arp TMS320 c55x
+FILE==
+CMDS=<<EOF
+e asm.arch=tms320
+e analysis.arch=tms320
+e analysis.cpu=c55x
+arp
+ar
+EOF
+EXPECT=<<EOF
+=PC	pc
+=A0	ar0
+=A1	ar1
+=A2	ar2
+=A3	ar3
+=A4	ar4
+=R0	ar0
+ctr ac0    .40 496 0 # Accumulator 0
+ctr ac1    .40 498 0 # Accumulator 1
+ctr ac2    .40 500 0 # Accumulator 2
+ctr ac3    .40 502 0 # Accumulator 3
+gpr ar0    .16 504 0 # Auxiliary registers 0
+gpr ar1    .16 505 0 # Auxiliary registers 1
+gpr ar2    .16 506 0 # Auxiliary registers 2
+gpr ar3    .16 507 0 # Auxiliary registers 3
+gpr ar4    .16 508 0 # Auxiliary registers 4
+gpr ar5    .16 509 0 # Auxiliary registers 5
+gpr ar6    .16 510 0 # Auxiliary registers 6
+gpr ar7    .16 511 0 # Auxiliary registers 7
+gpr xar0   .23 512 0 # Extended auxiliary registers 0
+gpr xar1   .23 513 0 # Extended auxiliary registers 1
+gpr xar2   .23 514 0 # Extended auxiliary registers 2
+gpr xar3   .23 515 0 # Extended auxiliary registers 3
+gpr xar4   .23 516 0 # Extended auxiliary registers 4
+gpr xar5   .23 517 0 # Extended auxiliary registers 5
+gpr xar6   .23 518 0 # Extended auxiliary registers 6
+gpr xar7   .23 519 0 # Extended auxiliary registers 7
+ctr bk03   .16 520 0 # Circular buffer size registers
+ctr bk47   .16 521 0 # Circular buffer size registers
+ctr bkc    .16 522 0 # Circular buffer size registers
+ctr brc0   .16 523 0 # Block-repeat counters 0
+ctr brc1   .16 524 0 # Block-repeat counters 1
+ctr brs1   .16 525 0 # BRC1 save register
+ctr bsa01  .16 526 0 # Circular buffer start address registers
+ctr bsa23  .16 527 0 # Circular buffer start address registers
+ctr bsa45  .16 528 0 # Circular buffer start address registers
+ctr bsa67  .16 529 0 # Circular buffer start address registers
+ctr bsac   .16 530 0 # Circular buffer start address registers
+ctr cdp    .16 531 0 # Coefficient data pointer (low part of XCDP)
+ctr cdph   .7  532 0 # High part of XCDP
+ctr cfct   .8  533 0 # Control-flow context register
+ctr csr    .16 534 0 # Computed single-repeat register
+ctr dbier0 .16 535 0 # Debug interrupt enable registers 0
+ctr dbier1 .16 536 0 # Debug interrupt enable registers 1
+ctr dp     .16 537 0 # Data page register (low part of XDP)
+ctr dph    .7  538 0 # High part of XDP
+ctr ier0   .16 539 0 # Interrupt enable registers 0
+ctr ier1   .16 540 0 # Interrupt enable registers 1
+ctr ifr0   .16 541 0 # Interrupt flag registers 0
+ctr ifr1   .16 542 0 # Interrupt flag registers 1
+ctr ivpd   .16 543 0 # Interrupt vector pointers
+ctr ivph   .16 544 0 # Interrupt vector pointers
+ctr pc     .24 545 0 # Program counter
+ctr pdp    .9  546 0 # Peripheral data page register
+ctr rea0   .24 547 0 # Block-repeat end address registers 0
+ctr rea1   .24 548 0 # Block-repeat end address registers 1
+ctr reta   .24 549 0 # Return address register
+ctr rptc   .16 550 0 # Single-repeat counter
+ctr rsa0   .24 551 0 # Block-repeat start address registers 0
+ctr rsa1   .24 552 0 # Block-repeat start address registers 1
+ctr sp     .16 553 0 # Data stack pointer (low part of XSP)
+ctr sph    .7  554 0 # High part of XSP and XSSP
+ctr ssp    .16 555 0 # System stack pointer (low part of XSSP)
+ctr st0_55 .16 556 0 # Status registers 0
+ctr st1_55 .16 557 0 # Status registers 1
+ctr st2_55 .16 558 0 # Status registers 2
+ctr st3_55 .16 559 0 # Status registers 3
+ctr t0     .16 560 0 # Temporary register 0
+ctr t1     .16 561 0 # Temporary register 1
+ctr t2     .16 562 0 # Temporary register 2
+ctr t3     .16 563 0 # Temporary register 3
+ctr trn0   .16 564 0 # Transition registers 1
+ctr trn1   .16 565 0 # Transition registers 1
+ctr xcdp   .23 566 0 # Extended coefficient data pointer
+ctr xdp    .23 567 0 # Extended data page register
+ctr xsp    .23 568 0 # Extended data stack pointer
+ctr xssp   .23 569 0 # Extended system stack pointer
+
+ar0 = 0x00000000
+ar1 = 0x00000000
+ar2 = 0x00000000
+ar3 = 0x00000000
+ar4 = 0x00000000
+ar5 = 0x00000000
+ar6 = 0x00000000
+ar7 = 0x00000000
+xar0 = 0x00000000
+xar1 = 0x00000000
+xar2 = 0x00000000
+xar3 = 0x00000000
+xar4 = 0x00000000
+xar5 = 0x00000000
+xar6 = 0x00000000
+xar7 = 0x00000000
+EOF
+RUN
diff --git a/test/db/analysis/tms320.c64x_32 b/test/db/analysis/tms320.c64x_32
index 1b742b12aa..fd98407f01 100644
--- a/test/db/analysis/tms320.c64x_32
+++ b/test/db/analysis/tms320.c64x_32
@@ -203,3 +203,150 @@ b30 = b30 * b17
 a16 = 2 .bitset a2 .. 2
 EOF
 RUN
+
+NAME=arp TMS320
+FILE==
+CMDS=<<EOF
+e asm.arch=tms320c64x
+e analysis.arch=tms320
+arp
+EOF
+EXPECT=<<EOF
+=PC	pc
+=A0	a4
+=A1	b4
+=A2	a6
+=A3	a6
+=A4	a8
+=A5	b8
+=A6	a10
+=A7	b10
+=A8	a12
+=A9	b12
+=R0	a4
+gpr	a0	.32	0 		0
+gpr	a1	.32	4 		0
+gpr	a2	.32	8 		0
+gpr	a3	.32	12 		0
+gpr	a4	.32	16 		0
+gpr	a5	.32	20 		0
+gpr	a6	.32	24 		0
+gpr	a7	.32	28 		0
+gpr	a8	.32	32 		0
+gpr	a9	.32	36 		0
+gpr	a10	.32	40 		0
+gpr	a11	.32	44 		0
+gpr	a12	.32	48 		0
+gpr	a13	.32	52 		0
+gpr	a14	.32	56 		0
+gpr	a15	.32	60 		0
+gpr	a16	.32	64 		0
+gpr	a17	.32	68 		0
+gpr	a18	.32	72 		0
+gpr	a19	.32	76 		0
+gpr	a20	.32	80 		0
+gpr	a21	.32	84 		0
+gpr	a22	.32	88 		0
+gpr	a23	.32	92 		0
+gpr	a24	.32	96 		0
+gpr	a25	.32	100 	0
+gpr	a26	.32	104 	0
+gpr	a27	.32	108 	0
+gpr	a28	.32	112 	0
+gpr	a29	.32	116 	0
+gpr	a30	.32	120 	0
+gpr	a31	.32	124 	0
+gpr	b0	.32	128 	0
+gpr	b1	.32	132 	0
+gpr	b2	.32	136 	0
+gpr	b3	.32	140 	0
+gpr	b4	.32	144 	0
+gpr	b5	.32	148 	0
+gpr	b6	.32	152 	0
+gpr	b7	.32	156 	0
+gpr	b8	.32	160 	0
+gpr	b9	.32	164 	0
+gpr	b10	.32	168 	0
+gpr	b11	.32	172 	0
+gpr	b12	.32	176 	0
+gpr	b13	.32	180 	0
+gpr	b14	.32	184 	0
+gpr	b15	.32	188 	0
+gpr	b16	.32	192 	0
+gpr	b17	.32	196 	0
+gpr	b18	.32	200 	0
+gpr	b19	.32	204 	0
+gpr	b20	.32	208 	0
+gpr	b21	.32	212 	0
+gpr	b22	.32	216 	0
+gpr	b23	.32	220 	0
+gpr	b24	.32	224 	0
+gpr	b25	.32	228 	0
+gpr	b26	.32	232 	0
+gpr	b27	.32	236 	0
+gpr	b28	.32	240 	0
+gpr	b29	.32	244 	0
+gpr	b30	.32	248 	0
+gpr	b31	.32	252 	0
+ctr amr     .32 256 0  # Addressing mode register
+ctr csr     .32 260 0  # Control status register
+ctr gfpgfr  .32 264 0  # Galois field multiply control register
+ctr icr     .32 268 0  # Interrupt clear register
+ctr ier     .32 272 0  # Interrupt enable register
+ctr ifr     .32 276 0  # Interrupt flag register
+ctr irp     .32 280 0  # Interrupt return pointer register
+ctr isr     .32 284 0  # Interrupt set register
+ctr istp    .32 288 0  # Interrupt service table pointer register
+ctr nrp     .32 292 0  # Nonmaskable interrupt return pointer register
+ctr pce1    .32 296 0  # Program counter, E1 phase
+ctr dier    .32 300 0  # (C64x+ only) Debug interrupt enable register
+ctr dnum    .32 304 0  # (C64x+ only) DSP core number register
+ctr ecr     .32 308 0  # (C64x+ only) Exception clear register
+ctr efr     .32 312 0  # (C64x+ only) Exception flag register
+ctr gplya   .32 316 0  # (C64x+ only) GMPY A-side polynomial register
+ctr gplyb   .32 320 0  # (C64x+ only) GMPY B-side polynomial register
+ctr ierr    .32 324 0  # (C64x+ only) Internal exception report register
+ctr ilc     .32 328 0  # (C64x+ only) Inner loop count register
+ctr itsr    .32 332 0  # (C64x+ only) Interrupt task state register
+ctr ntsr    .32 336 0  # (C64x+ only) NMI/Exception task state register
+ctr rep     .32 340 0  # (C64x+ only) Restricted entry point address register
+ctr rilc    .32 344 0  # (C64x+ only) Reload inner loop count register
+ctr ssr     .32 348 0  # (C64x+ only) Saturation status register
+ctr tsch    .32 352 0  # (C64x+ only) Time-stamp counter (high 32) register
+ctr tscl    .32 356 0  # (C64x+ only) Time-stamp counter (low 32) register
+ctr tsr     .32 360 0  # (C64x+ only) Task state register
+gpr	a0:a1 	.64	364	0
+gpr	a2:a3 	.64	368	0
+gpr	a4:a5 	.64	372	0
+gpr	a6:a7 	.64	376	0
+gpr	a8:a9 	.64	380	0
+gpr	a10:a11	.64	384	0
+gpr	a12:a13	.64	388	0
+gpr	a14:a15	.64	392	0
+gpr	a16:a17	.64	396	0
+gpr	a18:a19	.64	400	0
+gpr	a20:a21	.64	404	0
+gpr	a22:a23	.64	408	0
+gpr	a24:a25	.64	412	0
+gpr	a26:a27	.64	416	0
+gpr	a28:a29	.64	420	0
+gpr	a30:a31	.64	424	0
+gpr	b0:b1 	.64	428	0
+gpr	b2:b3 	.64	432	0
+gpr	b4:b5 	.64	436	0
+gpr	b6:b7 	.64	440	0
+gpr	b8:b9 	.64	444	0
+gpr	b10:b11	.64	448	0
+gpr	b12:b13	.64	452	0
+gpr	b14:b15	.64	456	0
+gpr	b16:b17	.64	460	0
+gpr	b18:b19	.64	464	0
+gpr	b20:b21	.64	468	0
+gpr	b22:b23	.64	472	0
+gpr	b24:b25	.64	476	0
+gpr	b26:b27	.64	480	0
+gpr	b28:b29	.64	484	0
+gpr	b30:b31	.64	488	0
+
+EOF
+RUN