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Fix FNEQ: x and y were interchanged. (#3973)

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* Fix FNEQ: x and y were interchanged.
* Add macros for LT, LE, GT, GE
* Add a test for NaN.
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Rot127 2023-11-20 04:52:43 +00:00 committed by GitHub
parent 947e9b574e
commit 41e700bbcd
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3 changed files with 11 additions and 3 deletions
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8
librz/include/rz_il/rz_il_opbuilder_begin.h
View file

@ -98,8 +98,12 @@
#define AND(x, y) rz_il_op_new_bool_and(x, y)
#define OR(x, y) rz_il_op_new_bool_or(x, y)
#define FNEQ(flx, fly) OR(FORDER(flx, fly), FORDER(DUP(flx), DUP(fly)))
#define FEQ(flx, fly) INV(FNEQ(flx, fly))
#define FNEQ(flx, fly) OR(OR(IS_FNAN(flx), IS_FNAN(fly)), OR(FORDER(DUP(flx), DUP(fly)), FORDER(DUP(fly), DUP(flx))))
#define FEQ(flx, fly) AND(INV(OR(IS_FNAN(flx), IS_FNAN(fly))), INV(FNEQ(DUP(flx), DUP(fly))))
#define FLT(flx, fly) AND(INV(OR(IS_FNAN(flx), IS_FNAN(fly))), FORDER(DUP(flx), DUP(fly)))
#define FLE(flx, fly) AND(INV(OR(IS_FNAN(flx), IS_FNAN(fly))), OR(FLT(DUP(flx), DUP(fly)), FEQ(DUP(flx), DUP(fly))))
#define FGT(flx, fly) AND(INV(OR(IS_FNAN(flx), IS_FNAN(fly))), INV(FLE(DUP(flx), DUP(fly))))
#define FGE(flx, fly) AND(INV(OR(IS_FNAN(flx), IS_FNAN(fly))), INV(FLT(DUP(flx), DUP(fly))))
#define UNSIGNED(n, x) rz_il_op_new_unsigned(n, x)
#define SIGNED(n, x) rz_il_op_new_signed(n, x)

4
librz/include/rz_il/rz_il_opbuilder_end.h
View file

@ -56,6 +56,10 @@
#undef FMAD
#undef FNEQ
#undef FEQ
#undef FLT
#undef FLE
#undef FGE
#undef FGT
#undef IL_FALSE
#undef IL_TRUE

2
test/db/asm/arm_32
View file

@ -691,7 +691,7 @@ d "vacgt.f32 q0, q1, q2" 540e22f3 0x0 (seq empty (set d0 (cast 64 false (<< (cas
d "vceq.i8 d0, d1, d2" 120801f3 0x0 (seq empty (set d0 (<< (cast 64 false (ite (== (cast 8 false (>> (var d1) (bv 8 0x0) false)) (cast 8 false (>> (var d2) (bv 8 0x0) false))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x0) false)) (set d0 (<< (cast 64 false (ite (== (cast 8 false (>> (var d1) (bv 8 0x8) false)) (cast 8 false (>> (var d2) (bv 8 0x8) false))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x8) false)) (set d0 (<< (cast 64 false (ite (== (cast 8 false (>> (var d1) (bv 8 0x10) false)) (cast 8 false (>> (var d2) (bv 8 0x10) false))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x10) false)) (set d0 (<< (cast 64 false (ite (== (cast 8 false (>> (var d1) (bv 8 0x18) false)) (cast 8 false (>> (var d2) (bv 8 0x18) false))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x18) false)) (set d0 (<< (cast 64 false (ite (== (cast 8 false (>> (var d1) (bv 8 0x20) false)) (cast 8 false (>> (var d2) (bv 8 0x20) false))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x20) false)) (set d0 (<< (cast 64 false (ite (== (cast 8 false (>> (var d1) (bv 8 0x28) false)) (cast 8 false (>> (var d2) (bv 8 0x28) false))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x28) false)) (set d0 (<< (cast 64 false (ite (== (cast 8 false (>> (var d1) (bv 8 0x30) false)) (cast 8 false (>> (var d2) (bv 8 0x30) false))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x30) false)) (set d0 (<< (cast 64 false (ite (== (cast 8 false (>> (var d1) (bv 8 0x38) false)) (cast 8 false (>> (var d2) (bv 8 0x38) false))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x38) false)))
d "vceq.i16 d0, d1, d2" 120811f3 0x0 (seq empty (set d0 (<< (cast 64 false (ite (== (cast 16 false (>> (var d1) (bv 8 0x0) false)) (cast 16 false (>> (var d2) (bv 8 0x0) false))) (~ (bv 16 0x0)) (bv 16 0x0))) (bv 8 0x0) false)) (set d0 (<< (cast 64 false (ite (== (cast 16 false (>> (var d1) (bv 8 0x10) false)) (cast 16 false (>> (var d2) (bv 8 0x10) false))) (~ (bv 16 0x0)) (bv 16 0x0))) (bv 8 0x10) false)) (set d0 (<< (cast 64 false (ite (== (cast 16 false (>> (var d1) (bv 8 0x20) false)) (cast 16 false (>> (var d2) (bv 8 0x20) false))) (~ (bv 16 0x0)) (bv 16 0x0))) (bv 8 0x20) false)) (set d0 (<< (cast 64 false (ite (== (cast 16 false (>> (var d1) (bv 8 0x30) false)) (cast 16 false (>> (var d2) (bv 8 0x30) false))) (~ (bv 16 0x0)) (bv 16 0x0))) (bv 8 0x30) false)))
d "vceq.i32 d0, d1, d2" 120821f3 0x0 (seq empty (set d0 (<< (cast 64 false (ite (== (cast 32 false (>> (var d1) (bv 8 0x0) false)) (cast 32 false (>> (var d2) (bv 8 0x0) false))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x0) false)) (set d0 (<< (cast 64 false (ite (== (cast 32 false (>> (var d1) (bv 8 0x20) false)) (cast 32 false (>> (var d2) (bv 8 0x20) false))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x20) false)))
d "vceq.f32 d0, d1, d2" 020e01f2 0x0 (seq empty (set d0 (<< (cast 64 false (ite (! (|| (<. (float 0 (cast 32 false (>> (var d1) (bv 8 0x0) false)) ) (float 0 (cast 32 false (>> (var d2) (bv 8 0x0) false)) )) (<. (float 0 (cast 32 false (>> (var d1) (bv 8 0x0) false)) ) (float 0 (cast 32 false (>> (var d2) (bv 8 0x0) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x0) false)) (set d0 (<< (cast 64 false (ite (! (|| (<. (float 0 (cast 32 false (>> (var d1) (bv 8 0x20) false)) ) (float 0 (cast 32 false (>> (var d2) (bv 8 0x20) false)) )) (<. (float 0 (cast 32 false (>> (var d1) (bv 8 0x20) false)) ) (float 0 (cast 32 false (>> (var d2) (bv 8 0x20) false)) )))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x20) false)))
d "vceq.f32 d0, d1, d2" 020e01f2 0x0 (seq empty (set d0 (<< (cast 64 false (ite (&& (! (|| (is_nan (float 0 (cast 32 false (>> (var d1) (bv 8 0x0) false)) )) (is_nan (float 0 (cast 32 false (>> (var d2) (bv 8 0x0) false)) )))) (! (|| (|| (is_nan (float 0 (cast 32 false (>> (var d1) (bv 8 0x0) false)) )) (is_nan (float 0 (cast 32 false (>> (var d2) (bv 8 0x0) false)) ))) (|| (<. (float 0 (cast 32 false (>> (var d1) (bv 8 0x0) false)) ) (float 0 (cast 32 false (>> (var d2) (bv 8 0x0) false)) )) (<. (float 0 (cast 32 false (>> (var d2) (bv 8 0x0) false)) ) (float 0 (cast 32 false (>> (var d1) (bv 8 0x0) false)) )))))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x0) false)) (set d0 (<< (cast 64 false (ite (&& (! (|| (is_nan (float 0 (cast 32 false (>> (var d1) (bv 8 0x20) false)) )) (is_nan (float 0 (cast 32 false (>> (var d2) (bv 8 0x20) false)) )))) (! (|| (|| (is_nan (float 0 (cast 32 false (>> (var d1) (bv 8 0x20) false)) )) (is_nan (float 0 (cast 32 false (>> (var d2) (bv 8 0x20) false)) ))) (|| (<. (float 0 (cast 32 false (>> (var d1) (bv 8 0x20) false)) ) (float 0 (cast 32 false (>> (var d2) (bv 8 0x20) false)) )) (<. (float 0 (cast 32 false (>> (var d2) (bv 8 0x20) false)) ) (float 0 (cast 32 false (>> (var d1) (bv 8 0x20) false)) )))))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x20) false)))
d "vcge.s8 d0, d1, d2" 120301f2 0x0 (seq empty (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 8 false (>> (var d1) (bv 8 0x0) false)) (cast 8 false (>> (var d2) (bv 8 0x0) false)))) (== (cast 8 false (>> (var d1) (bv 8 0x0) false)) (cast 8 false (>> (var d2) (bv 8 0x0) false)))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x0) false)) (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 8 false (>> (var d1) (bv 8 0x8) false)) (cast 8 false (>> (var d2) (bv 8 0x8) false)))) (== (cast 8 false (>> (var d1) (bv 8 0x8) false)) (cast 8 false (>> (var d2) (bv 8 0x8) false)))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x8) false)) (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 8 false (>> (var d1) (bv 8 0x10) false)) (cast 8 false (>> (var d2) (bv 8 0x10) false)))) (== (cast 8 false (>> (var d1) (bv 8 0x10) false)) (cast 8 false (>> (var d2) (bv 8 0x10) false)))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x10) false)) (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 8 false (>> (var d1) (bv 8 0x18) false)) (cast 8 false (>> (var d2) (bv 8 0x18) false)))) (== (cast 8 false (>> (var d1) (bv 8 0x18) false)) (cast 8 false (>> (var d2) (bv 8 0x18) false)))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x18) false)) (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 8 false (>> (var d1) (bv 8 0x20) false)) (cast 8 false (>> (var d2) (bv 8 0x20) false)))) (== (cast 8 false (>> (var d1) (bv 8 0x20) false)) (cast 8 false (>> (var d2) (bv 8 0x20) false)))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x20) false)) (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 8 false (>> (var d1) (bv 8 0x28) false)) (cast 8 false (>> (var d2) (bv 8 0x28) false)))) (== (cast 8 false (>> (var d1) (bv 8 0x28) false)) (cast 8 false (>> (var d2) (bv 8 0x28) false)))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x28) false)) (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 8 false (>> (var d1) (bv 8 0x30) false)) (cast 8 false (>> (var d2) (bv 8 0x30) false)))) (== (cast 8 false (>> (var d1) (bv 8 0x30) false)) (cast 8 false (>> (var d2) (bv 8 0x30) false)))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x30) false)) (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 8 false (>> (var d1) (bv 8 0x38) false)) (cast 8 false (>> (var d2) (bv 8 0x38) false)))) (== (cast 8 false (>> (var d1) (bv 8 0x38) false)) (cast 8 false (>> (var d2) (bv 8 0x38) false)))) (~ (bv 8 0x0)) (bv 8 0x0))) (bv 8 0x38) false)))
d "vcge.s16 d0, d1, d2" 120311f2 0x0 (seq empty (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 16 false (>> (var d1) (bv 8 0x0) false)) (cast 16 false (>> (var d2) (bv 8 0x0) false)))) (== (cast 16 false (>> (var d1) (bv 8 0x0) false)) (cast 16 false (>> (var d2) (bv 8 0x0) false)))) (~ (bv 16 0x0)) (bv 16 0x0))) (bv 8 0x0) false)) (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 16 false (>> (var d1) (bv 8 0x10) false)) (cast 16 false (>> (var d2) (bv 8 0x10) false)))) (== (cast 16 false (>> (var d1) (bv 8 0x10) false)) (cast 16 false (>> (var d2) (bv 8 0x10) false)))) (~ (bv 16 0x0)) (bv 16 0x0))) (bv 8 0x10) false)) (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 16 false (>> (var d1) (bv 8 0x20) false)) (cast 16 false (>> (var d2) (bv 8 0x20) false)))) (== (cast 16 false (>> (var d1) (bv 8 0x20) false)) (cast 16 false (>> (var d2) (bv 8 0x20) false)))) (~ (bv 16 0x0)) (bv 16 0x0))) (bv 8 0x20) false)) (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 16 false (>> (var d1) (bv 8 0x30) false)) (cast 16 false (>> (var d2) (bv 8 0x30) false)))) (== (cast 16 false (>> (var d1) (bv 8 0x30) false)) (cast 16 false (>> (var d2) (bv 8 0x30) false)))) (~ (bv 16 0x0)) (bv 16 0x0))) (bv 8 0x30) false)))
d "vcge.s32 d0, d1, d2" 120321f2 0x0 (seq empty (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 32 false (>> (var d1) (bv 8 0x0) false)) (cast 32 false (>> (var d2) (bv 8 0x0) false)))) (== (cast 32 false (>> (var d1) (bv 8 0x0) false)) (cast 32 false (>> (var d2) (bv 8 0x0) false)))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x0) false)) (set d0 (<< (cast 64 false (ite (|| (! (sle (cast 32 false (>> (var d1) (bv 8 0x20) false)) (cast 32 false (>> (var d2) (bv 8 0x20) false)))) (== (cast 32 false (>> (var d1) (bv 8 0x20) false)) (cast 32 false (>> (var d2) (bv 8 0x20) false)))) (~ (bv 32 0x0)) (bv 32 0x0))) (bv 8 0x20) false)))