librz/arch: add Xtensa RzIL support (#4712)
- **Add support for rzIL**: Implement various Xtensa instructions and functionalities. - **Instruction Set Additions**: - **Arithmetic and Logical Operations**: sub*, add*, and*, or*, xor*, mul*, div*, rem*, neg*, abs, addi*, addmi, addexp*, addexpm*, addx2|4|8 - **Bitwise Operations**: srl*, sra*, sll*, andb, andbc, nsau, nsa - **Branching and Jumps**: b*, beq*, bne*, ball, bany, bnall, bnone, j, jx, loop*, loopgez, loopnez - **Data Transfer**: st*, ld*, l32*, l16*, l8ui, ssi*, ssa*, src - **Floating Point**: sqrt0.s, float.s, floor.s, trunc*, ueq*, ule*, ult*, ufloat*, neg.s, oeq.s, ole.s, olt.s, min, max, clamps, nex - **System Calls and Synchronization**: syscall, simcall, entry, isync, dsync, esync, rsync, memw - **Miscellaneous**: const_s, extui, extw, excw, sext, witlb, wur, rur.*, mksadj.ss, mkdadj.s, const_s - **Testing and Patches**: - Implement asm tests for all - **Miscellaneous Improvements**: - Update Capstone and fix ARM architecture support for building.
This commit is contained in:
billow
GitHub
parent
4c055aaffa
commit
42302da16d
10 changed files with 2730 additions and 27 deletions
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@ -201,6 +201,9 @@ static void setup_vm_init_state(RzAnalysisILVM *vm, RZ_NULLABLE RzAnalysisILInit
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rz_vector_foreach (&is->vars, v) {
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rz_il_vm_set_global_var(vm->vm, v->name, rz_il_value_dup(v->val));
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}
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if (is->cb) {
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is->cb(vm, reg);
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}
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}
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}
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@ -31,6 +31,8 @@ bool xtensa_open(XtensaContext *ctx, const char *cpu, bool big_endian);
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bool xtensa_disassemble(XtensaContext *self, const ut8 *buf, int len, ut64 addr);
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void xtensa_disassemble_fini(XtensaContext *self);
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void xtensa_analyze_op_esil(XtensaContext *ctx, RzAnalysisOp *op);
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void xtensa_analyze_op_rzil(XtensaContext *ctx, RzAnalysisOp *op);
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RzAnalysisILConfig *xtensa_il_config(RzAnalysis *a);
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static inline cs_xtensa_op_mem *xtensa_op_mem(cs_insn *insn, unsigned int index) {
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cs_xtensa_op *op = &insn->detail->xtensa.operands[index];
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@ -56,12 +58,13 @@ static inline int32_t xtensa_op_l32r(cs_insn *insn, unsigned int index) {
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return op->imm;
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}
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#define XOP(I) (ctx->insn->detail->xtensa.operands + I)
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#define MEM(I) xtensa_op_mem(ctx->insn, I)
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#define REGI(I) xtensa_op_reg(ctx->insn, I)
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#define REGN(I) cs_reg_name(ctx->handle, (xtensa_op_reg(ctx->insn, I)))
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#define IMM(I) xtensa_op_imm(ctx->insn, I)
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#define L32R(I) xtensa_op_l32r(ctx->insn, I)
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#define INSN_SIZE (ctx->insn->size)
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#define XOP(I) (ctx->insn->detail->xtensa.operands + I)
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#define MEM(I) xtensa_op_mem(ctx->insn, I)
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#define REGI(I) xtensa_op_reg(ctx->insn, I)
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#define REGNAME(I) cs_reg_name(ctx->handle, (I))
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#define REGN(I) REGNAME(REGI((I)))
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#define IMM(I) xtensa_op_imm(ctx->insn, I)
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#define L32R(I) xtensa_op_l32r(ctx->insn, I)
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#define INSN_SIZE (ctx->insn->size)
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#endif // RZ_XTENSA_H
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2169
librz/arch/isa/xtensa/xtensa_il.c
Normal file
2169
librz/arch/isa/xtensa/xtensa_il.c
Normal file
File diff suppressed because it is too large
Load diff
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@ -338,6 +338,7 @@ if capstone_dep.version() == 'next'
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arch_isa_sources += [
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'isa/xtensa/xtensa.c',
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'isa/xtensa/xtensa_esil.c',
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'isa/xtensa/xtensa_il.c',
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]
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endif
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@ -58,6 +58,166 @@ static char *xtensa_get_reg_profile(RzAnalysis *analysis) {
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"gpr a14 .32 60 0\n"
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"gpr a15 .32 64 0\n"
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"gpr f0 .64 76 0\n"
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"gpr f1 .64 84 0\n"
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"gpr f2 .64 92 0\n"
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"gpr f3 .64 100 0\n"
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"gpr f4 .64 108 0\n"
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"gpr f5 .64 116 0\n"
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"gpr f6 .64 124 0\n"
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"gpr f7 .64 132 0\n"
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"gpr f8 .64 140 0\n"
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"gpr f9 .64 148 0\n"
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"gpr f10 .64 156 0\n"
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"gpr f11 .64 164 0\n"
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"gpr f12 .64 172 0\n"
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"gpr f13 .64 180 0\n"
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"gpr f14 .64 188 0\n"
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"gpr f15 .64 196 0\n"
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"gpr b0 .1 210 0\n"
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"gpr b1 .1 211 0\n"
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"gpr b2 .1 212 0\n"
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"gpr b3 .1 213 0\n"
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"gpr b4 .1 214 0\n"
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"gpr b5 .1 215 0\n"
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"gpr b6 .1 216 0\n"
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"gpr b7 .1 217 0\n"
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"gpr b8 .1 218 0\n"
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"gpr b9 .1 219 0\n"
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"gpr b10 .1 220 0\n"
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"gpr b11 .1 221 0\n"
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"gpr b12 .1 222 0\n"
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"gpr b13 .1 223 0\n"
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"gpr b14 .1 224 0\n"
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"gpr b15 .1 225 0\n"
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/*Special Registers*/
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/*0*/ "gpr lbeg .32 226 0\n"
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/*1*/ "gpr lend .32 230 0\n"
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/*2*/ "gpr lcount .32 234 0\n"
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/*3*/ "gpr sar .32 238 0\n"
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/*4*/ "gpr br .32 242 0\n"
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/*5*/ "gpr litbase .32 246 0\n"
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/*12*/ "gpr scompare1 .32 274 0\n"
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/*16*/ "gpr acclo .32 290 0\n"
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/*17*/ "gpr acchi .32 294 0\n"
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/*32*/ "gpr m0 .32 354 0\n"
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/*33*/ "gpr m1 .32 358 0\n"
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/*34*/ "gpr m2 .32 362 0\n"
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/*35*/ "gpr m3 .32 366 0\n"
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/*72*/ "gpr windowbase .32 514 0\n"
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/*73*/ "gpr windowstart .32 518 0\n"
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/*83*/ "gpr ptevaddr .32 546 0\n"
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/*90*/ "gpr rasid .32 570 0\n"
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/*91*/ "gpr itlbcfg .32 574 0\n"
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/*92*/ "gpr dtlbcfg .32 578 0\n"
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/*95*/ "gpr eracess .32 586 0\n"
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/*96*/ "gpr ibreakenable .32 590 0\n"
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/*97*/ "gpr memctl .32 594 0\n"
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/*99*/ "gpr atomctl .32 602 0\n"
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/*104*/ "gpr ddr .32 618 0\n"
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/*106*/ "gpr mepc .32 626 0\n"
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/*107*/ "gpr meps .32 630 0\n"
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/*108*/ "gpr mesave .32 634 0\n"
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/*109*/ "gpr mesr .32 638 0\n"
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/*110*/ "gpr mecr .32 642 0\n"
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/*111*/ "gpr mevaddr .32 646 0\n"
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/*128*/ "gpr ibreaka0 .32 690 0\n"
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/*129*/ "gpr ibreaka1 .32 694 0\n"
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/*144*/ "gpr dbreaka0 .32 738 0\n"
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/*145*/ "gpr dbreaka1 .32 742 0\n"
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/*160*/ "gpr dbreakc0 .32 786 0\n"
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/*161*/ "gpr dbreakc1 .32 790 0\n"
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/*177*/ "gpr epc1 .32 934 0\n"
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/*178*/ "gpr epc2 .32 938 0\n"
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/*179*/ "gpr epc3 .32 942 0\n"
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/*180*/ "gpr epc4 .32 946 0\n"
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/*181*/ "gpr epc5 .32 950 0\n"
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/*182*/ "gpr epc6 .32 954 0\n"
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/*183*/ "gpr epc7 .32 958 0\n"
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/*192*/ "gpr depc .32 994 0\n"
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/*193*/ "gpr eps1 .32 998 0\n"
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/*194*/ "gpr eps2 .32 1002 0\n"
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/*195*/ "gpr eps3 .32 1006 0\n"
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/*196*/ "gpr eps4 .32 1010 0\n"
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/*197*/ "gpr eps5 .32 1014 0\n"
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/*198*/ "gpr eps6 .32 1018 0\n"
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/*199*/ "gpr eps7 .32 1022 0\n"
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/*209*/ "gpr excsave1 .32 1062 0\n"
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/*210*/ "gpr excsave2 .32 1066 0\n"
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/*211*/ "gpr excsave3 .32 1070 0\n"
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/*212*/ "gpr excsave4 .32 1074 0\n"
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/*213*/ "gpr excsave5 .32 1078 0\n"
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/*214*/ "gpr excsave6 .32 1082 0\n"
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/*215*/ "gpr excsave7 .32 1086 0\n"
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/*224*/ "gpr cpenable .32 1122 0\n"
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/*226*/ "gpr interrupt .32 1126 0\n"
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/*227*/ "gpr intclear .32 1130 0\n"
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/*228*/ "gpr intenable .32 1134 0\n"
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/*230*/ "gpr ps .32 1138 0\n"
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/*231*/ "gpr vecbase .32 1142 0\n"
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/*232*/ "gpr exccause .32 1146 0\n"
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/*233*/ "gpr debugcause .32 1150 0\n"
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/*234*/ "gpr ccount .32 1154 0\n"
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/*235*/ "gpr prid .32 1158 0\n"
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/*236*/ "gpr icount .32 1162 0\n"
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/*237*/ "gpr icountlevel .32 1166 0\n"
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/*238*/ "gpr excvaddr .32 1170 0\n"
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/*240*/ "gpr ccompare0 .32 1178 0\n"
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/*241*/ "gpr ccompare1 .32 1182 0\n"
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/*242*/ "gpr ccompare2 .32 1186 0\n"
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/*244*/ "gpr misc0 .32 1190 0\n"
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/*245*/ "gpr misc1 .32 1194 0\n"
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/*246*/ "gpr misc2 .32 1198 0\n"
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/*247*/ "gpr misc3 .32 1202 0\n"
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"gpr ndepc .1 2000 0\n"
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"gpr ResetVector .32 2004 0\n"
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"gpr UserExceptionVector .32 2008 0\n"
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"gpr KernelExceptionVector .32 2012 0\n"
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"gpr DoubleExceptionVector .32 2016 0\n"
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"gpr accx_0 .32 3000 0\n"
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"gpr accx_1 .32 3004 0\n"
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"gpr bithead .32 3008 0\n"
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"gpr bitptr .32 3012 0\n"
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"gpr bitsused .32 3016 0\n"
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"gpr cbegin0 .32 3020 0\n"
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"gpr cend0 .32 3024 0\n"
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"gpr cwrap .32 3028 0\n"
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"gpr cw_sd_no .32 3032 0\n"
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"gpr first_ts .32 3036 0\n"
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"gpr nextoffset .32 3040 0\n"
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"gpr overflow .32 3044 0\n"
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"gpr ovf_sar .32 3048 0\n"
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"gpr sar .32 3052 0\n"
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"gpr searchdone .32 3056 0\n"
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"gpr tablesize .32 3060 0\n"
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"gpr ts_fts_bu_bp .32 3064 0\n"
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"gpr fft_bit_width .32 3068 0\n"
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"gpr gpio_out .32 3072 0\n"
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"gpr qacc_h_0 .32 3076 0\n"
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"gpr qacc_h_1 .32 3080 0\n"
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"gpr qacc_h_2 .32 3084 0\n"
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"gpr qacc_h_3 .32 3088 0\n"
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"gpr qacc_h_4 .32 3092 0\n"
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"gpr qacc_l_0 .32 3096 0\n"
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"gpr qacc_l_1 .32 3100 0\n"
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"gpr qacc_l_2 .32 3104 0\n"
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"gpr qacc_l_3 .32 3108 0\n"
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"gpr qacc_l_4 .32 3112 0\n"
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"gpr sar_byte .32 3116 0\n"
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"gpr ua_state_0 .32 3120 0\n"
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"gpr ua_state_1 .32 3124 0\n"
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"gpr ua_state_2 .32 3128 0\n"
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"gpr ua_state_3 .32 3132 0\n"
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"gpr windowunderflow4 .32 3136 0\n"
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"gpr windowunderflow8 .32 3140 0\n"
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"gpr windowunderflow12 .32 3144 0\n"
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"gpr fcr .32 4000 0\n"
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"gpr fsr .32 4004 0\n"
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// pc
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"gpr pc .32 68 0\n"
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@ -140,6 +300,11 @@ static void xop_to_rval(RzAnalysis *a, XtensaContext *ctx, cs_xtensa_op *xop, Rz
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static void xtensa_analyze_op(RzAnalysis *a, RzAnalysisOp *op, XtensaContext *ctx) {
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int src_count = 0;
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for (int i = 0; i < ctx->insn->detail->xtensa.op_count; ++i) {
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if (src_count >= RZ_ARRAY_SIZE(op->src)) {
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rz_warn_if_reached();
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break;
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}
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cs_xtensa_op *xop = XOP(i);
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if (xop->access & CS_AC_WRITE) {
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xop_to_rval(a, ctx, xop, &op->dst);
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@ -276,7 +441,7 @@ static void xtensa_analyze_op(RzAnalysis *a, RzAnalysisOp *op, XtensaContext *ct
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case XTENSA_INS_CALL8:
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case XTENSA_INS_CALL12:
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op->type = RZ_ANALYSIS_OP_TYPE_CALL;
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op->jump = ctx->insn->address + IMM(0);
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op->jump = (ctx->insn->address + IMM(0)) & ~3;
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op->fail = ctx->insn->address + ctx->insn->size;
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break;
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case XTENSA_INS_MOVEQZ: /* moveqz */
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@ -325,6 +490,9 @@ static int xtensa_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut
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goto beach;
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}
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op->size = ctx->insn->size;
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op->id = ctx->insn->id;
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op->addr = addr;
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xtensa_analyze_op(analysis, op, ctx);
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if (mask & RZ_ANALYSIS_OP_MASK_DISASM) {
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@ -339,9 +507,9 @@ static int xtensa_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut
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xtensa_analyze_op_esil(ctx, op);
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}
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op->size = ctx->insn->size;
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op->id = ctx->insn->id;
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op->addr = addr;
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if (mask & RZ_ANALYSIS_OP_MASK_IL) {
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xtensa_analyze_op_rzil(ctx, op);
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}
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xtensa_disassemble_fini(ctx);
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return op->size;
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@ -359,6 +527,7 @@ RzAnalysisPlugin rz_analysis_plugin_xtensa_cs = {
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.bits = 8,
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.op = xtensa_op,
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.esil = true,
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.il_config = xtensa_il_config,
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.archinfo = xtensa_archinfo,
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.get_reg_profile = xtensa_get_reg_profile,
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.init = xtensa_init,
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@ -928,7 +928,7 @@ typedef struct rz_analysis_op_t {
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st64 stackptr; /* stack pointer */
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int refptr; /* if (0) ptr = "reference" else ptr = "load memory of refptr bytes" */
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ut64 mmio_address; // mmio address
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RzAnalysisValue *src[6];
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RzAnalysisValue *src[8];
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RzAnalysisValue *dst;
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RzList /*<RzAnalysisValue *>*/ *access; /* RzAnalysisValue access information */
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RzStrBuf esil;
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@ -1230,6 +1230,8 @@ typedef struct rz_analysis_il_init_state_var_t {
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RZ_NONNULL RzILVal *val;
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} RzAnalysisILInitStateVar;
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typedef void (*RzAnalysisILInitCallback)(RzAnalysisILVM *vm, RzReg *reg);
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/**
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* \brief Description of an initial state of an RzAnalysisILVM
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*
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@ -1240,6 +1242,7 @@ typedef struct rz_analysis_il_init_state_var_t {
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*/
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typedef struct rz_analysis_il_init_state_t {
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RzVector /*<RzAnalysisILInitStateVar>*/ vars; ///< Contents of global variables
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RzAnalysisILInitCallback cb; ///< Callback to run after the initial state has been set up
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} RzAnalysisILInitState;
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/**
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323
test/db/asm/xtensa
Normal file
323
test/db/asm/xtensa
Normal file
File diff suppressed because one or more lines are too long
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@ -445,7 +445,7 @@ a____ 16 32 64 x86.nasm LGPL3 X86 nasm assembler
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a____ 16 32 64 x86.nz LGPL3 x86 handmade assembler
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_dA__ 16 xap PD XAP4 RISC (CSR)
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_dA__ 32 xcore BSD Capstone XCore disassembler (by pancake)
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_dAe_ 32 xtensa LGPL3 Capstone Xtensa disassembly plugin (by billow)
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_dAeI 32 xtensa LGPL3 Capstone Xtensa disassembly plugin (by billow)
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adA__ 8 z80 GPL3 Zilog Z80 (by condret)
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EOF
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RUN
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@ -67,18 +67,18 @@ e asm.arch=xtensa
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e asm.bits=32
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wx c5000022a020c00200000000000000008000000000000000000000000000000002a030c00000
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aes
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ar~pc
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ar~a0
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ar~^pc
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ar~^a0
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aes
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aes
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ar~a2
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aes
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ar~pc
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ar~a0
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ar~^pc
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ar~^a0
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aes
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aes
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ar~pc
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ar~a0
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ar~^pc
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ar~^a0
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EOF
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EXPECT=<<EOF
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pc = 0x00000010
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@ -99,11 +99,11 @@ e asm.bits=32
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wx 22a002e6320526320200000086fdff
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aes
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aes
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ar~pc
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ar~^pc
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aes
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ar~pc
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ar~^pc
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aes
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ar~pc
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ar~^pc
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EOF
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EXPECT=<<EOF
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pc = 0x0000000c
|
||||
|
|
@ -120,7 +120,7 @@ e asm.bits=32
|
|||
wx 22a002d6920000000000000000000000060000
|
||||
aes
|
||||
aes
|
||||
ar~pc
|
||||
ar~^pc
|
||||
EOF
|
||||
EXPECT=<<EOF
|
||||
pc = 0x00000010
|
||||
|
|
@ -137,7 +137,7 @@ aes
|
|||
aes
|
||||
aes
|
||||
aes
|
||||
ar~pc
|
||||
ar~^pc
|
||||
EOF
|
||||
EXPECT=<<EOF
|
||||
pc = 0x00000010
|
||||
|
|
@ -155,7 +155,7 @@ aeip
|
|||
aes
|
||||
aes
|
||||
aes
|
||||
ar~pc
|
||||
ar~^pc
|
||||
EOF
|
||||
EXPECT=<<EOF
|
||||
pc = 0x00000020
|
||||
|
|
@ -172,7 +172,7 @@ s 0x10
|
|||
aeip
|
||||
aes
|
||||
aes
|
||||
ar~pc
|
||||
ar~^pc
|
||||
EOF
|
||||
EXPECT=<<EOF
|
||||
pc = 0x00000020
|
||||
|
|
@ -190,7 +190,7 @@ aeip
|
|||
aes
|
||||
aes
|
||||
aes
|
||||
ar~pc
|
||||
ar~^pc
|
||||
EOF
|
||||
EXPECT=<<EOF
|
||||
pc = 0x00000020
|
||||
|
|
|
|||
32
test/db/rzil/xtensa
Normal file
32
test/db/rzil/xtensa
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
NAME=Testing the decryption in emulateme
|
||||
FILE=bins/xtensa/emulateme.xtensa-esp32-elf
|
||||
TIMEOUT=30
|
||||
CMDS=<<EOF
|
||||
e analysis.cpu=esp32
|
||||
aaa
|
||||
pdf @ main
|
||||
e io.cache=1
|
||||
aezi
|
||||
aezsu 0x400238
|
||||
ps @ obj.seckrit
|
||||
EOF
|
||||
EXPECT=<<EOF
|
||||
; DATA XREF from entry0 @ 0x4000d1
|
||||
/ int main(int argc, char **argv, char **envp);
|
||||
| ; arg int argc @ a2
|
||||
| ; arg char **argv @ a3
|
||||
| ; arg int32_t arg6 @ a7
|
||||
| 0x00400220 entry a1, 0x40
|
||||
| 0x00400223 mov.n a7, a1 ; arg6
|
||||
| 0x00400225 s32i.n a2, a7, 0x10 ; arg6
|
||||
| 0x00400227 s32i.n a3, a7, 0x14 ; arg6
|
||||
| 0x00400229 l32r a8, . 0x4000b4 ; 0x400264 ; "AnyColourYouLike"
|
||||
| 0x0040022c s32i.n a8, a7, 0 ; arg6
|
||||
| 0x0040022e l32i a10, a7, 0 ; arg6
|
||||
| 0x00400231 call8 . -0xb4 ; sym.decrypt
|
||||
| 0x00400234 movi.n a8, 0
|
||||
| 0x00400236 mov.n a2, a8
|
||||
\ 0x00400238 retw.n
|
||||
Hello from RzIL!
|
||||
EOF
|
||||
RUN
|
||||
Loading…
Reference in a new issue