diff --git a/librz/arch/isa/m68k/m68k_cs.h b/librz/arch/isa/m68k/m68k_cs.h new file mode 100644 index 0000000000..9f9eef27ea --- /dev/null +++ b/librz/arch/isa/m68k/m68k_cs.h @@ -0,0 +1,48 @@ +// SPDX-FileCopyrightText: 2026 RizinOrg +// SPDX-License-Identifier: LGPL-3.0-only + +#ifndef RZ_M68K_CS_H +#define RZ_M68K_CS_H + +#include +#include + +#define M68K_LONGEST_INSTRUCTION 22 + +#if CS_NEXT_VERSION >= 7 +#define M68K_CPUS "68000,68010,68020,68030,68040,68060,cpu32" +#else +#define M68K_CPUS "68000,68010,68020,68030,68040,68060" +#endif + +static inline cs_mode rz_m68k_cs_mode(const char *cpu) { + if (!cpu) { + return CS_MODE_M68K_040; + } +#if CS_NEXT_VERSION >= 7 + if (strstr(cpu, "cpu32") || strstr(cpu, "CPU32")) { + return CS_MODE_M68K_CPU32; + } +#endif + if (strstr(cpu, "68000")) { + return CS_MODE_M68K_000; + } + if (strstr(cpu, "68010")) { + return CS_MODE_M68K_010; + } + if (strstr(cpu, "68020")) { + return CS_MODE_M68K_020; + } + if (strstr(cpu, "68030")) { + return CS_MODE_M68K_030; + } + if (strstr(cpu, "68040")) { + return CS_MODE_M68K_040; + } + if (strstr(cpu, "68060")) { + return CS_MODE_M68K_060; + } + return CS_MODE_M68K_040; +} + +#endif diff --git a/librz/arch/p/analysis/analysis_m68k_cs.c b/librz/arch/p/analysis/analysis_m68k_cs.c index fd5b87da7d..03a66ebe0b 100644 --- a/librz/arch/p/analysis/analysis_m68k_cs.c +++ b/librz/arch/p/analysis/analysis_m68k_cs.c @@ -18,6 +18,7 @@ #if CAPSTONE_HAS_M68K #include +#include "m68k/m68k_cs.h" // http://www.mrc.uidaho.edu/mrc/people/jff/digital/M68Kir.html #define OPERAND(x) insn->detail->m68k.operands[x] @@ -187,41 +188,21 @@ static int m68k_analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 cs_m68k *m68k; cs_detail *detail; - cs_mode mode = CS_MODE_M68K_040; + cs_mode mode = rz_m68k_cs_mode(a->cpu); - // mode |= (a->bits==64)? CS_MODE_64: CS_MODE_32; if (mode != ctx->omode || a->bits != ctx->obits) { cs_close(&ctx->handle); ctx->handle = 0; - ctx->omode = mode; + ctx->omode = -1; ctx->obits = a->bits; } - // XXX no arch->cpu ?!?! CS_MODE_MICRO, N64 - // replace this with the asm.features? - if (a->cpu && strstr(a->cpu, "68000")) { - mode |= CS_MODE_M68K_000; - } - if (a->cpu && strstr(a->cpu, "68010")) { - mode |= CS_MODE_M68K_010; - } - if (a->cpu && strstr(a->cpu, "68020")) { - mode |= CS_MODE_M68K_020; - } - if (a->cpu && strstr(a->cpu, "68030")) { - mode |= CS_MODE_M68K_030; - } - if (a->cpu && strstr(a->cpu, "68040")) { - mode |= CS_MODE_M68K_040; - } - if (a->cpu && strstr(a->cpu, "68060")) { - mode |= CS_MODE_M68K_060; - } op->size = 4; if (ctx->handle == 0) { ret = cs_open(CS_ARCH_M68K, mode, &ctx->handle); if (ret != CS_ERR_OK) { goto fin; } + ctx->omode = mode; cs_option(ctx->handle, CS_OPT_DETAIL, CS_OPT_ON); } n = cs_disasm(ctx->handle, (ut8 *)buf, len, addr, 1, &insn); @@ -724,6 +705,9 @@ fin: } static char *m68k_get_reg_profile(RzAnalysis *analysis) { + // The GPR offsets follow Linux/m68k struct user_regs_struct, which is also + // the ELF core PRSTATUS regset layout. + // https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/m68k/include/asm/user.h const char *p = "=PC pc\n" "=SP a7\n" @@ -732,52 +716,52 @@ static char *m68k_get_reg_profile(RzAnalysis *analysis) { "=A1 a1\n" "=A2 a2\n" "=A3 a3\n" - "gpr d0 .32 0 0\n" - "gpr d1 .32 4 0\n" - "gpr d2 .32 8 0\n" - "gpr d3 .32 12 0\n" - "gpr d4 .32 16 0\n" - "gpr d5 .32 20 0\n" - "gpr d6 .32 24 0\n" - "gpr d7 .32 28 0\n" - "gpr a0 .32 32 0\n" - "gpr a1 .32 36 0\n" - "gpr a2 .32 40 0\n" - "gpr a3 .32 44 0\n" - "gpr a4 .32 48 0\n" - "gpr a5 .32 52 0\n" - "gpr a6 .32 56 0\n" + "gpr d0 .32 56 0\n" + "gpr d1 .32 0 0\n" + "gpr d2 .32 4 0\n" + "gpr d3 .32 8 0\n" + "gpr d4 .32 12 0\n" + "gpr d5 .32 16 0\n" + "gpr d6 .32 20 0\n" + "gpr d7 .32 24 0\n" + "gpr a0 .32 28 0\n" + "gpr a1 .32 32 0\n" + "gpr a2 .32 36 0\n" + "gpr a3 .32 40 0\n" + "gpr a4 .32 44 0\n" + "gpr a5 .32 48 0\n" + "gpr a6 .32 52 0\n" "gpr a7 .32 60 0\n" - "gpr pc .32 64 0\n" - "gpr ccr .8 68 0\n" // subset of the SR, available from any mode - "gpr fp0 .32 69 0\n" // FPU register 0, 96bits to write and read max - "gpr fp1 .32 73 0\n" // FPU register 1, 96bits to write and read max - "gpr fp2 .32 77 0\n" // FPU register 2, 96bits to write and read max - "gpr fp3 .32 81 0\n" // FPU register 3, 96bits to write and read max - "gpr fp4 .32 85 0\n" // FPU register 4, 96bits to write and read max - "gpr fp5 .32 89 0\n" // FPU register 5, 96bits to write and read max - "gpr fp6 .32 93 0\n" // FPU register 6, 96bits to write and read max - "gpr fp7 .32 97 0\n" // FPU register 7, 96bits to write and read max - "gpr fpcr .32 101 0\n" - "gpr fpsr .32 105 0\n" - "gpr fpiar .32 109 0\n" - "gpr sr .32 113 0\n" // only available for read and write access during supervisor mode 16bit - "gpr sfc .32 117 0\n" // source function code register - "gpr dfc .32 121 0\n" // destination function code register - "gpr usp .32 125 0\n" // user stack point this is an shadow register of A7 user mode, SR bit 0xD is 0 - "gpr vbr .32 129 0\n" // vector base register, this is a Address pointer - "gpr cacr .32 133 0\n" // cache control register, implementation specific - "gpr caar .32 137 0\n" // cache address register, 68020, 68EC020, 68030 and 68EC030 only. - "gpr msp .32 141 0\n" // master stack pointer, this is an shadow register of A7 supervisor mode, SR bits 0xD && 0xC are set - "gpr isp .32 145 0\n" // interrupt stack pointer, this is an shadow register of A7 supervisor mode, SR bit 0xD is set, 0xC is not. - "gpr tc .32 149 0\n" - "gpr itt0 .32 153 0\n" // in 68EC040 this is IACR0 - "gpr itt1 .32 157 0\n" // in 68EC040 this is IACR1 - "gpr dtt0 .32 161 0\n" // in 68EC040 this is DACR0 - "gpr dtt1 .32 165 0\n" // in 68EC040 this is DACR1 - "gpr mmusr .32 169 0\n" - "gpr urp .32 173 0\n" - "gpr srp .32 177 0\n"; + "gpr pc .32 72 0\n" + "gpr ccr .8 71 0\n" // subset of the SR, available from any mode + "gpr fp0 .32 80 0\n" // FPU register 0, 96bits to write and read max + "gpr fp1 .32 84 0\n" // FPU register 1, 96bits to write and read max + "gpr fp2 .32 88 0\n" // FPU register 2, 96bits to write and read max + "gpr fp3 .32 92 0\n" // FPU register 3, 96bits to write and read max + "gpr fp4 .32 96 0\n" // FPU register 4, 96bits to write and read max + "gpr fp5 .32 100 0\n" // FPU register 5, 96bits to write and read max + "gpr fp6 .32 104 0\n" // FPU register 6, 96bits to write and read max + "gpr fp7 .32 108 0\n" // FPU register 7, 96bits to write and read max + "gpr fpcr .32 112 0\n" + "gpr fpsr .32 116 0\n" + "gpr fpiar .32 120 0\n" + "gpr sr .16 70 0\n" // only available for read and write access during supervisor mode + "gpr sfc .32 124 0\n" // source function code register + "gpr dfc .32 128 0\n" // destination function code register + "gpr usp .32 60 0\n" // user stack point this is an shadow register of A7 user mode, SR bit 0xD is 0 + "gpr vbr .32 132 0\n" // vector base register, this is a Address pointer + "gpr cacr .32 136 0\n" // cache control register, implementation specific + "gpr caar .32 140 0\n" // cache address register, 68020, 68EC020, 68030 and 68EC030 only. + "gpr msp .32 144 0\n" // master stack pointer, this is an shadow register of A7 supervisor mode, SR bits 0xD && 0xC are set + "gpr isp .32 148 0\n" // interrupt stack pointer, this is an shadow register of A7 supervisor mode, SR bit 0xD is set, 0xC is not. + "gpr tc .32 152 0\n" + "gpr itt0 .32 156 0\n" // in 68EC040 this is IACR0 + "gpr itt1 .32 160 0\n" // in 68EC040 this is IACR1 + "gpr dtt0 .32 164 0\n" // in 68EC040 this is DACR0 + "gpr dtt1 .32 168 0\n" // in 68EC040 this is DACR1 + "gpr mmusr .32 172 0\n" + "gpr urp .32 176 0\n" + "gpr srp .32 180 0\n"; return rz_str_dup(p); } @@ -795,7 +779,7 @@ static int m68k_archinfo(RzAnalysis *a, RzAnalysisInfoType query) { case RZ_ANALYSIS_ARCHINFO_MIN_OP_SIZE: return 2; case RZ_ANALYSIS_ARCHINFO_MAX_OP_SIZE: - return 4; + return M68K_LONGEST_INSTRUCTION; case RZ_ANALYSIS_ARCHINFO_TEXT_ALIGN: return 2; case RZ_ANALYSIS_ARCHINFO_DATA_ALIGN: diff --git a/librz/arch/p/asm/asm_m68k_cs.c b/librz/arch/p/asm/asm_m68k_cs.c index 4e12ed9ba7..ea2526ee86 100644 --- a/librz/arch/p/asm/asm_m68k_cs.c +++ b/librz/arch/p/asm/asm_m68k_cs.c @@ -7,12 +7,10 @@ #include #include "cs_helper.h" +#include "m68k/m68k_cs.h" CAPSTONE_DEFINE_PLUGIN_FUNCTIONS(m68k_asm); -// Size of the longest instruction in bytes -#define M68K_LONGEST_INSTRUCTION 10 - static int m68k_disassemble(const RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) { if (!buf) { return -1; @@ -21,27 +19,8 @@ static int m68k_disassemble(const RzAsm *a, RzAsmOp *op, const ut8 *buf, int len char *buf_asm = NULL; cs_insn *insn = NULL; int ret = 0, n = 0; - cs_mode mode = CS_MODE_M68K_040; + cs_mode mode = rz_m68k_cs_mode(a->cpu); - // replace this with the asm.features? - if (a->cpu && strstr(a->cpu, "68000")) { - mode |= CS_MODE_M68K_000; - } - if (a->cpu && strstr(a->cpu, "68010")) { - mode |= CS_MODE_M68K_010; - } - if (a->cpu && strstr(a->cpu, "68020")) { - mode |= CS_MODE_M68K_020; - } - if (a->cpu && strstr(a->cpu, "68030")) { - mode |= CS_MODE_M68K_030; - } - if (a->cpu && strstr(a->cpu, "68040")) { - mode |= CS_MODE_M68K_040; - } - if (a->cpu && strstr(a->cpu, "68060")) { - mode |= CS_MODE_M68K_060; - } if (op) { op->size = 4; } @@ -112,6 +91,9 @@ static char **m68k_cpu_descriptions() { "68030", "Motorola 68030: Enhanced 32-bit microprocessor with integrated MMU", "68040", "Motorola 68040: High-performance 32-bit microprocessor with integrated FPU", "68060", "Motorola 68060: 32-bit microprocessor, highest performer in m68k series", +#if CS_NEXT_VERSION >= 7 + "cpu32", "Motorola CPU32: 32-bit embedded-controller CPU core based on the 68020", +#endif NULL }; return cpu_desc; @@ -120,7 +102,7 @@ static char **m68k_cpu_descriptions() { RzAsmPlugin rz_asm_plugin_m68k_cs = { .name = "m68k", .desc = "Motorola 68K Capstone-based disassembler", - .cpus = "68000,68010,68020,68030,68040,68060", + .cpus = M68K_CPUS, .license = "BSD", .arch = "m68k", .bits = 32, diff --git a/librz/bin/format/elf/elf_notes.c b/librz/bin/format/elf/elf_notes.c index 59300268af..b317af7f34 100644 --- a/librz/bin/format/elf/elf_notes.c +++ b/librz/bin/format/elf/elf_notes.c @@ -37,11 +37,13 @@ #define RISCV_32_FP (FP_LAYOUT | RISCV_32) #define RISCV_64_FP (FP_LAYOUT | RISCV_64) #define PPC64 15 +#define M68K 16 +#define M68K_FP (FP_LAYOUT | M68K) #define S390X 17 #define LOONGARCH32 18 #define LOONGARCH64 19 // Floating point register layout. -#define ARCH_LEN (FP_LAYOUT | 0xf) +#define ARCH_LEN (FP_LAYOUT | 0x1f) // See elf.c::elfcore_grok_solaris_note_impl() of binutil's bfd // https://sourceware.org/git/?p=binutils-gdb.git;a=blob;f=bfd/elf.c;h=6ef603010918f14eda69f0d0dc1637b4d51e8157;hb=HEAD#l11777 @@ -116,6 +118,14 @@ #define LOONGARCH64_PR_STATUS_REG_OFFSET 0x70 #define LOONGARCH64_PR_STATUS_REG_OFFSET_SP 24 +// Linux/m68k NT_PRSTATUS uses elf_gregset_t[20] at byte 0x46. The order is +// d1-d7, a0-a6, d0, usp, orig_d0, sr, pc, format/vector. +// https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/m68k/include/asm/elf.h +// https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/m68k/include/asm/user.h +#define M68K_REGS_SIZE (20 * 4) +#define M68K_PR_STATUS_REG_OFFSET 0x46 +#define M68K_PR_STATUS_REG_OFFSET_SP (15 * 4) + // The ones for Linux coredumps. // linux/arch/sparc/include/asm/elf_64.h or elf_32.h // @@ -161,6 +171,12 @@ #define X86_FPREG_OFFSET 0x0 #define X86_64_FPREG_OFFSET 0x0 +// linux/arch/m68k/include/asm/user.h: user_m68kfp_struct has 8 96-bit +// fpregs plus fpcr/fpsr/fpiar. +// https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/m68k/include/asm/user.h +#define M68K_FPREGS_SIZE ((8 * 3 * 4) + (3 * 4)) +#define M68K_FPREG_OFFSET 0x0 + // o6 is the stack pointer. So g0-g7,o0-5 come before it. // Same for OpenBSD and Linux. #define SPARC32_PR_STATUS_REG_OFFSET_SP (4 * 14) @@ -207,6 +223,8 @@ static RzBinElfPrStatusLayout prstatus_layouts[ARCH_LEN] = { [PPC64] = { PPC64_REGS_SIZE, PPC64_PR_STATUS_REG_OFFSET, 64, PPC64_PR_STATUS_REG_OFFSET_SP }, + [M68K] = { M68K_REGS_SIZE, M68K_PR_STATUS_REG_OFFSET, 32, M68K_PR_STATUS_REG_OFFSET_SP }, + [S390X] = { S390X_REGS_SIZE, S390X_PR_STATUS_REG_OFFSET, 64, S390X_PR_STATUS_REG_OFFSET_SP }, [LOONGARCH32] = { LOONGARCH32_REGS_SIZE, LOONGARCH32_PR_STATUS_REG_OFFSET, 32, LOONGARCH32_PR_STATUS_REG_OFFSET_SP }, [LOONGARCH64] = { LOONGARCH64_REGS_SIZE, LOONGARCH64_PR_STATUS_REG_OFFSET, 64, LOONGARCH64_PR_STATUS_REG_OFFSET_SP }, @@ -225,6 +243,7 @@ static RzBinElfPrStatusLayout prstatus_layouts[ARCH_LEN] = { [X86 | FP_LAYOUT] = { X86_FPREGS_SIZE, X86_FPREG_OFFSET, 0, 0 }, [X86_64 | FP_LAYOUT] = { X86_64_FPREGS_SIZE, X86_64_FPREG_OFFSET, 0, 0 }, + [M68K_FP] = { M68K_FPREGS_SIZE, M68K_FPREG_OFFSET, 0, 0 }, }; static bool parse_register_note(ELFOBJ *bin, RzVector /**/ *notes, Elf_(Nhdr) * note_segment_header, ut64 offset, size_t n_type) { @@ -474,6 +493,11 @@ RZ_BORROW RzBinElfPrStatusLayout *Elf_(rz_bin_elf_get_prstatus_layout)(RZ_NONNUL return NULL; case EM_PPC64: return prstatus_layouts + PPC64; + case EM_68K: + if (bin->ehdr.e_ident[EI_CLASS] == ELFCLASS32) { + return prstatus_layouts + M68K; + } + return NULL; case EM_S390: if (bin->ehdr.e_ident[EI_CLASS] == ELFCLASS64) { return prstatus_layouts + S390X; @@ -527,6 +551,14 @@ RZ_BORROW RzBinElfPrStatusLayout *Elf_(rz_bin_elf_get_regset_layout)(RZ_NONNULL return NULL; } break; + case EM_68K: + if (n_type == NT_FPREGSET && bin->ehdr.e_ident[EI_CLASS] == ELFCLASS32) { + off = M68K_FP; + } else { + rz_warn_if_reached(); + return NULL; + } + break; case EM_MIPS: /* fall-thru */ case EM_MIPS_RS3_LE: diff --git a/subprojects/capstone-next.wrap b/subprojects/capstone-next.wrap index 23d4aa77d2..9fe1b3ad3a 100644 --- a/subprojects/capstone-next.wrap +++ b/subprojects/capstone-next.wrap @@ -1,6 +1,6 @@ [wrap-git] url = https://github.com/capstone-engine/capstone.git -revision = 7b1002db6bce9009f2cc5aa6e24380e38a1d51b9 +revision = d4e5fa01626adbd347057c0506c8a5230e8d61ac directory = capstone-next patch_directory = capstone-next depth = 1 diff --git a/test/db/analysis/m68k b/test/db/analysis/m68k index 08e66e9d3e..3d25ff25a8 100644 --- a/test/db/analysis/m68k +++ b/test/db/analysis/m68k @@ -29,7 +29,7 @@ intrp N/A laddr 0x00000000 lang N/A machine Sega Megadrive -maxopsz 4 +maxopsz 22 minopsz 2 os smd cc N/A @@ -139,7 +139,6 @@ a5 = 0x00000000 a6 = 0x00000000 a7 = 0x00000000 pc = 0x00000000 -ccr = 0x00 fp0 = 0x00000000 fp1 = 0x00000000 fp2 = 0x00000000 @@ -151,7 +150,7 @@ fp7 = 0x00000000 fpcr = 0x00000000 fpsr = 0x00000000 fpiar = 0x00000000 -sr = 0x00000000 +sr = 0x0000 sfc = 0x00000000 dfc = 0x00000000 usp = 0x00000000 diff --git a/test/db/asm/m68k_68000_32 b/test/db/asm/m68k_68000_32 new file mode 100644 index 0000000000..1cb63209f1 --- /dev/null +++ b/test/db/asm/m68k_68000_32 @@ -0,0 +1,2 @@ +d "btst.b 0xe8, 0x1aa8(pc)" 083a00e80a54 0x1050 +d "btst.b 0x38, 0x343d(pc, d0.w)" 083b00380039 0x3400 diff --git a/test/db/asm/m68k_68020_32 b/test/db/asm/m68k_68020_32 new file mode 100644 index 0000000000..fdb77ed7f7 --- /dev/null +++ b/test/db/asm/m68k_68020_32 @@ -0,0 +1,3 @@ +d "bftst 0x9c.w{d0:32}" e8f80800009c +d "bftst 0x9c.w{20:5}" e8f80505009c +d "bftst 0x9c.w{d1:d0}" e8f80860009c diff --git a/test/db/asm/m68k_68030_32 b/test/db/asm/m68k_68030_32 new file mode 100644 index 0000000000..fdf4d66a58 --- /dev/null +++ b/test/db/asm/m68k_68030_32 @@ -0,0 +1,13 @@ +d "pmove (a0), tc" f0104000 +d "pmove tc, (a0)" f0104200 +d "pmove (a1), srp" f0114800 +d "pmove (a2), crp" f0124c00 +d "pmove (a0), mmusr" f0106000 +d "pmove (a0), tt0" f0100800 +d "pmove (a0), tt1" f0100c00 +d "pflush sfc, 0x0, (a0)" f0103800 +d "pflusha" f0002400 +d "ploadw sfc, (a0)" f0102000 +d "ploadr sfc, (a0)" f0102200 +d "ptestw sfc, (a0), 0x7" f0109c00 +d "ptestr sfc, (a0), 0x7" f0109e00 diff --git a/test/db/asm/m68k_68060_32 b/test/db/asm/m68k_68060_32 new file mode 100644 index 0000000000..903cb507f2 --- /dev/null +++ b/test/db/asm/m68k_68060_32 @@ -0,0 +1,8 @@ +d "move16 (a0)+, (a1)+" f6209000 +d "halt" 4ac8 +d "pflushn (a0)" f500 +d "pflush (a0)" f508 +d "pflushan" f510 +d "pflusha" f518 +d "plpaw (a0)" f588 +d "plpar (a0)" f5c8 diff --git a/test/db/asm/m68k_cpu32_32 b/test/db/asm/m68k_cpu32_32 new file mode 100644 index 0000000000..adde4a9010 --- /dev/null +++ b/test/db/asm/m68k_cpu32_32 @@ -0,0 +1,7 @@ +d "bgnd" 4afa +d "tblu.w (a0), d0" f8100140 +d "tbls.l (a2), d3" f8123980 +d "tblun.b (a1), d2" f8112500 +d "tblsn.w (a4), d5" f8145d40 +d "tblu.w d1:d2, d3" f8013042 +d "tbls.b d4:d5, d6" f8046805 diff --git a/test/db/cmd/cmd_aL b/test/db/cmd/cmd_aL index bd8f9edbff..bd39308fdb 100644 --- a/test/db/cmd/cmd_aL +++ b/test/db/cmd/cmd_aL @@ -161,6 +161,7 @@ hcs08 Freescale HCS08: 8-bit microcontroller family 68030 Motorola 68030: Enhanced 32-bit microprocessor with integrated MMU 68040 Motorola 68040: High-performance 32-bit microprocessor with integrated FPU 68060 Motorola 68060: 32-bit microprocessor, highest performer in m68k series +cpu32 Motorola CPU32: 32-bit embedded-controller CPU core based on the 68020 baseline Baseline 12-bit instruction set microcontrollers: PIC10Fxxx, PIC12Fxxx, and PIC16Fxxx midrange Mid-Range 14-bit instruction set microcontrollers: PIC10Fxxx, PIC12Fxxx, and PIC16Fxxx highend High-End 16-bit instruction set microcontrollers: PIC18Fxxxx, PIC18FxxJxx, and PIC18FxxKxx diff --git a/test/db/formats/bflt b/test/db/formats/bflt index 251a7bae89..12ce3ba631 100644 --- a/test/db/formats/bflt +++ b/test/db/formats/bflt @@ -310,7 +310,7 @@ intrp N/A laddr 0x00000000 lang N/A machine unknown -maxopsz 4 +maxopsz 22 minopsz 2 os Linux cc N/A diff --git a/test/db/formats/elf/core b/test/db/formats/elf/core index 8aa3288377..358205f03d 100644 --- a/test/db/formats/elf/core +++ b/test/db/formats/elf/core @@ -1111,3 +1111,59 @@ orig_a0 = 0x0000000000000001 pc = 0x0000555555794988 EOF RUN + +NAME=core regs linux m68k +FILE=bins/elf/core/core-linux-m68k +CMDS=<