[RzIL] Update flags on init and step

This commit is contained in:
Florian Märkl 2022-01-13 21:16:31 +01:00 committed by Anton Kochkov
parent f40b5ef545
commit 5be9fa2f0f
4 changed files with 20 additions and 2 deletions

View file

@ -414,7 +414,7 @@ RzAnalysisPlugin rz_analysis_plugin_bf = {
.desc = "brainfuck code analysis plugin",
.license = "LGPL3",
.arch = "bf",
.bits = 8,
.bits = 64, // RzIL emulation of bf and the reg definitions above use 64bit values
.op = &bf_op,
.get_reg_profile = get_reg_profile,
.rzil_init = bf_init_rzil,

View file

@ -37,7 +37,7 @@ static RzBinInfo *info(RzBinFile *bf) {
ret->machine = strdup("brainfuck");
ret->arch = strdup("bf");
ret->has_va = 1;
ret->bits = 32; // 16?
ret->bits = 64; // RzIL emulation of bf uses 64bit values
ret->big_endian = 0;
ret->dbg_info = 0;
/* TODO: move this somewhere else */

View file

@ -417,6 +417,7 @@ RZ_IPI void rz_core_analysis_rzil_reinit(RzCore *core) {
if (core->analysis->rzil) {
// initialize the program counter with the current offset
rz_reg_set_value_by_role(core->analysis->reg, RZ_REG_NAME_PC, core->offset);
rz_core_reg_update_flags(core);
}
}
@ -639,6 +640,7 @@ RZ_IPI void rz_core_rzil_step(RzCore *core) {
RZ_LOG_ERROR("RzIL: stepping failed.\n");
}
rz_il_vm_sync_to_reg(vm, analysis->reg);
rz_core_reg_update_flags(core);
} else {
RZ_LOG_ERROR("RzIL: invalid instruction or lifting not implemented at address 0x%08" PFMT64x "\n", addr);
}

View file

@ -48,6 +48,7 @@ ar pc=0x54
aezs 1
aezv
ar
f @F:registers
EOF
EXPECT=<<EOF
ptr = 0x00010000
@ -58,5 +59,20 @@ pc = 0x00000001
PC: 0x0000000000000055 ptr: 0x0000000000010001
ptr = 0x00010001
pc = 0x00000055
0x00000055 8 pc
0x00010001 8 ptr
EOF
RUN
NAME=aezi pc and flags
FILE=bins/bf/hello-ok.bf
CMDS=<<EOF
s 0x100
aezi
f @F:registers
EOF
EXPECT=<<EOF
0x00000100 8 pc
0x00010000 8 ptr
EOF
RUN