Fix build with capstone v4 and v5 and disable hacks for v6

librz/arch/meson.build

@@ -97,7 +97,6 @@ arch_plugin_sources = [
   'p/arch_ppc_cs.c',
   'p/arch_propeller.c',
   'p/arch_pyc.c',
-  'p/arch_riscv_cs.c',
   'p/arch_rl78.c',
   'p/arch_rsp.c',
   'p/arch_rx.c',
@@ -107,7 +106,6 @@ arch_plugin_sources = [
   'p/arch_spc700.c',
   'p/arch_sysz.c',
   'p/arch_tms320.c',
-  'p/arch_tricore_cs.c',
   'p/arch_v810.c',
   'p/arch_v850.c',
   'p/arch_wasm.c',

librz/arch/p/analysis/analysis_arm_cs.c

@@ -7,7 +7,10 @@
 #include <capstone/capstone.h>
 #include <capstone/arm.h>
 #include <rz_util/rz_assert.h>
-#include "./analysis_arm_hacks.inc"
+
+#if CS_NEXT_VERSION < 6
+#include "analysis_arm_hacks.inc"
+#endif
 
 #include "arm/arm_cs.h"
 #include "arm/arm_accessors32.h"
@@ -15,6 +18,7 @@
 #include "arm/arm_it.h"
 
 #if CS_NEXT_VERSION < 6
+
 inline static const char *ARMCondCodeToString(arm_cc cc) {
 	switch (cc) {
 	default:
@@ -736,6 +740,8 @@ static void anop64(AnalysisArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) {
 		op->family = RZ_ANALYSIS_OP_FAMILY_PRIV;
 	} else if (cs_insn_group(handle, insn, AArch64_FEATURE_HasNEON)) {
 		op->family = RZ_ANALYSIS_OP_FAMILY_MMX;
+	} else if (cs_insn_group(handle, insn, AArch64_FEATURE_HasMTE)) {
+		op->family = RZ_ANALYSIS_OP_FAMILY_SECURITY;
 	} else if (cs_insn_group(handle, insn, AArch64_FEATURE_HasFPARMv8)) {
 		op->family = RZ_ANALYSIS_OP_FAMILY_FPU;
 	} else {
@@ -1035,6 +1041,21 @@ static void anop64(AnalysisArmCSContext *ctx, RzAnalysisOp *op, cs_insn *insn) {
 			op->val = IMM64(1);
 		}
 		break;
+	case CS_AARCH64(_INS_ADDG):
+		op->type = RZ_ANALYSIS_OP_TYPE_ADD;
+		if (ISIMM64(1)) {
+			op->val = IMM64(1);
+		}
+		break;
+	case CS_AARCH64(_INS_IRG):
+		op->type = RZ_ANALYSIS_OP_TYPE_MOV;
+		break;
+	case CS_AARCH64(_INS_SUBG):
+		op->type = RZ_ANALYSIS_OP_TYPE_SUB;
+		if (ISIMM64(1)) {
+			op->val = IMM64(1);
+		}
+		break;
 #endif
 	case CS_AARCH64(_INS_ROR):
 		op->cycles = 1;
@@ -2074,10 +2095,12 @@ static int analysis_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *bu
 			return -1;
 		}
 	}
-	int haa = hackyArmAnal(a, op, buf, len); // TODO: disable this for capstone 5 after testing that everything works
+#if CS_NEXT_VERSION < 6
+	int haa = hackyArmAnalysis(a, op, buf, len);
 	if (haa > 0) {
 		return haa;
 	}
+#endif
 
 	n = cs_disasm(ctx->handle, (ut8 *)buf, RZ_MIN(4, len), addr, 1, &insn);
 	if (n < 1) {

librz/arch/p/analysis/analysis_arm_hacks.inc

@@ -147,7 +147,7 @@ static int hack_handle_br_exc_sys(ut32 insn, RzAnalysisOp *op) {
 	return -1;
 }
 
-static inline int hackyArmAnal(RzAnalysis *a, RzAnalysisOp *op, const ut8 *buf, int len) {
+static inline int hackyArmAnalysis(RzAnalysis *a, RzAnalysisOp *op, const ut8 *buf, int len) {
 	int ret = -1;
 	rz_return_val_if_fail(buf, ret);
 	// Hacky support for ARMv8.3 and ARMv8.5

librz/arch/p/asm/asm_arm_cs.c

@@ -9,7 +9,7 @@
 #include "arm/arm_it.h"
 
 #if CS_NEXT_VERSION < 6
-#include "./asm_arm_hacks.inc"
+#include "asm_arm_hacks.inc"
 #endif
 
 typedef struct asm_arm_cs_context_t {
@@ -19,46 +19,6 @@ typedef struct asm_arm_cs_context_t {
 	int obits;
 } AsmArmCSContext;
 
-#if CS_NEXT_VERSION < 6
-inline static const char *ARMCondCodeToString(arm_cc cc) {
-	switch (cc) {
-	default:
-		rz_warn_if_reached();
-		return "";
-	case ARM_CC_EQ:
-		return "eq";
-	case ARM_CC_NE:
-		return "ne";
-	case ARM_CC_HS:
-		return "hs";
-	case ARM_CC_LO:
-		return "lo";
-	case ARM_CC_MI:
-		return "mi";
-	case ARM_CC_PL:
-		return "pl";
-	case ARM_CC_VS:
-		return "vs";
-	case ARM_CC_VC:
-		return "vc";
-	case ARM_CC_HI:
-		return "hi";
-	case ARM_CC_LS:
-		return "ls";
-	case ARM_CC_GE:
-		return "ge";
-	case ARM_CC_LT:
-		return "lt";
-	case ARM_CC_GT:
-		return "gt";
-	case ARM_CC_LE:
-		return "le";
-	case ARM_CC_AL:
-		return "al";
-	}
-}
-#endif
-
 bool arm64ass(const char *str, ut64 addr, ut32 *op);
 
 static bool check_features(RzAsm *a, cs_insn *insn) {

librz/arch/p/asm/asm_arm_hacks.inc

@@ -1,7 +1,7 @@
 // SPDX-FileCopyrightText: 2020 phakeobj
 // SPDX-License-Identifier: LGPL-3.0-only
 
-static char *hack_handle_dp_imm(ut32 insn) {
+static char *hack_handle_dp_imm_asm(ut32 insn) {
 	char *buf_asm = NULL;
 	char *mnemonic = NULL;
 	const ut8 op0 = (insn >> 23) & 0x7;
@@ -33,7 +33,7 @@ static char *hack_handle_dp_imm(ut32 insn) {
 	return NULL;
 }
 
-static char *hack_handle_br_exc_sys(ut32 insn) {
+static char *hack_handle_br_exc_sys_asm(ut32 insn) {
 	char *buf_asm = NULL;
 	const char *mnemonic = "bti";
 	const ut8 op0 = (insn >> 29) & 0x7;
@@ -64,7 +64,7 @@ static char *hack_handle_br_exc_sys(ut32 insn) {
 	return buf_asm;
 }
 
-static char *hack_handle_dp_reg(ut32 insn) {
+static char *hack_handle_dp_reg_asm(ut32 insn) {
 	char *buf_asm = NULL;
 	char *mnemonic = NULL;
 	const bool op0 = (insn >> 30) & 0x1;
@@ -109,7 +109,7 @@ static char *hack_handle_dp_reg(ut32 insn) {
 	return NULL;
 }
 
-static char *hack_handle_ldst(ut32 insn) {
+static char *hack_handle_ldst_asm(ut32 insn) {
 	char *buf_asm = NULL;
 	char *mnemonic = NULL;
 	bool ignore_imm9 = false;
@@ -231,19 +231,19 @@ static int hackyArmAsm(RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) {
 		case 5:
 		case 13:
 			// irg, subp, gmi, subps
-			buf_asm = hack_handle_dp_reg(insn);
+			buf_asm = hack_handle_dp_reg_asm(insn);
 			break;
 		// Data Processing -- Immediate
 		case 8:
 		case 9:
 			// addg, subg
-			buf_asm = hack_handle_dp_imm(insn);
+			buf_asm = hack_handle_dp_imm_asm(insn);
 			break;
 		// Branches, Exception generating, and System instructions
 		case 10:
 		case 11:
 			// bti
-			buf_asm = hack_handle_br_exc_sys(insn);
+			buf_asm = hack_handle_br_exc_sys_asm(insn);
 			break;
 		// Loads and Stores
 		case 4:
@@ -251,7 +251,7 @@ static int hackyArmAsm(RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) {
 		case 12:
 		case 14:
 			// stg, stzgm, ldg, stzg, st2g, stgm, stz2g, ldgm, stgp
-			buf_asm = hack_handle_ldst(insn);
+			buf_asm = hack_handle_ldst_asm(insn);
 			break;
 		default:
 			break;

test/db/analysis/arm64

@@ -108,7 +108,7 @@ pseudo: asm("irg x8, sp, x8")
 mnemonic: irg
 mask: ffffffff
 prefix: 0
-id: 0
+id: 455
 bytes: e813c89a
 refptr: 0
 size: 4
@@ -125,7 +125,7 @@ pseudo: asm("addg x9, x8, 0x20, 0")
 mnemonic: addg
 mask: ffffffff
 prefix: 0
-id: 0
+id: 6
 bytes: 09018291
 refptr: 0
 size: 4
@@ -156,7 +156,7 @@ pseudo: asm("addg x12, x8, 0x200, 2")
 mnemonic: addg
 mask: ffffffff
 prefix: 0
-id: 0
+id: 6
 bytes: 91a0090c
 refptr: 0
 size: 4
@@ -173,7 +173,7 @@ pseudo: asm("addg x9, x8, 0x20, 0")
 mnemonic: addg
 mask: ffffffff
 prefix: 0
-id: 0
+id: 6
 bytes: 91820109
 refptr: 0
 size: 4
@@ -190,7 +190,7 @@ pseudo: asm("irg x8, sp, x8")
 mnemonic: irg
 mask: ffffffff
 prefix: 0
-id: 0
+id: 455
 bytes: 9ac813e8
 refptr: 0
 size: 4