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Adding tricore support for rz_debug_plugin_gdb (#3557)

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billow 2023-06-06 12:53:51 +08:00 committed by GitHub
parent 0efc031365
commit 6eb14128ad
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GPG key ID: 4AEE18F83AFDEB23
8 changed files with 61 additions and 6 deletions
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4
librz/debug/debug.c
View file

@ -1702,11 +1702,11 @@ RZ_API ut64 rz_debug_get_baddr(RzDebug *dbg, const char *file) {
rz_debug_map_sync(dbg);
char *abspath = rz_sys_pid_to_path(pid);
#if !__WINDOWS__
if (!abspath) {
if (!abspath && file) {
abspath = rz_file_abspath(file);
}
#endif
if (!abspath) {
if (!abspath && file) {
abspath = strdup(file);
}
if (abspath) {

2
librz/debug/p/debug_gdb.c
View file

@ -582,7 +582,7 @@ RzDebugPlugin rz_debug_plugin_gdb = {
.name = "gdb",
/* TODO: Add support for more architectures here */
.license = "LGPL3",
.arch = "x86,arm,sh,mips,avr,lm32,v850,ba2",
.arch = "x86,arm,sh,mips,avr,lm32,v850,ba2,tricore",
.bits = RZ_SYS_BITS_16 | RZ_SYS_BITS_32 | RZ_SYS_BITS_64,
.init = rz_debug_gdb_init,
.fini = rz_debug_gdb_fini,

3
librz/include/rz_types.h
View file

@ -563,7 +563,8 @@ typedef enum {
RZ_SYS_ARCH_HPPA,
RZ_SYS_ARCH_V810,
RZ_SYS_ARCH_LM32,
RZ_SYS_ARCH_RISCV
RZ_SYS_ARCH_RISCV,
RZ_SYS_ARCH_TRICORE,
} RzSysArch;
/* os */

1
librz/util/sys.c
View file

@ -141,6 +141,7 @@ static const struct {
{ "rar", RZ_SYS_ARCH_RAR },
{ "lm32", RZ_SYS_ARCH_LM32 },
{ "v850", RZ_SYS_ARCH_V850 },
{ "tricore", RZ_SYS_ARCH_TRICORE },
{ NULL, 0 }
};

50
subprojects/rzgdb/include/reg/tricore.h Normal file
View file

@ -0,0 +1,50 @@
// SPDX-FileCopyrightText: 2023 billow <billow.fun@gmail.com>
// SPDX-License-Identifier: LGPL-3.0-only
return strdup(
"=PC pc\n"
"=SP sp\n"
"gpr d0 .32 0 0\n"
"gpr d1 .32 4 0\n"
"gpr d2 .32 8 0\n"
"gpr d3 .32 12 0\n"
"gpr d4 .32 16 0\n"
"gpr d5 .32 20 0\n"
"gpr d6 .32 24 0\n"
"gpr d7 .32 28 0\n"
"gpr d8 .32 32 0\n"
"gpr d9 .32 36 0\n"
"gpr d10 .32 40 0\n"
"gpr d11 .32 44 0\n"
"gpr d12 .32 48 0\n"
"gpr d13 .32 52 0\n"
"gpr d14 .32 56 0\n"
"gpr d15 .32 60 0\n"
"gpr a0 .32 64 0\n"
"gpr a1 .32 68 0\n"
"gpr a2 .32 72 0\n"
"gpr a3 .32 76 0\n"
"gpr a4 .32 80 0\n"
"gpr a5 .32 84 0\n"
"gpr a6 .32 88 0\n"
"gpr a7 .32 92 0\n"
"gpr a8 .32 96 0\n"
"gpr a9 .32 100 0\n"
"gpr a10 .32 104 0\n"
"gpr a11 .32 108 0\n"
"gpr a12 .32 112 0\n"
"gpr a13 .32 116 0\n"
"gpr a14 .32 120 0\n"
"gpr a15 .32 124 0\n"
"gpr lcx .32 128 0\n"
"gpr fcx .32 132 0\n"
"gpr pcxi .32 136 0\n"
"gpr psw .32 140 0\n"
"gpr pc .32 144 0\n"
"gpr icr .32 148 0\n"
"gpr isp .32 152 0\n"
"gpr btv .32 156 0\n"
"gpr biv .32 160 0\n"
"gpr syscon .32 164 0\n"
"gpr pmucon0 .32 168 0\n"
"gpr dmucon .32 172 0");

3
subprojects/rzgdb/src/libgdbr.c
View file

@ -118,6 +118,9 @@ char *gdbr_get_reg_profile(int arch, int bits) {
case RZ_SYS_ARCH_V850:
#include "reg/v850.h"
break;
case RZ_SYS_ARCH_TRICORE:
#include "reg/tricore.h"
break;
}
return NULL;
}

2
test/db/archos/linux-x64/cmd_list
View file

@ -36,7 +36,7 @@ EXPECT=<<EOF
{"arch":"bf","name":"bf","license":"LGPL3"}
{"arch":"x86","name":"bochs","license":"LGPL3"}
{"arch":"x86,arm","name":"dmp","license":"LGPL3"}
{"arch":"x86,arm,sh,mips,avr,lm32,v850,ba2","name":"gdb","license":"LGPL3"}
{"arch":"x86,arm,sh,mips,avr,lm32,v850,ba2,tricore","name":"gdb","license":"LGPL3"}
{"arch":"any","name":"io","license":"MIT"}
{"arch":"any","name":"null","license":"MIT"}
{"arch":"any","name":"rap","license":"LGPL3"}

2
test/db/cmd/cmd_list
View file

@ -369,7 +369,7 @@ EXPECT=<<EOF
{"arch":"bf","name":"bf","license":"LGPL3"}
{"arch":"x86","name":"bochs","license":"LGPL3"}
{"arch":"x86,arm","name":"dmp","license":"LGPL3"}
{"arch":"x86,arm,sh,mips,avr,lm32,v850,ba2","name":"gdb","license":"LGPL3"}
{"arch":"x86,arm,sh,mips,avr,lm32,v850,ba2,tricore","name":"gdb","license":"LGPL3"}
{"arch":"any","name":"io","license":"MIT"}
{"arch":"any","name":"null","license":"MIT"}
{"arch":"any","name":"rap","license":"LGPL3"}