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Bump Capstone to latest next (v6-Alpha5 + two fixes). (#5308)

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- Fix LoongArch absolute address usage.
- Sparc: update to use new Auto-Sync module.
- Sparc: Fix unconditional delayed branch instructions with annul bit.
This commit is contained in:
Rot127 2025-08-22 01:29:04 +00:00 committed by GitHub
parent 3374bcb54d
commit 72bf85309b
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
9 changed files with 338 additions and 267 deletions
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8
librz/arch/p/analysis/analysis_loongarch_cs.c
View file

@ -349,11 +349,11 @@ static void loongarch_op_set_type(RzAsmLoongArchContext *ctx, RzAnalysisOp *op)
case LOONGARCH_INS_B:
op->delay = 1;
op->type = RZ_ANALYSIS_OP_TYPE_JMP;
op->jump = op->addr + loongarch_op_as_imm(ctx, 0);
op->jump = loongarch_op_as_imm(ctx, 0);
break;
case LOONGARCH_INS_BL:
op->type = RZ_ANALYSIS_OP_TYPE_CALL;
op->jump = op->addr + loongarch_op_as_imm(ctx, 0);
op->jump = loongarch_op_as_imm(ctx, 0);
op->fail = op->addr + op->size;
op->delay = 1;
break;
@ -364,7 +364,7 @@ static void loongarch_op_set_type(RzAsmLoongArchContext *ctx, RzAnalysisOp *op)
case LOONGARCH_INS_BEQ:
case LOONGARCH_INS_BNE:
op->type = RZ_ANALYSIS_OP_TYPE_CJMP;
op->jump = op->addr + loongarch_op_as_imm(ctx, 2);
op->jump = loongarch_op_as_imm(ctx, 2);
op->fail = op->addr + op->size;
op->delay = 1;
break;
@ -373,7 +373,7 @@ static void loongarch_op_set_type(RzAsmLoongArchContext *ctx, RzAnalysisOp *op)
case LOONGARCH_INS_BEQZ:
case LOONGARCH_INS_BNEZ:
op->type = RZ_ANALYSIS_OP_TYPE_CJMP;
op->jump = op->addr + loongarch_op_as_imm(ctx, 1);
op->jump = loongarch_op_as_imm(ctx, 1);
op->fail = op->addr + op->size;
op->delay = 1;
break;

430
librz/arch/p/analysis/analysis_sparc_cs.c
View file

@ -6,8 +6,27 @@
#include <capstone/capstone.h>
#include <capstone/sparc.h>
#define INSOP(n) insn->detail->sparc.operands[n]
#define INSCC insn->detail->sparc.cc
#define INSDETAIL() insn->detail->sparc
#define INSOP(n) insn->detail->sparc.operands[n]
#if CS_API_MAJOR >= 6
#define INSCC_NORM() (insn->detail->sparc.cc & ~(SPARC_CC_FCC_BEGIN | SPARC_CC_CPCC_BEGIN | SPARC_CC_REG_BEGIN))
#else
#define INSCC_NORM() (insn->detail->sparc.cc)
#endif
#define INSCC_RAW() (insn->detail->sparc.cc)
#define INSHINT() (insn->detail->sparc.hint)
#define IN_64BIT_MODE ((mode & CS_MODE_64) == CS_MODE_64)
#define SPARC_ARCH_BITS (IN_64BIT_MODE ? 64 : 32)
#define SPARC_INSN_SIZE 4
#define SPARC_BYTE (8 * 1)
#define SPARC_HALF_WORD (8 * 2)
#define SPARC_WORD (8 * 4)
#define SPARC_DOUBLE_WORD (8 * 8)
#define SPARC_EXTENDED_WORD (8 * 8)
#define SPARC_QUAD_WORD (8 * 16)
static void opex(RzStrBuf *buf, csh handle, cs_insn *insn) {
int i;
@ -113,16 +132,21 @@ static void op_fillval(RzAnalysis *a, RzAnalysisOp *op, csh handle, cs_insn *ins
static int analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, RzAnalysisOpMask mask) {
RzAnalysisValueSPARC *sparc = (RzAnalysisValueSPARC *)a->plugin_data;
cs_insn *insn;
int mode, n, ret;
int mode = 0;
int n, ret;
if (!a->big_endian) {
return -1;
if (a->big_endian) {
mode = CS_MODE_BIG_ENDIAN;
}
mode = CS_MODE_LITTLE_ENDIAN;
if (!strcmp(a->cpu, "v9")) {
if (RZ_STR_EQ(a->cpu, "v9")) {
mode |= CS_MODE_V9;
}
if (a->bits == 64) {
mode |= CS_MODE_64;
} else {
mode |= CS_MODE_32;
}
if (mode != sparc->omode) {
cs_close(&sparc->handle);
sparc->handle = 0;
@ -133,207 +157,233 @@ static int analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf
if (ret != CS_ERR_OK) {
return -1;
}
#if CS_API_MAJOR >= 6
cs_option(sparc->handle, CS_OPT_DETAIL, CS_OPT_ON | CS_OPT_DETAIL_REAL);
#else
cs_option(sparc->handle, CS_OPT_DETAIL, CS_OPT_ON);
#endif
}
// capstone-next
n = cs_disasm(sparc->handle, (const ut8 *)buf, len, addr, 1, &insn);
if (n < 1) {
op->type = RZ_ANALYSIS_OP_TYPE_ILL;
} else {
if (mask & RZ_ANALYSIS_OP_MASK_OPEX) {
opex(&op->opex, sparc->handle, insn);
}
op->size = insn->size;
op->id = insn->id;
switch (insn->id) {
case SPARC_INS_INVALID:
op->type = RZ_ANALYSIS_OP_TYPE_ILL;
cs_free(insn, n);
return 0;
}
if (mask & RZ_ANALYSIS_OP_MASK_OPEX) {
opex(&op->opex, sparc->handle, insn);
}
op->size = insn->size;
op->id = insn->id;
switch (insn->id) {
case SPARC_INS_INVALID:
op->type = RZ_ANALYSIS_OP_TYPE_ILL;
break;
case SPARC_INS_MOV:
op->type = RZ_ANALYSIS_OP_TYPE_MOV;
break;
case SPARC_INS_RETT:
op->type = RZ_ANALYSIS_OP_TYPE_RET;
op->delay = 1;
break;
case SPARC_INS_UNIMP:
op->type = RZ_ANALYSIS_OP_TYPE_UNK;
break;
case SPARC_INS_CALL:
switch (INSOP(0).type) {
case SPARC_OP_MEM:
// TODO
break;
case SPARC_INS_MOV:
op->type = RZ_ANALYSIS_OP_TYPE_MOV;
break;
case SPARC_INS_RETT:
case SPARC_INS_RET:
case SPARC_INS_RETL:
op->type = RZ_ANALYSIS_OP_TYPE_RET;
case SPARC_OP_REG:
op->type = RZ_ANALYSIS_OP_TYPE_UCALL;
op->delay = 1;
break;
case SPARC_INS_UNIMP:
op->type = RZ_ANALYSIS_OP_TYPE_UNK;
break;
case SPARC_INS_CALL:
switch (INSOP(0).type) {
case SPARC_OP_MEM:
// TODO
break;
case SPARC_OP_REG:
op->type = RZ_ANALYSIS_OP_TYPE_UCALL;
op->delay = 1;
break;
default:
op->type = RZ_ANALYSIS_OP_TYPE_CALL;
op->delay = 1;
op->jump = INSOP(0).imm;
break;
}
break;
case SPARC_INS_NOP:
op->type = RZ_ANALYSIS_OP_TYPE_NOP;
break;
case SPARC_INS_CMP:
op->type = RZ_ANALYSIS_OP_TYPE_CMP;
break;
case SPARC_INS_JMP:
case SPARC_INS_JMPL:
op->type = RZ_ANALYSIS_OP_TYPE_JMP;
default:
op->type = RZ_ANALYSIS_OP_TYPE_CALL;
op->delay = 1;
op->jump = INSOP(0).imm;
break;
case SPARC_INS_LDD:
case SPARC_INS_LD:
case SPARC_INS_LDQ:
case SPARC_INS_LDSB:
case SPARC_INS_LDSH:
case SPARC_INS_LDSW:
case SPARC_INS_LDUB:
case SPARC_INS_LDUH:
case SPARC_INS_LDX:
op->type = RZ_ANALYSIS_OP_TYPE_LOAD;
}
break;
case SPARC_INS_NOP:
op->type = RZ_ANALYSIS_OP_TYPE_NOP;
break;
case SPARC_INS_SUBCC:
#if CS_API_MAJOR >= 6
if (insn->alias_id == SPARC_INS_ALIAS_CMP) {
op->type = RZ_ANALYSIS_OP_TYPE_CMP;
} else {
op->type = RZ_ANALYSIS_OP_TYPE_SUB;
}
#else
op->type = RZ_ANALYSIS_OP_TYPE_SUB;
#endif
break;
case SPARC_INS_JMPL:
op->delay = 1;
#if CS_API_MAJOR >= 6
if (insn->alias_id == SPARC_INS_ALIAS_RET || insn->alias_id == SPARC_INS_ALIAS_RETL) {
op->type = RZ_ANALYSIS_OP_TYPE_RET;
} else if (insn->alias_id == SPARC_INS_ALIAS_CALL) {
op->type = RZ_ANALYSIS_OP_TYPE_CALL;
} else {
op->type = RZ_ANALYSIS_OP_TYPE_UJMP;
}
#else
op->type = RZ_ANALYSIS_OP_TYPE_UJMP;
#endif
break;
#if CS_API_MAJOR >= 6
case SPARC_INS_LDDA:
case SPARC_INS_LDA:
case SPARC_INS_LDQA:
case SPARC_INS_LDSBA:
case SPARC_INS_LDSHA:
case SPARC_INS_LDSWA:
case SPARC_INS_LDUBA:
case SPARC_INS_LDUHA:
case SPARC_INS_LDXA:
#endif
case SPARC_INS_LDD:
case SPARC_INS_LD:
case SPARC_INS_LDQ:
case SPARC_INS_LDSB:
case SPARC_INS_LDSH:
case SPARC_INS_LDSW:
case SPARC_INS_LDUB:
case SPARC_INS_LDUH:
case SPARC_INS_LDX:
op->type = RZ_ANALYSIS_OP_TYPE_LOAD;
break;
#if CS_API_MAJOR >= 6
case SPARC_INS_STBA:
case SPARC_INS_STDA:
case SPARC_INS_STA:
case SPARC_INS_STHA:
case SPARC_INS_STQA:
case SPARC_INS_STXA:
#endif
case SPARC_INS_STBAR:
case SPARC_INS_STB:
case SPARC_INS_STD:
case SPARC_INS_ST:
case SPARC_INS_STH:
case SPARC_INS_STQ:
case SPARC_INS_STX:
op->type = RZ_ANALYSIS_OP_TYPE_STORE;
break;
case SPARC_INS_ORCC:
case SPARC_INS_ORNCC:
case SPARC_INS_ORN:
case SPARC_INS_OR:
op->type = RZ_ANALYSIS_OP_TYPE_OR;
break;
case SPARC_INS_B:
case SPARC_INS_BMASK:
case SPARC_INS_FB: {
// See Table 6-5 in OSA 2015 - Revision: Draft D1.0.0:
bool annul_bit = INSHINT() & SPARC_HINT_A;
op->delay = !(INSCC_NORM() == SPARC_CC_ICC_A && annul_bit);
switch (INSOP(0).type) {
default:
case SPARC_OP_REG:
op->type = RZ_ANALYSIS_OP_TYPE_UJMP;
break;
case SPARC_INS_STBAR:
case SPARC_INS_STB:
case SPARC_INS_STD:
case SPARC_INS_ST:
case SPARC_INS_STH:
case SPARC_INS_STQ:
case SPARC_INS_STX:
op->type = RZ_ANALYSIS_OP_TYPE_STORE;
break;
case SPARC_INS_ORCC:
case SPARC_INS_ORNCC:
case SPARC_INS_ORN:
case SPARC_INS_OR:
op->type = RZ_ANALYSIS_OP_TYPE_OR;
break;
case SPARC_INS_B:
case SPARC_INS_BMASK:
case SPARC_INS_BRGEZ:
case SPARC_INS_BRGZ:
case SPARC_INS_BRLEZ:
case SPARC_INS_BRLZ:
case SPARC_INS_BRNZ:
case SPARC_INS_BRZ:
case SPARC_INS_FB:
switch (INSOP(0).type) {
case SPARC_OP_REG:
if (INSCC != SPARC_CC_ICC_N) { // never
op->jump = INSOP(1).imm;
}
if (INSCC != SPARC_CC_ICC_A) { // always
op->fail = addr + 8;
op->delay = 1;
op->type = RZ_ANALYSIS_OP_TYPE_CJMP;
} else {
op->type = RZ_ANALYSIS_OP_TYPE_JMP;
}
break;
case SPARC_OP_IMM:
if (INSCC != SPARC_CC_ICC_N) { // never
op->jump = INSOP(0).imm;
}
if (INSCC != SPARC_CC_ICC_A) { // always
op->fail = addr + 8;
op->delay = 1;
op->type = RZ_ANALYSIS_OP_TYPE_CJMP;
} else {
op->type = RZ_ANALYSIS_OP_TYPE_JMP;
}
break;
default:
// MEM?
break;
case SPARC_OP_IMM:
op->type = RZ_ANALYSIS_OP_TYPE_JMP;
if (INSCC_NORM() != SPARC_CC_ICC_N) { // never
op->jump = INSOP(0).imm;
}
break;
case SPARC_INS_FHSUBD:
case SPARC_INS_FHSUBS:
case SPARC_INS_FPSUB16:
case SPARC_INS_FPSUB16S:
case SPARC_INS_FPSUB32:
case SPARC_INS_FPSUB32S:
case SPARC_INS_FSUBD:
case SPARC_INS_FSUBQ:
case SPARC_INS_FSUBS:
case SPARC_INS_SUBCC:
case SPARC_INS_SUBX:
case SPARC_INS_SUBXCC:
case SPARC_INS_SUB:
case SPARC_INS_TSUBCCTV:
case SPARC_INS_TSUBCC:
op->type = RZ_ANALYSIS_OP_TYPE_SUB;
break;
case SPARC_INS_ADDCC:
case SPARC_INS_ADDX:
case SPARC_INS_ADDXCC:
case SPARC_INS_ADDXC:
case SPARC_INS_ADDXCCC:
case SPARC_INS_ADD:
case SPARC_INS_FADDD:
case SPARC_INS_FADDQ:
case SPARC_INS_FADDS:
case SPARC_INS_FHADDD:
case SPARC_INS_FHADDS:
case SPARC_INS_FNADDD:
case SPARC_INS_FNADDS:
case SPARC_INS_FNHADDD:
case SPARC_INS_FNHADDS:
case SPARC_INS_FPADD16:
case SPARC_INS_FPADD16S:
case SPARC_INS_FPADD32:
case SPARC_INS_FPADD32S:
case SPARC_INS_FPADD64:
case SPARC_INS_TADDCCTV:
case SPARC_INS_TADDCC:
op->type = RZ_ANALYSIS_OP_TYPE_ADD;
break;
case SPARC_INS_FDMULQ:
case SPARC_INS_FMUL8SUX16:
case SPARC_INS_FMUL8ULX16:
case SPARC_INS_FMUL8X16:
case SPARC_INS_FMUL8X16AL:
case SPARC_INS_FMUL8X16AU:
case SPARC_INS_FMULD:
case SPARC_INS_FMULD8SUX16:
case SPARC_INS_FMULD8ULX16:
case SPARC_INS_FMULQ:
case SPARC_INS_FMULS:
case SPARC_INS_FSMULD:
case SPARC_INS_MULX:
case SPARC_INS_SMULCC:
case SPARC_INS_SMUL:
case SPARC_INS_UMULCC:
case SPARC_INS_UMULXHI:
case SPARC_INS_UMUL:
case SPARC_INS_XMULX:
case SPARC_INS_XMULXHI:
op->type = RZ_ANALYSIS_OP_TYPE_MUL;
break;
case SPARC_INS_FDIVD:
case SPARC_INS_FDIVQ:
case SPARC_INS_FDIVS:
case SPARC_INS_SDIVCC:
case SPARC_INS_SDIVX:
case SPARC_INS_SDIV:
case SPARC_INS_UDIVCC:
case SPARC_INS_UDIVX:
case SPARC_INS_UDIV:
op->type = RZ_ANALYSIS_OP_TYPE_DIV;
break;
}
if (mask & RZ_ANALYSIS_OP_MASK_VAL) {
op_fillval(a, op, sparc->handle, insn);
if (INSCC_NORM() != SPARC_CC_ICC_A) {
// Conditional branches and BN
if (INSCC_NORM() != SPARC_CC_ICC_N) {
op->type |= RZ_ANALYSIS_OP_TYPE_COND;
}
op->fail = addr + 8;
}
cs_free(insn, n);
// BA and BA,a don't set fail
break;
}
case SPARC_INS_FHSUBD:
case SPARC_INS_FHSUBS:
case SPARC_INS_FPSUB16:
case SPARC_INS_FPSUB16S:
case SPARC_INS_FPSUB32:
case SPARC_INS_FPSUB32S:
case SPARC_INS_FSUBD:
case SPARC_INS_FSUBQ:
case SPARC_INS_FSUBS:
case SPARC_INS_SUBX:
case SPARC_INS_SUBXCC:
case SPARC_INS_SUB:
case SPARC_INS_TSUBCCTV:
case SPARC_INS_TSUBCC:
op->type = RZ_ANALYSIS_OP_TYPE_SUB;
break;
case SPARC_INS_ADDCC:
case SPARC_INS_ADDX:
case SPARC_INS_ADDXCC:
case SPARC_INS_ADDXC:
case SPARC_INS_ADDXCCC:
case SPARC_INS_ADD:
case SPARC_INS_FADDD:
case SPARC_INS_FADDQ:
case SPARC_INS_FADDS:
case SPARC_INS_FHADDD:
case SPARC_INS_FHADDS:
case SPARC_INS_FNADDD:
case SPARC_INS_FNADDS:
case SPARC_INS_FNHADDD:
case SPARC_INS_FNHADDS:
case SPARC_INS_FPADD16:
case SPARC_INS_FPADD16S:
case SPARC_INS_FPADD32:
case SPARC_INS_FPADD32S:
case SPARC_INS_FPADD64:
case SPARC_INS_TADDCCTV:
case SPARC_INS_TADDCC:
op->type = RZ_ANALYSIS_OP_TYPE_ADD;
break;
case SPARC_INS_FDMULQ:
case SPARC_INS_FMUL8SUX16:
case SPARC_INS_FMUL8ULX16:
case SPARC_INS_FMUL8X16:
case SPARC_INS_FMUL8X16AL:
case SPARC_INS_FMUL8X16AU:
case SPARC_INS_FMULD:
case SPARC_INS_FMULD8SUX16:
case SPARC_INS_FMULD8ULX16:
case SPARC_INS_FMULQ:
case SPARC_INS_FMULS:
case SPARC_INS_FSMULD:
case SPARC_INS_MULX:
case SPARC_INS_SMULCC:
case SPARC_INS_SMUL:
case SPARC_INS_UMULCC:
case SPARC_INS_UMULXHI:
case SPARC_INS_UMUL:
case SPARC_INS_XMULX:
case SPARC_INS_XMULXHI:
op->type = RZ_ANALYSIS_OP_TYPE_MUL;
break;
case SPARC_INS_FDIVD:
case SPARC_INS_FDIVQ:
case SPARC_INS_FDIVS:
case SPARC_INS_SDIVCC:
case SPARC_INS_SDIVX:
case SPARC_INS_SDIV:
case SPARC_INS_UDIVCC:
case SPARC_INS_UDIVX:
case SPARC_INS_UDIV:
op->type = RZ_ANALYSIS_OP_TYPE_DIV;
break;
}
if (mask & RZ_ANALYSIS_OP_MASK_VAL) {
op_fillval(a, op, sparc->handle, insn);
}
cs_free(insn, n);
return op->size;
}

15
librz/arch/p/asm/asm_sparc_cs.c
View file

@ -12,10 +12,17 @@ static int sparc_disassemble(RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) {
cs_insn *insn;
int n = -1, ret = -1;
int mode = CS_MODE_BIG_ENDIAN;
int mode = 0;
if (a->big_endian) {
mode = CS_MODE_BIG_ENDIAN;
}
if (a->cpu && *a->cpu) {
if (!strcmp(a->cpu, "v9")) {
mode |= CS_MODE_V9;
if (RZ_STR_EQ(a->cpu, "v9")) {
mode |= CS_MODE_V9 | CS_MODE_64;
} else if (a->bits == 64) {
mode |= CS_MODE_64;
} else {
mode |= CS_MODE_32;
}
}
if (op) {
@ -78,7 +85,7 @@ RzAsmPlugin rz_asm_plugin_sparc_cs = {
.desc = "Sun SPARC Capstone-based disassembler",
.license = "BSD",
.arch = "sparc",
.cpus = "v9",
.cpus = "v9,v8",
.bits = 32 | 64,
.endian = RZ_SYS_ENDIAN_BIG | RZ_SYS_ENDIAN_LITTLE,
.init = sparc_asm_init,

2
subprojects/capstone-next.wrap
View file

@ -1,6 +1,6 @@
[wrap-git]
url = https://github.com/capstone-engine/capstone.git
revision = 42fbce6c524a3a57748f9de2b5460a7135e236c1
revision = 9539045d675a30eed43869325f7f51cfc26de0b7
directory = capstone-next
patch_directory = capstone-next
depth = 1

10
subprojects/capstone-v6.wrap
View file

@ -1,6 +1,6 @@
[wrap-file]
source_url = https://github.com/capstone-engine/capstone/releases/download/6.0.0-Alpha4/capstone-6.0.0-Alpha4.tar.xz
source_filename = capstone-6.0.0-Alpha4.tar.xz
source_hash = 1a4680fac134673c1dfbadace262d7ecdd1e1b813d39a5ca737f1f6e0d11689f
directory = capstone-6.0.0-Alpha4
patch_directory = capstone-6.0.0-alpha4
source_url = https://github.com/capstone-engine/capstone/releases/download/6.0.0-Alpha5/capstone-6.0.0-Alpha5.tar.xz
source_filename = capstone-6.0.0-Alpha5.tar.xz
source_hash = 51de69e20154d500ea7b7fc161108069ad1812aba7b23e28eb7e5e6ef75c662f
directory = capstone-6.0.0-Alpha5
patch_directory = capstone-6.0.0-alpha5

27
subprojects/packagefiles/capstone-6.0.0-alpha4/meson.build → subprojects/packagefiles/capstone-6.0.0-alpha5/meson.build
View file

@ -36,6 +36,11 @@ cs_files = [
'arch/HPPA/HPPAInstPrinter.c',
'arch/HPPA/HPPAMapping.c',
'arch/HPPA/HPPAModule.c',
'arch/LoongArch/LoongArchInstPrinter.c',
'arch/LoongArch/LoongArchDisassembler.c',
'arch/LoongArch/LoongArchMapping.c',
'arch/LoongArch/LoongArchDisassemblerExtension.c',
'arch/LoongArch/LoongArchModule.c',
'arch/M680X/M680XDisassembler.c',
'arch/M680X/M680XInstPrinter.c',
'arch/M680X/M680XModule.c',
@ -51,15 +56,16 @@ cs_files = [
'arch/PowerPC/PPCMapping.c',
'arch/PowerPC/PPCModule.c',
'arch/Sparc/SparcDisassembler.c',
'arch/Sparc/SparcDisassemblerExtension.c',
'arch/Sparc/SparcInstPrinter.c',
'arch/Sparc/SparcMapping.c',
'arch/Sparc/SparcModule.c',
'arch/SystemZ/SystemZInstPrinter.c',
'arch/SystemZ/SystemZModule.c',
'arch/SystemZ/SystemZMapping.c',
'arch/SystemZ/SystemZDisassemblerExtension.c',
'arch/SystemZ/SystemZMCTargetDesc.c',
'arch/SystemZ/SystemZDisassembler.c',
'arch/SystemZ/SystemZInstPrinter.c',
'arch/SystemZ/SystemZMapping.c',
'arch/SystemZ/SystemZMCTargetDesc.c',
'arch/SystemZ/SystemZModule.c',
'arch/TMS320C64x/TMS320C64xDisassembler.c',
'arch/TMS320C64x/TMS320C64xInstPrinter.c',
'arch/TMS320C64x/TMS320C64xMapping.c',
@ -79,6 +85,10 @@ cs_files = [
'arch/TriCore/TriCoreInstPrinter.c',
'arch/TriCore/TriCoreMapping.c',
'arch/TriCore/TriCoreModule.c',
'arch/Xtensa/XtensaDisassembler.c',
'arch/Xtensa/XtensaInstPrinter.c',
'arch/Xtensa/XtensaMapping.c',
'arch/Xtensa/XtensaModule.c',
'cs.c',
'Mapping.c',
'MCInst.c',
@ -96,20 +106,23 @@ libcapstone_c_args = [
'-DCAPSTONE_X86_REDUCE_NO',
'-DCAPSTONE_USE_SYS_DYN_MEM',
'-DCAPSTONE_DIET_NO',
'-DCAPSTONE_HAS_AARCH64',
'-DCAPSTONE_HAS_ARC',
'-DCAPSTONE_HAS_ALPHA',
'-DCAPSTONE_HAS_ARM',
'-DCAPSTONE_HAS_AARCH64',
'-DCAPSTONE_HAS_HPPA',
'-DCAPSTONE_HAS_M68K',
'-DCAPSTONE_HAS_LOONGARCH',
'-DCAPSTONE_HAS_M680X',
'-DCAPSTONE_HAS_M68K',
'-DCAPSTONE_HAS_MIPS',
'-DCAPSTONE_HAS_POWERPC',
'-DCAPSTONE_HAS_SPARC',
'-DCAPSTONE_HAS_SYSTEMZ',
'-DCAPSTONE_HAS_XCORE',
'-DCAPSTONE_HAS_TMS320C64X',
'-DCAPSTONE_HAS_TRICORE',
'-DCAPSTONE_HAS_X86',
'-DCAPSTONE_HAS_XCORE',
'-DCAPSTONE_HAS_XTENSA',
]
if meson.get_compiler('c').has_argument('-Wmaybe-uninitialized')

1
subprojects/packagefiles/capstone-next/meson.build
View file

@ -56,6 +56,7 @@ cs_files = [
'arch/PowerPC/PPCMapping.c',
'arch/PowerPC/PPCModule.c',
'arch/Sparc/SparcDisassembler.c',
'arch/Sparc/SparcDisassemblerExtension.c',
'arch/Sparc/SparcInstPrinter.c',
'arch/Sparc/SparcMapping.c',
'arch/Sparc/SparcModule.c',

2
test/db/analysis/loongarch
View file

@ -120,7 +120,7 @@ bits 64
| 0x0001029c jirl ra, t0, 0
| 0x000102a0 ld.d t1, sp, 8
| 0x000102a4 ldptr.d t0, s1, 0
| ,=< 0x000102a8 bne t1, t0, 0x1c
| ,=< 0x000102a8 bne t1, t0, 0x102c4
| | 0x000102ac ld.d ra, sp, 0x28
| | 0x000102b0 ld.d s0, sp, 0x20
| | 0x000102b4 ld.d s1, sp, 0x18

110
test/db/analysis/sparc
View file

@ -174,7 +174,7 @@ EXPECT=<<EOF
0x0002b938 1 8 root.0002b938
0x0002bca4 1 8 root.0002bca4
0x0002c05c 1 8 root.0002c05c
0x0002c880 1 16 root.0002c880
0x0002c880 1 72 root.0002c880
0x0003f9b0 1 8 root.0003f9b0
0x0003f9bc 1 8 root.0003f9bc
0x0003f9c8 1 8 root.0003f9c8
@ -230,7 +230,7 @@ EXPECT=<<EOF
0x0002c108 0x0002c118 00:0000 16 j 0x0002c570 f 0x0002c118
0x0002c118 0x0002c128 00:0000 16 j 0x0002c58c f 0x0002c128
0x0002c128 0x0002c12c 00:0000 4 j 0x0002c12c
0x0002c12c 0x0002c138 00:0000 12 j 0x0002c14c
0x0002c12c 0x0002c13c 00:0000 16 j 0x0002c14c
0x0002c13c 0x0002c14c 00:0000 16 j 0x0002c58c f 0x0002c14c
0x0002c14c 0x0002c15c 00:0000 16 j 0x0002c13c f 0x0002c15c
0x0002c15c 0x0002c174 00:0000 24 j 0x0002c13c f 0x0002c174
@ -246,7 +246,7 @@ EXPECT=<<EOF
0x0002c228 0x0002c244 00:0000 28 j 0x0002d2f0 f 0x0002c244
0x0002c244 0x0002c25c 00:0000 24 j 0x0002c384 f 0x0002c25c
0x0002c25c 0x0002c284 00:0000 40 j 0x0002c380 f 0x0002c284
0x0002c284 0x0002c2b4 00:0000 48 j 0x0002c340
0x0002c284 0x0002c2b8 00:0000 52 j 0x0002c340
0x0002c2b8 0x0002c2c0 00:0000 8 j 0x0002c2c0
0x0002c2c0 0x0002c2e0 00:0000 32 j 0x0002c2e0
0x0002c2e0 0x0002c2f4 00:0000 20 j 0x0002c66c f 0x0002c2f4
@ -279,7 +279,7 @@ EXPECT=<<EOF
0x0002c4c4 0x0002c4c8 00:0000 4 j 0x0002c4c8
0x0002c4c8 0x0002c4d8 00:0000 16 j 0x0002c83c f 0x0002c4d8
0x0002c4d8 0x0002c4e8 00:0000 16 j 0x0002c81c f 0x0002c4e8
0x0002c4e8 0x0002c4f4 00:0000 12 j 0x0002c50c
0x0002c4e8 0x0002c4f8 00:0000 16 j 0x0002c50c
0x0002c4f8 0x0002c508 00:0000 16 j 0x0002c814 f 0x0002c508
0x0002c508 0x0002c50c 00:0000 4 j 0x0002c50c
0x0002c50c 0x0002c534 00:0000 40 j 0x0002c4f8 f 0x0002c534
@ -287,23 +287,23 @@ EXPECT=<<EOF
0x0002c53c 0x0002c550 00:0000 20 j 0x0002bfdc f 0x0002c550
0x0002c550 0x0002c560 00:0000 16 j 0x0002bed8 f 0x0002c560
0x0002c560 0x0002c564 00:0000 4 j 0x0002c564
0x0002c564 0x0002c56c 00:0000 8 j 0x0002bed4
0x0002c564 0x0002c570 00:0000 12 j 0x0002bed4
0x0002c570 0x0002c580 00:0000 16 j 0x0002c118 f 0x0002c580
0x0002c580 0x0002c58c 00:0000 12 j 0x0002c12c f 0x0002c58c
0x0002c58c 0x0002c598 00:0000 12 j 0x0002c200 f 0x0002c598
0x0002c598 0x0002c5c0 00:0000 40 j 0x0002d290
0x0002c5c4 0x0002c5d8 00:0000 20 j 0x0002c1b8
0x0002c598 0x0002c5c4 00:0000 44 j 0x0002d290
0x0002c5c4 0x0002c5dc 00:0000 24 j 0x0002c1b8
0x0002c5dc 0x0002c60c 00:0000 48 j 0x0002bdec f 0x0002c60c
0x0002c60c 0x0002c610 00:0000 4 j 0x0002caf4
0x0002c60c 0x0002c614 00:0000 8 j 0x0002caf4
0x0002c614 0x0002c61c 00:0000 8 j 0x0002c0a4 f 0x0002c61c
0x0002c61c 0x0002c62c 00:0000 16 j 0x0002c098 f 0x0002c62c
0x0002c62c 0x0002c630 00:0000 4 j 0x0002c0a4
0x0002c62c 0x0002c634 00:0000 8 j 0x0002c0a4
0x0002c634 0x0002c644 00:0000 16
0x0002c644 0x0002c650 00:0000 12 j 0x0002cd58 f 0x0002c650
0x0002c650 0x0002c668 00:0000 24 j 0x0002c014
0x0002c650 0x0002c66c 00:0000 28 j 0x0002c014
0x0002c66c 0x0002c67c 00:0000 16 j 0x0002c69c f 0x0002c67c
0x0002c67c 0x0002c694 00:0000 24 j 0x0002d26c f 0x0002c694
0x0002c694 0x0002c698 00:0000 4 j 0x0002c2e0
0x0002c694 0x0002c69c 00:0000 8 j 0x0002c2e0
0x0002c69c 0x0002c6a8 00:0000 12
0x0002c78c 0x0002c7a4 00:0000 24
0x0002c7a4 0x0002c7c4 00:0000 32 j 0x0002c028 f 0x0002c7c4
@ -311,8 +311,8 @@ EXPECT=<<EOF
0x0002c7c8 0x0002c7d4 00:0000 12 j 0x0002cbbc f 0x0002c7d4
0x0002c7d4 0x0002c7e8 00:0000 20 j 0x0002c028 f 0x0002c7e8
0x0002c7e8 0x0002c7f8 00:0000 16 j 0x0002c028 f 0x0002c7f8
0x0002c7f8 0x0002c808 00:0000 16 j 0x0002c028
0x0002c80c 0x0002c810 00:0000 4 j 0x0002c200
0x0002c7f8 0x0002c80c 00:0000 20 j 0x0002c028
0x0002c80c 0x0002c814 00:0000 8 j 0x0002c200
0x0002c814 0x0002c81c 00:0000 8 j 0x0002c81c
0x0002c81c 0x0002c83c 00:0000 32 j 0x0002c83c
0x0002c83c 0x0002c868 00:0000 44 j 0x0002cbfc f 0x0002c868
@ -334,27 +334,27 @@ EXPECT=<<EOF
0x0002c9e0 0x0002ca14 00:0000 52 j 0x0002ca14
0x0002ca14 0x0002ca38 00:0000 36 j 0x0002ca38
0x0002ca38 0x0002ca48 00:0000 16 j 0x0002c3e8 f 0x0002ca48
0x0002ca48 0x0002ca4c 00:0000 4 j 0x0002c3dc
0x0002ca50 0x0002ca54 00:0000 4 j 0x0002c3a8
0x0002ca48 0x0002ca50 00:0000 8 j 0x0002c3dc
0x0002ca50 0x0002ca58 00:0000 8 j 0x0002c3a8
0x0002ca58 0x0002ca68 00:0000 16 j 0x0002c480 f 0x0002ca68
0x0002ca68 0x0002ca7c 00:0000 20 j 0x0002ca8c f 0x0002ca7c
0x0002ca7c 0x0002ca8c 00:0000 16 j 0x0002c480 f 0x0002ca8c
0x0002ca8c 0x0002caac 00:0000 32 j 0x0002c480 f 0x0002caac
0x0002caac 0x0002cac8 00:0000 28 j 0x0002c480 f 0x0002cac8
0x0002cac8 0x0002cae8 00:0000 32 j 0x0002c488
0x0002caec 0x0002caf0 00:0000 4 j 0x0002c030
0x0002cac8 0x0002caec 00:0000 36 j 0x0002c488
0x0002caec 0x0002caf4 00:0000 8 j 0x0002c030
0x0002caf4 0x0002cb08 00:0000 20 j 0x0002bdec f 0x0002cb08
0x0002cb08 0x0002cb0c 00:0000 4 j 0x0002bdf8
0x0002cb10 0x0002cb24 00:0000 20 j 0x0002c910
0x0002cb08 0x0002cb10 00:0000 8 j 0x0002bdf8
0x0002cb10 0x0002cb28 00:0000 24 j 0x0002c910
0x0002cb28 0x0002cb2c 00:0000 4 j 0x0002cb2c
0x0002cb2c 0x0002cb40 00:0000 20 j 0x0002cb2c f 0x0002cb40
0x0002cb40 0x0002cb44 00:0000 4 j 0x0002c4b4
0x0002cb40 0x0002cb48 00:0000 8 j 0x0002c4b4
0x0002cb48 0x0002cb58 00:0000 16 j 0x0002c410 f 0x0002cb58
0x0002cb58 0x0002cb64 00:0000 12 j 0x0002c410
0x0002cb98 0x0002cbb8 00:0000 32 j 0x0002c4c8
0x0002cb58 0x0002cb68 00:0000 16 j 0x0002c410
0x0002cb98 0x0002cbbc 00:0000 36 j 0x0002c4c8
0x0002cbbc 0x0002cbcc 00:0000 16 j 0x0002c028 f 0x0002cbcc
0x0002cbcc 0x0002cbf4 00:0000 40 j 0x0002c028 f 0x0002cbf4
0x0002cbf4 0x0002cbf8 00:0000 4 j 0x0002c7d4
0x0002cbf4 0x0002cbfc 00:0000 8 j 0x0002c7d4
0x0002cbfc 0x0002cc20 00:0000 36 j 0x0002cc30 f 0x0002cc20
0x0002cc20 0x0002cc30 00:0000 16 j 0x0002ccb4 f 0x0002cc30
0x0002cc30 0x0002cc34 00:0000 4 j 0x0002cc34
@ -366,17 +366,17 @@ EXPECT=<<EOF
0x0002cc7c 0x0002cc8c 00:0000 16 j 0x0002cd10 f 0x0002cc8c
0x0002cc8c 0x0002cc90 00:0000 4 j 0x0002cc90
0x0002cc90 0x0002cca4 00:0000 20 j 0x0002c868 f 0x0002cca4
0x0002cca4 0x0002ccb0 00:0000 12 j 0x0002c868
0x0002ccb4 0x0002ccc8 00:0000 20 j 0x0002cc34
0x0002cca4 0x0002ccb4 00:0000 16 j 0x0002c868
0x0002ccb4 0x0002cccc 00:0000 24 j 0x0002cc34
0x0002cccc 0x0002ccd8 00:0000 12 j 0x0002cc60 f 0x0002ccd8
0x0002ccd8 0x0002cce8 00:0000 16 j 0x0002cc60 f 0x0002cce8
0x0002cce8 0x0002cd04 00:0000 28 j 0x0002cc60 f 0x0002cd04
0x0002cd04 0x0002cd0c 00:0000 8 j 0x0002cc64
0x0002cd04 0x0002cd10 00:0000 12 j 0x0002cc64
0x0002cd10 0x0002cd2c 00:0000 28 j 0x0002cc90 f 0x0002cd2c
0x0002cd2c 0x0002cd38 00:0000 12 j 0x0002cc90 f 0x0002cd38
0x0002cd38 0x0002cd50 00:0000 24 j 0x0002cc90 f 0x0002cd50
0x0002cd50 0x0002cd54 00:0000 4 j 0x0002cc90
0x0002cd58 0x0002cd5c 00:0000 4 j 0x0002c650
0x0002cd50 0x0002cd58 00:0000 8 j 0x0002cc90
0x0002cd58 0x0002cd60 00:0000 8 j 0x0002c650
0x0002cd60 0x0002cd74 00:0000 20 j 0x0002cd84 f 0x0002cd74
0x0002cd74 0x0002cd84 00:0000 16 j 0x0002d324 f 0x0002cd84
0x0002cd84 0x0002cd98 00:0000 20 j 0x0002ceb0 f 0x0002cd98
@ -391,15 +391,15 @@ EXPECT=<<EOF
0x0002ce38 0x0002ce48 00:0000 16 j 0x0002cee4 f 0x0002ce48
0x0002ce48 0x0002ce58 00:0000 16 j 0x0002ce58
0x0002ce58 0x0002ce60 00:0000 8 j 0x0002ce60
0x0002ce60 0x0002ce70 00:0000 16 j 0x0002c99c
0x0002ce74 0x0002ce94 00:0000 32 j 0x0002c968
0x0002ce98 0x0002ceac 00:0000 20 j 0x0002cde4
0x0002ce60 0x0002ce74 00:0000 20 j 0x0002c99c
0x0002ce74 0x0002ce98 00:0000 36 j 0x0002c968
0x0002ce98 0x0002ceb0 00:0000 24 j 0x0002cde4
0x0002ceb0 0x0002cec4 00:0000 20 j 0x0002cec4
0x0002cec4 0x0002ced4 00:0000 16 j 0x0002cd98 f 0x0002ced4
0x0002ced4 0x0002cee0 00:0000 12 j 0x0002cdb0
0x0002ced4 0x0002cee4 00:0000 16 j 0x0002cdb0
0x0002cee4 0x0002cf10 00:0000 44 j 0x0002cf24 f 0x0002cf10
0x0002cf10 0x0002cf24 00:0000 20 j 0x0002d394 f 0x0002cf24
0x0002cf24 0x0002cf30 00:0000 12 j 0x0002ce48
0x0002cf24 0x0002cf34 00:0000 16 j 0x0002ce48
0x0002cf34 0x0002cf4c 00:0000 24 j 0x0002d108 f 0x0002cf4c
0x0002cf4c 0x0002cf60 00:0000 20 j 0x0002cf60
0x0002cf60 0x0002cf6c 00:0000 12 j 0x0002d1a0 f 0x0002cf6c
@ -414,7 +414,7 @@ EXPECT=<<EOF
0x0002d008 0x0002d01c 00:0000 20 j 0x0002d030 f 0x0002d01c
0x0002d01c 0x0002d030 00:0000 20 j 0x0002d030
0x0002d030 0x0002d034 00:0000 4 j 0x0002d034
0x0002d034 0x0002d040 00:0000 12 j 0x0002c950
0x0002d034 0x0002d044 00:0000 16 j 0x0002c950
0x0002d044 0x0002d04c 00:0000 8 j 0x0002d220 f 0x0002d04c
0x0002d04c 0x0002d060 00:0000 20 j 0x0002d090 f 0x0002d060
0x0002d060 0x0002d06c 00:0000 12 j 0x0002d094 f 0x0002d06c
@ -424,8 +424,8 @@ EXPECT=<<EOF
0x0002d094 0x0002d0a0 00:0000 12 j 0x0002d22c f 0x0002d0a0
0x0002d0a0 0x0002d0b4 00:0000 20 j 0x0002d0d0 f 0x0002d0b4
0x0002d0b4 0x0002d0d0 00:0000 28 j 0x0002d0d0
0x0002d0d0 0x0002d0dc 00:0000 12 j 0x0002d034
0x0002d0e0 0x0002d104 00:0000 36 j 0x0002c534
0x0002d0d0 0x0002d0e0 00:0000 16 j 0x0002d034
0x0002d0e0 0x0002d108 00:0000 40 j 0x0002c534
0x0002d108 0x0002d11c 00:0000 20 j 0x0002d190 f 0x0002d11c
0x0002d11c 0x0002d12c 00:0000 16 j 0x0002cf6c f 0x0002d12c
0x0002d12c 0x0002d140 00:0000 20 j 0x0002d1a0 f 0x0002d140
@ -435,44 +435,44 @@ EXPECT=<<EOF
0x0002d16c 0x0002d17c 00:0000 16 j 0x0002d408 f 0x0002d17c
0x0002d17c 0x0002d180 00:0000 4 j 0x0002d180
0x0002d180 0x0002d190 00:0000 16 j 0x0002cf4c f 0x0002d190
0x0002d190 0x0002d198 00:0000 8 j 0x0002cf60
0x0002d190 0x0002d19c 00:0000 12 j 0x0002cf60
0x0002d19c 0x0002d1a0 00:0000 4 j 0x0002d1a0
0x0002d1a0 0x0002d1a8 00:0000 8 j 0x0002cfa4
0x0002d1a0 0x0002d1ac 00:0000 12 j 0x0002cfa4
0x0002d1ac 0x0002d1d0 00:0000 36 j 0x0002d20c f 0x0002d1d0
0x0002d1d0 0x0002d1ec 00:0000 28 j 0x0002d090 f 0x0002d1ec
0x0002d1ec 0x0002d208 00:0000 28 j 0x0002d090 f 0x0002d208
0x0002d208 0x0002d20c 00:0000 4 j 0x0002d20c
0x0002d20c 0x0002d21c 00:0000 16 j 0x0002d090
0x0002d20c 0x0002d220 00:0000 20 j 0x0002d090
0x0002d220 0x0002d228 00:0000 8 j 0x0002d0d0 f 0x0002d228
0x0002d228 0x0002d22c 00:0000 4 j 0x0002d22c
0x0002d22c 0x0002d23c 00:0000 16 j 0x0002d0d0 f 0x0002d23c
0x0002d23c 0x0002d250 00:0000 20 j 0x0002d0d0 f 0x0002d250
0x0002d250 0x0002d268 00:0000 24 j 0x0002d0d0
0x0002d250 0x0002d26c 00:0000 28 j 0x0002d0d0
0x0002d26c 0x0002d290 00:0000 36 j 0x0002d290
0x0002d290 0x0002d2a0 00:0000 16 j 0x0002c534
0x0002d2a4 0x0002d2c0 00:0000 28 j 0x0002c534
0x0002d290 0x0002d2a4 00:0000 20 j 0x0002c534
0x0002d2a4 0x0002d2c4 00:0000 32 j 0x0002c534
0x0002d2c4 0x0002d2d0 00:0000 12 j 0x0002cc8c f 0x0002d2d0
0x0002d2d0 0x0002d2e0 00:0000 16 j 0x0002d2f8 f 0x0002d2e0
0x0002d2e0 0x0002d2e4 00:0000 4 j 0x0002d2e4
0x0002d2e4 0x0002d2ec 00:0000 8 j 0x0002cc7c
0x0002d2f0 0x0002d2f4 00:0000 4 j 0x0002c380
0x0002d2e4 0x0002d2f0 00:0000 12 j 0x0002cc7c
0x0002d2f0 0x0002d2f8 00:0000 8 j 0x0002c380
0x0002d2f8 0x0002d314 00:0000 28 j 0x0002d2e4 f 0x0002d314
0x0002d314 0x0002d320 00:0000 12 j 0x0002cc7c
0x0002d324 0x0002d348 00:0000 36 j 0x0002cec4
0x0002d34c 0x0002d37c 00:0000 48 j 0x0002ce34
0x0002d394 0x0002d3a8 00:0000 20 j 0x0002ce48
0x0002d3ac 0x0002d3b8 00:0000 12 j 0x0002cde4
0x0002d314 0x0002d324 00:0000 16 j 0x0002cc7c
0x0002d324 0x0002d34c 00:0000 40 j 0x0002cec4
0x0002d34c 0x0002d380 00:0000 52 j 0x0002ce34
0x0002d394 0x0002d3ac 00:0000 24 j 0x0002ce48
0x0002d3ac 0x0002d3bc 00:0000 16 j 0x0002cde4
0x0002d3bc 0x0002d3e0 00:0000 36 j 0x0002d448 f 0x0002d3e0
0x0002d3e0 0x0002d3fc 00:0000 28 j 0x0002d42c f 0x0002d3fc
0x0002d3fc 0x0002d400 00:0000 4 j 0x0002d400
0x0002d400 0x0002d404 00:0000 4 j 0x0002cfa4
0x0002d408 0x0002d428 00:0000 32 j 0x0002d034
0x0002d400 0x0002d408 00:0000 8 j 0x0002cfa4
0x0002d408 0x0002d42c 00:0000 36 j 0x0002d034
0x0002d42c 0x0002d444 00:0000 24 j 0x0002d400 f 0x0002d444
0x0002d444 0x0002d448 00:0000 4 j 0x0002d448
0x0002d448 0x0002d458 00:0000 16 j 0x0002d400
0x0002d448 0x0002d45c 00:0000 20 j 0x0002d400
0x0002d45c 0x0002d470 00:0000 20 j 0x0002d16c f 0x0002d470
0x0002d470 0x0002d490 00:0000 32 j 0x0002d16c f 0x0002d490
0x0002d490 0x0002d494 00:0000 4 j 0x0002d180
0x0002d490 0x0002d498 00:0000 8 j 0x0002d180
EOF
RUN
@ -506,9 +506,9 @@ EXPECT=<<EOF
0x0001bc70 0x0001bc98 00:0000 40 j 0x0001bcf8
0x0001bc98 0x0001bca8 00:0000 16 j 0x0001bcf8 f 0x0001bca8
0x0001bca8 0x0001bcbc 00:0000 20 j 0x0001bcf8 f 0x0001bcbc
0x0001bcbc 0x0001bcc4 00:0000 8 j 0x0001bc34 f 0x0001bcc4
0x0001bcbc 0x0001bcc4 00:0000 8 j 0x0001bc34
0x0001bcc4 0x0001bcec 00:0000 40 j 0x0001bc70 f 0x0001bcec
0x0001bcec 0x0001bcf8 00:0000 12 j 0x0001bc70 f 0x0001bcf8
0x0001bcec 0x0001bcf8 00:0000 12 j 0x0001bc70
0x0001bcf8 0x0001bd00 00:0000 8
EOF
RUN