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Remove RzAnalysisPlugin.set_reg_profile (#2091)

Browse source 
Refactored all plugins to use get_reg_profile instead, which simply
returns the register profile instead of applying it as a side-effect.
This commit is contained in:
Florian Märkl 2021-12-11 10:18:31 +01:00 committed by GitHub
parent 8c1ef7672b
commit 79a17ef482
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
52 changed files with 1519 additions and 106 deletions
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15
librz/analysis/analysis.c
View file

@ -234,16 +234,12 @@ RZ_API char *rz_analysis_get_reg_profile(RzAnalysis *analysis) {
// deprecate.. or at least reuse get_reg_profile...
RZ_API bool rz_analysis_set_reg_profile(RzAnalysis *analysis) {
bool ret = false;
if (analysis && analysis->cur && analysis->cur->set_reg_profile) {
ret = analysis->cur->set_reg_profile(analysis);
} else {
char *p = rz_analysis_get_reg_profile(analysis);
if (p && *p) {
rz_reg_set_profile_string(analysis->reg, p);
ret = true;
}
free(p);
char *p = rz_analysis_get_reg_profile(analysis);
if (p) {
rz_reg_set_profile_string(analysis->reg, p);
ret = true;
}
free(p);
return ret;
}
@ -333,6 +329,7 @@ RZ_API void rz_analysis_set_cpu(RzAnalysis *analysis, const char *cpu) {
if (v != -1) {
analysis->pcalign = v;
}
rz_analysis_set_reg_profile(analysis);
rz_type_db_set_cpu(analysis->typedb, cpu);
char *types_dir = rz_path_system(RZ_SDB_TYPES);
rz_type_db_reload(analysis->typedb, types_dir);

6
librz/analysis/p/analysis_6502.c
View file

@ -909,7 +909,7 @@ static int _6502_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8
return op->size;
}
static bool set_reg_profile(RzAnalysis *analysis) {
static char *get_reg_profile(RzAnalysis *analysis) {
char *p =
"=PC pc\n"
"=SP sp\n"
@ -931,7 +931,7 @@ static bool set_reg_profile(RzAnalysis *analysis) {
"gpr N .1 .31 0\n"
"gpr sp .8 4 0\n"
"gpr pc .16 5 0\n";
return rz_reg_set_profile_string(analysis->reg, p);
return strdup(p);
}
static int esil_6502_init(RzAnalysisEsil *esil) {
@ -962,7 +962,7 @@ RzAnalysisPlugin rz_analysis_plugin_6502 = {
.bits = 8,
.address_bits = address_bits,
.op = &_6502_op,
.set_reg_profile = &set_reg_profile,
.get_reg_profile = &get_reg_profile,
.esil = true,
.esil_init = esil_6502_init,
.esil_fini = esil_6502_fini,

16
librz/analysis/p/analysis_8051.c
View file

@ -1012,6 +1012,9 @@ static int i8051_hook_reg_write(RzAnalysisEsil *esil, const char *name, ut64 *va
#endif
static int esil_i8051_init(RzAnalysisEsil *esil) {
// reset emulation control registers based on cpu
set_cpu_model(esil->analysis, true);
if (esil->cb.user) {
return true;
}
@ -1035,7 +1038,7 @@ static int esil_i8051_fini(RzAnalysisEsil *esil) {
return true;
}
static bool set_reg_profile(RzAnalysis *analysis) {
static char *get_reg_profile(RzAnalysis *analysis) {
const char *p =
"=PC pc\n"
"=SP sp\n"
@ -1086,14 +1089,7 @@ static bool set_reg_profile(RzAnalysis *analysis) {
"gpr _sfr .32 28 0\n"
"gpr _xdata .32 32 0\n"
"gpr _pdata .32 36 0\n";
int retval = rz_reg_set_profile_string(analysis->reg, p);
if (retval) {
// reset emulation control registers based on cpu
set_cpu_model(analysis, true);
}
return retval;
return strdup(p);
}
static ut32 map_direct_addr(RzAnalysis *analysis, ut8 addr) {
@ -1279,7 +1275,7 @@ RzAnalysisPlugin rz_analysis_plugin_8051 = {
.desc = "8051 CPU code analysis plugin",
.license = "LGPL3",
.op = &i8051_op,
.set_reg_profile = &set_reg_profile,
.get_reg_profile = &get_reg_profile,
.esil_init = esil_i8051_init,
.esil_fini = esil_i8051_fini
};

6
librz/analysis/p/analysis_amd29k.c
View file

@ -5,7 +5,7 @@
#include <rz_lib.h>
#include "../../asm/arch/amd29k/amd29k.h"
static bool set_reg_profile(RzAnalysis *analysis) {
static char *get_reg_profile(RzAnalysis *analysis) {
const char *p =
"=PC pc\n"
"=SP gp1\n"
@ -275,7 +275,7 @@ static bool set_reg_profile(RzAnalysis *analysis) {
"gpr lr126 .32 2024 0\n"
"gpr lr127 .32 2032 0\n"
"gpr lr128 .32 2040 0\n";
return rz_reg_set_profile_string(analysis->reg, p);
return strdup(p);
}
static int archinfo(RzAnalysis *a, int q) {
@ -330,7 +330,7 @@ RzAnalysisPlugin rz_analysis_plugin_amd29k = {
.bits = 32,
.archinfo = archinfo,
.op = &analop,
.set_reg_profile = &set_reg_profile,
.get_reg_profile = &get_reg_profile,
};
#ifndef RZ_PLUGIN_INCORE

6
librz/analysis/p/analysis_arc.c
View file

@ -1083,7 +1083,7 @@ static int archinfo(RzAnalysis *analysis, int query) {
}
}
static bool set_reg_profile(RzAnalysis *analysis) {
static char *get_reg_profile(RzAnalysis *analysis) {
if (analysis->bits != 16) {
return false;
}
@ -1135,7 +1135,7 @@ static bool set_reg_profile(RzAnalysis *analysis) {
/* TODO: */
/* Should I add the Auxiliary Register Set? */
/* it contains the flag bits, amongst other things */
return rz_reg_set_profile_string(analysis->reg, p16);
return strdup(p16);
}
RzAnalysisPlugin rz_analysis_plugin_arc = {
@ -1146,7 +1146,7 @@ RzAnalysisPlugin rz_analysis_plugin_arc = {
.desc = "ARC code analysis plugin",
.op = &arc_op,
.archinfo = archinfo,
.set_reg_profile = set_reg_profile,
.get_reg_profile = get_reg_profile,
};
#ifndef RZ_PLUGIN_INCORE

6
librz/analysis/p/analysis_avr.c
View file

@ -1917,7 +1917,7 @@ static int esil_avr_fini(RzAnalysisEsil *esil) {
return true;
}
static bool set_reg_profile(RzAnalysis *analysis) {
static char *get_reg_profile(RzAnalysis *analysis) {
const char *p =
"=PC pcl\n"
"=SN r24\n"
@ -2027,7 +2027,7 @@ RAMPX, RAMPY, RAMPZ, RAMPD and EIND:
// Store Program Memory Control and Status Register (SPMCSR)
"gpr spmcsr .8 64 0\n";
return rz_reg_set_profile_string(analysis->reg, p);
return strdup(p);
}
static int archinfo(RzAnalysis *analysis, int q) {
@ -2104,7 +2104,7 @@ RzAnalysisPlugin rz_analysis_plugin_avr = {
.bits = 8 | 16, // 24 big regs conflicts
.address_bits = address_bits,
.op = &avr_op,
.set_reg_profile = &set_reg_profile,
.get_reg_profile = &get_reg_profile,
.esil_init = esil_avr_init,
.esil_fini = esil_avr_fini,
.analysis_mask = analysis_mask_avr,

6
librz/analysis/p/analysis_cris.c
View file

@ -238,7 +238,7 @@ static int analop(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, in
return opsize;
}
static bool set_reg_profile(RzAnalysis *analysis) {
static char *get_reg_profile(RzAnalysis *analysis) {
const char *p =
"=PC pc\n"
"=SP r14\n" // XXX
@ -272,7 +272,7 @@ static bool set_reg_profile(RzAnalysis *analysis) {
"gpr r15 .32 60 0\n"
// ADD P REGISTERS
;
return rz_reg_set_profile_string(analysis->reg, p);
return strdup(p);
}
RzAnalysisPlugin rz_analysis_plugin_cris = {
@ -281,7 +281,7 @@ RzAnalysisPlugin rz_analysis_plugin_cris = {
.license = "LGPL3",
.esil = false,
.arch = "cris",
.set_reg_profile = set_reg_profile,
.get_reg_profile = get_reg_profile,
.bits = 32,
.op = &analop,
};

6
librz/analysis/p/analysis_dalvik.c
View file

@ -700,7 +700,7 @@ static int dalvik_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut
return sz;
}
static bool set_reg_profile(RzAnalysis *analysis) {
static char *get_reg_profile(RzAnalysis *analysis) {
const char *p =
"=PC ip\n"
"=SP sp\n"
@ -748,13 +748,13 @@ static bool set_reg_profile(RzAnalysis *analysis) {
"gpr ip .32 116 0\n"
"gpr sp .32 120 0\n"
"gpr bp .32 124 0\n";
return rz_reg_set_profile_string(analysis->reg, p);
return strdup(p);
}
RzAnalysisPlugin rz_analysis_plugin_dalvik = {
.name = "dalvik",
.arch = "dalvik",
.set_reg_profile = &set_reg_profile,
.get_reg_profile = &get_reg_profile,
.license = "LGPL3",
.bits = 32,
.desc = "Dalvik (Android VM) bytecode analysis plugin",

6
librz/analysis/p/analysis_gb.c
View file

@ -1464,7 +1464,7 @@ static int gb_anop(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8
the mbc can be seen as a register but it isn't. For the Gameboy the mbc is invisble.
*/
static bool set_reg_profile(RzAnalysis *analysis) {
static char *get_reg_profile(RzAnalysis *analysis) {
const char *p =
"=PC mpc\n"
"=SP sp\n"
@ -1503,7 +1503,7 @@ static bool set_reg_profile(RzAnalysis *analysis) {
"gpr mbcram .16 16 0\n"
"gpr ime .1 18 0\n";
return rz_reg_set_profile_string(analysis->reg, p);
return strdup(p);
}
static int esil_gb_init(RzAnalysisEsil *esil) {
@ -1542,7 +1542,7 @@ RzAnalysisPlugin rz_analysis_plugin_gb = {
.esil = true,
.bits = 16,
.op = &gb_anop,
.set_reg_profile = &set_reg_profile,
.get_reg_profile = &get_reg_profile,
.esil_init = esil_gb_init,
.esil_fini = esil_gb_fini,
};

6
librz/analysis/p/analysis_h8300.c
View file

@ -681,7 +681,7 @@ static int h8300_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr,
return ret;
}
static bool set_reg_profile(RzAnalysis *analysis) {
static char *get_reg_profile(RzAnalysis *analysis) {
char *p =
"=PC pc\n"
"=SP r7\n"
@ -720,7 +720,7 @@ static bool set_reg_profile(RzAnalysis *analysis) {
"gpr Z .1 .146 0\n"
"gpr V .1 .145 0\n"
"gpr C .1 .144 0\n";
return rz_reg_set_profile_string(analysis->reg, p);
return strdup(p);
}
RzAnalysisPlugin rz_analysis_plugin_h8300 = {
@ -731,7 +731,7 @@ RzAnalysisPlugin rz_analysis_plugin_h8300 = {
.bits = 16,
.op = &h8300_op,
.esil = true,
.set_reg_profile = set_reg_profile,
.get_reg_profile = get_reg_profile,
};
#ifndef RZ_PLUGIN_INCORE

6
librz/analysis/p/analysis_hexagon.c
View file

@ -27,7 +27,7 @@ RZ_API int hexagon_v6_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, cons
return op->size;
}
RZ_API bool set_reg_profile(RzAnalysis *analysis) {
RZ_API char *get_reg_profile(RzAnalysis *analysis) {
const char *p =
"=PC pc\n"
@ -375,7 +375,7 @@ RZ_API bool set_reg_profile(RzAnalysis *analysis) {
"gpr s75:74 .64 13676 0\n"
"gpr s77:76 .64 13684 0\n"
"gpr s79:78 .64 13692 0\n";
return rz_reg_set_profile_string(analysis->reg, p);
return strdup(p);
}
RzAnalysisPlugin rz_analysis_plugin_hexagon = {
@ -386,7 +386,7 @@ RzAnalysisPlugin rz_analysis_plugin_hexagon = {
.bits = 32,
.op = hexagon_v6_op,
.esil = false,
.set_reg_profile = set_reg_profile,
.get_reg_profile = get_reg_profile,
};
#ifndef RZ_PLUGIN_INCORE

7
librz/analysis/p/analysis_i4004.c
View file

@ -10,7 +10,7 @@
#define AVR_SOFTCAST(x, y) ((x) + ((y)*0x100))
static bool set_reg_profile(RzAnalysis *analysis) {
static char *get_reg_profile(RzAnalysis *analysis) {
const char *p =
"=PC PC\n"
/* syntax not yet supported */
@ -41,8 +41,7 @@ static bool set_reg_profile(RzAnalysis *analysis) {
"gpr PC1 .64 34 0\n"
"gpr PC2 .64 34 0\n"
"gpr PC3 .64 34 0\n";
return rz_reg_set_profile_string(analysis->reg, p);
return strdup(p);
}
/* That 3 is a hack */
@ -209,7 +208,7 @@ RzAnalysisPlugin rz_analysis_plugin_i4004 = {
.esil = false,
.bits = 8,
.op = &i4004_op,
.set_reg_profile = &set_reg_profile
.get_reg_profile = &get_reg_profile
};
#ifndef RZ_PLUGIN_INCORE

6
librz/analysis/p/analysis_java.c
View file

@ -111,7 +111,7 @@ static int java_analysis(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, cons
return op->size;
}
static bool set_reg_profile(RzAnalysis *analysis) {
static char *get_reg_profile(RzAnalysis *analysis) {
const char *p =
"=PC pc\n"
"=SP garbage\n"
@ -125,7 +125,7 @@ static bool set_reg_profile(RzAnalysis *analysis) {
"=A6 garbage\n"
"gpr pc .32 0 0\n"
"gpr garbage .32 32 0\n";
return rz_reg_set_profile_string(analysis->reg, p);
return strdup(p);
}
static int archinfo(RzAnalysis *analysis, int query) {
@ -164,7 +164,7 @@ RzAnalysisPlugin rz_analysis_plugin_java = {
.archinfo = archinfo,
.init = java_init,
.fini = java_fini,
.set_reg_profile = &set_reg_profile,
.get_reg_profile = &get_reg_profile,
};
#ifndef RZ_PLUGIN_INCORE

7
librz/analysis/p/analysis_m680x_cs.c
View file

@ -515,8 +515,7 @@ fin:
return opsize;
}
// XXX
static bool set_reg_profile(RzAnalysis *analysis) {
static char *get_reg_profile(RzAnalysis *analysis) {
const char *p =
"=PC pc\n"
"=SP sp\n"
@ -526,7 +525,7 @@ static bool set_reg_profile(RzAnalysis *analysis) {
"gpr sp .16 48 0\n"
"gpr a0 .16 48 0\n"
"gpr a1 .16 48 0\n";
return rz_reg_set_profile_string(analysis->reg, p);
return strdup(p);
}
RzAnalysisPlugin rz_analysis_plugin_m680x_cs = {
@ -535,7 +534,7 @@ RzAnalysisPlugin rz_analysis_plugin_m680x_cs = {
.license = "BSD",
.esil = false,
.arch = "m680x",
.set_reg_profile = &set_reg_profile,
.get_reg_profile = &get_reg_profile,
.bits = 16 | 32,
.op = &analop,
};

6
librz/analysis/p/analysis_m68k_cs.c
View file

@ -711,7 +711,7 @@ fin:
return opsize;
}
static bool set_reg_profile(RzAnalysis *analysis) {
static char *get_reg_profile(RzAnalysis *analysis) {
const char *p =
"=PC pc\n"
"=SP a7\n"
@ -766,7 +766,7 @@ static bool set_reg_profile(RzAnalysis *analysis) {
"gpr fpcr .32 176 0\n"
"gpr fpsr .32 180 0\n"
"gpr fpiar .32 184 0\n";
return rz_reg_set_profile_string(analysis->reg, p);
return strdup(p);
}
RzAnalysisPlugin rz_analysis_plugin_m68k_cs = {
@ -775,7 +775,7 @@ RzAnalysisPlugin rz_analysis_plugin_m68k_cs = {
.license = "BSD",
.esil = false,
.arch = "m68k",
.set_reg_profile = &set_reg_profile,
.get_reg_profile = &get_reg_profile,
.bits = 32,
.op = &analop,
};

6
librz/analysis/p/analysis_mcore.c
View file

@ -44,7 +44,7 @@ static int mcore_analysis(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, con
return op->size;
}
static bool set_reg_profile(RzAnalysis *analysis) {
static char *get_reg_profile(RzAnalysis *analysis) {
const char *p =
"=PC pc\n"
"=SP r1\n"
@ -107,7 +107,7 @@ static bool set_reg_profile(RzAnalysis *analysis) {
"gpr cr30 .32 184 0\n"
"gpr cr31 .32 188 0\n"
"gpr pc .32 192 0\n";
return rz_reg_set_profile_string(analysis->reg, p);
return strdup(p);
}
static int archinfo(RzAnalysis *analysis, int q) {
@ -122,7 +122,7 @@ RzAnalysisPlugin rz_analysis_plugin_mcore = {
.bits = 32,
.op = &mcore_analysis,
.archinfo = archinfo,
.set_reg_profile = &set_reg_profile,
.get_reg_profile = &get_reg_profile,
};
#ifndef RZ_PLUGIN_INCORE

6
librz/analysis/p/analysis_mips_gnu.c
View file

@ -1667,7 +1667,7 @@ static int mips_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8
*/
/* Set the profile register */
static bool mips_set_reg_profile(RzAnalysis *analysis) {
static char *mips_get_reg_profile(RzAnalysis *analysis) {
const char *p =
#if 0
"=PC pc\n"
@ -1758,7 +1758,7 @@ static bool mips_set_reg_profile(RzAnalysis *analysis) {
/* extra */
"gpr pc .64 272 0\n";
#endif
return rz_reg_set_profile_string(analysis->reg, p);
return strdup(p);
}
static int archinfo(RzAnalysis *analysis, int q) {
@ -1774,7 +1774,7 @@ RzAnalysisPlugin rz_analysis_plugin_mips_gnu = {
.esil = true,
.archinfo = archinfo,
.op = &mips_op,
.set_reg_profile = mips_set_reg_profile,
.get_reg_profile = mips_get_reg_profile,
};
#ifndef RZ_PLUGIN_INCORE

6
librz/analysis/p/analysis_null.c
View file

@ -11,8 +11,8 @@ static int null_analysis(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, cons
return op->size = 1;
}
static bool null_set_reg_profile(RzAnalysis *analysis) {
return rz_reg_set_profile_string(analysis->reg, "");
static char *null_get_reg_profile(RzAnalysis *analysis) {
return strdup("");
}
RzAnalysisPlugin rz_analysis_plugin_null = {
@ -22,7 +22,7 @@ RzAnalysisPlugin rz_analysis_plugin_null = {
.license = "LGPL3",
.bits = 8 | 16 | 32 | 64, /* is this used? */
.op = &null_analysis,
.set_reg_profile = &null_set_reg_profile,
.get_reg_profile = &null_get_reg_profile,
};
#ifndef RZ_PLUGIN_INCORE

20
librz/analysis/p/analysis_pic.c
View file

@ -1007,7 +1007,7 @@ beach:
return op->size;
}
static bool analysis_pic_midrange_set_reg_profile(RzAnalysis *esil) {
static char *analysis_pic_midrange_get_reg_profile(RzAnalysis *esil) {
const char *p =
"=PC pc\n"
"=SP stkptr\n"
@ -1034,10 +1034,10 @@ static bool analysis_pic_midrange_set_reg_profile(RzAnalysis *esil) {
"gpr stkptr .8 14 0\n"
"gpr _sram .32 15 0\n"
"gpr _stack .32 19 0\n";
return rz_reg_set_profile_string(esil->reg, p);
return strdup(p);
}
static bool analysis_pic_pic18_set_reg_profile(RzAnalysis *esil) {
static char *analysis_pic_pic18_get_reg_profile(RzAnalysis *esil) {
const char *p =
"#pc lives in nowhere actually"
"=PC pc\n"
@ -1153,7 +1153,7 @@ static bool analysis_pic_pic18_set_reg_profile(RzAnalysis *esil) {
"gpr stkptr .8 96 0\n"
"gpr tablat .8 14 0\n";
return rz_reg_set_profile_string(esil->reg, p);
return strdup(p);
}
static int analysis_pic_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, RzAnalysisOpMask mask) {
@ -1170,18 +1170,18 @@ static int analysis_pic_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, co
return -1;
}
static bool analysis_pic_set_reg_profile(RzAnalysis *analysis) {
static char *analysis_pic_get_reg_profile(RzAnalysis *analysis) {
if (analysis->cpu && strcasecmp(analysis->cpu, "baseline") == 0) {
// TODO: We are using the midrange profile as the baseline
return analysis_pic_midrange_set_reg_profile(analysis);
return analysis_pic_midrange_get_reg_profile(analysis);
}
if (analysis->cpu && strcasecmp(analysis->cpu, "midrange") == 0) {
return analysis_pic_midrange_set_reg_profile(analysis);
return analysis_pic_midrange_get_reg_profile(analysis);
}
if (analysis->cpu && strcasecmp(analysis->cpu, "pic18") == 0) {
return analysis_pic_pic18_set_reg_profile(analysis);
return analysis_pic_pic18_get_reg_profile(analysis);
}
return false;
return NULL;
}
RzAnalysisPlugin rz_analysis_plugin_pic = {
@ -1191,7 +1191,7 @@ RzAnalysisPlugin rz_analysis_plugin_pic = {
.arch = "pic",
.bits = 8,
.op = &analysis_pic_op,
.set_reg_profile = &analysis_pic_set_reg_profile,
.get_reg_profile = &analysis_pic_get_reg_profile,
.esil = true
};

6
librz/analysis/p/analysis_sh.c
View file

@ -1102,7 +1102,7 @@ static int sh_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8 *d
}
/* Set the profile register */
static bool sh_set_reg_profile(RzAnalysis *analysis) {
static char *sh_get_reg_profile(RzAnalysis *analysis) {
// TODO Add system ( ssr, spc ) + fpu regs
const char *p =
"=PC pc\n"
@ -1137,7 +1137,7 @@ static bool sh_set_reg_profile(RzAnalysis *analysis) {
"gpr vbr .32 80 0\n"
"gpr mach .32 84 0\n"
"gpr macl .32 88 0\n";
return rz_reg_set_profile_string(analysis->reg, p);
return strdup(p);
}
static int archinfo(RzAnalysis *analysis, int q) {
@ -1157,7 +1157,7 @@ RzAnalysisPlugin rz_analysis_plugin_sh = {
.archinfo = archinfo,
.bits = 32,
.op = &sh_op,
.set_reg_profile = &sh_set_reg_profile,
.get_reg_profile = &sh_get_reg_profile,
.esil = true
};

6
librz/analysis/p/analysis_sparc_cs.c
View file

@ -324,7 +324,7 @@ static int analop(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, in
return op->size;
}
static bool set_reg_profile(RzAnalysis *analysis) {
static char *get_reg_profile(RzAnalysis *analysis) {
const char *p =
"=PC pc\n"
"=SP sp\n"
@ -378,7 +378,7 @@ static bool set_reg_profile(RzAnalysis *analysis) {
"gpr i6 .32 136 0\n"
"gpr fp .32 136 0\n"
"gpr i7 .32 140 0\n";
return rz_reg_set_profile_string(analysis->reg, p);
return strdup(p);
}
static int archinfo(RzAnalysis *analysis, int q) {
@ -394,7 +394,7 @@ RzAnalysisPlugin rz_analysis_plugin_sparc_cs = {
.bits = 32 | 64,
.archinfo = archinfo,
.op = &analop,
.set_reg_profile = &set_reg_profile,
.get_reg_profile = &get_reg_profile,
};
#ifndef RZ_PLUGIN_INCORE

6
librz/analysis/p/analysis_sparc_gnu.c
View file

@ -458,7 +458,7 @@ static int sparc_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8
return sz;
}
static bool set_reg_profile(RzAnalysis *analysis) {
static char *get_reg_profile(RzAnalysis *analysis) {
/* As far as I can see, sparc v9 register and instruction set
don't depened on bits of the running application.
But: They depend on the bits of the consuming application,
@ -594,7 +594,7 @@ static bool set_reg_profile(RzAnalysis *analysis) {
"fpu qf60 .128 544 0\n" /* df60 df62 */
"gpr fsr .64 560 0\n"; /* note that
we've left out the filler */
return rz_reg_set_profile_string(analysis->reg, p);
return strdup(p);
}
static int archinfo(RzAnalysis *analysis, int q) {
@ -609,7 +609,7 @@ RzAnalysisPlugin rz_analysis_plugin_sparc_gnu = {
.bits = 32 | 64,
.op = &sparc_op,
.archinfo = archinfo,
.set_reg_profile = set_reg_profile,
.get_reg_profile = get_reg_profile,
};
#ifndef RZ_PLUGIN_INCORE

6
librz/analysis/p/analysis_spc700.c
View file

@ -17,7 +17,7 @@ static int op(RzAnalysis *analysis, RzAnalysisOp *rz_op, ut64 addr, const ut8 *b
return rz_op->size;
}
static bool set_reg_profile(RzAnalysis *analysis) {
static char *get_reg_profile(RzAnalysis *analysis) {
char *p =
"=PC pc\n"
"=SP sp\n"
@ -38,7 +38,7 @@ static bool set_reg_profile(RzAnalysis *analysis) {
"gpr N .1 .31 0\n"
"gpr sp .8 4 0\n"
"gpr pc .16 5 0\n";
return rz_reg_set_profile_string(analysis->reg, p);
return strdup(p);
}
RzAnalysisPlugin rz_analysis_plugin_spc700 = {
@ -48,7 +48,7 @@ RzAnalysisPlugin rz_analysis_plugin_spc700 = {
.license = "LGPL3",
.bits = 16,
.op = &op,
.set_reg_profile = &set_reg_profile,
.get_reg_profile = &get_reg_profile,
};
#ifndef RZ_PLUGIN_INCORE

6
librz/analysis/p/analysis_sysz.c
View file

@ -146,7 +146,7 @@ static int analop(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, in
return op->size;
}
static bool set_reg_profile(RzAnalysis *analysis) {
static char *get_reg_profile(RzAnalysis *analysis) {
const char *p =
"=PC r15\n"
"=LR r14\n"
@ -181,7 +181,7 @@ static bool set_reg_profile(RzAnalysis *analysis) {
"gpr r13 .32 52 0\n"
"gpr r14 .32 56 0\n"
"gpr r15 .32 60 0\n";
return rz_reg_set_profile_string(analysis->reg, p);
return strdup(p);
}
static int archinfo(RzAnalysis *analysis, int q) {
@ -205,7 +205,7 @@ RzAnalysisPlugin rz_analysis_plugin_sysz = {
.bits = 32 | 64,
.op = &analop,
.archinfo = archinfo,
.set_reg_profile = &set_reg_profile,
.get_reg_profile = &get_reg_profile,
};
#ifndef RZ_PLUGIN_INCORE

6
librz/analysis/p/analysis_tricore.c
View file

@ -8,7 +8,7 @@
#include <rz_analysis.h>
//#include "../../asm/arch/tricore/gnu/tricore-opc.c"
static bool set_reg_profile(RzAnalysis *analysis) {
static char *get_reg_profile(RzAnalysis *analysis) {
const char *p =
"=PC pc\n"
"=SP a10\n"
@ -71,7 +71,7 @@ static bool set_reg_profile(RzAnalysis *analysis) {
"gpr BIV .32 152 0\n"
"gpr BTV .32 156 0\n"
"gpr pc .32 160 0\n";
return rz_reg_set_profile_string(analysis->reg, p);
return strdup(p);
}
RzAnalysisPlugin rz_analysis_plugin_tricore = {
@ -80,7 +80,7 @@ RzAnalysisPlugin rz_analysis_plugin_tricore = {
.license = "LGPL3",
.arch = "tricore",
.bits = 32,
.set_reg_profile = set_reg_profile,
.get_reg_profile = get_reg_profile,
};
#ifndef RZ_PLUGIN_INCORE

6
librz/analysis/p/analysis_v810.c
View file

@ -387,7 +387,7 @@ static int v810_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8
return ret;
}
static bool set_reg_profile(RzAnalysis *analysis) {
static char *get_reg_profile(RzAnalysis *analysis) {
const char *p =
"=PC pc\n"
"=SP r3\n"
@ -441,7 +441,7 @@ static bool set_reg_profile(RzAnalysis *analysis) {
"flg s .1 132.30 0\n"
"flg z .1 132.31 0\n";
return rz_reg_set_profile_string(analysis->reg, p);
return strdup(p);
}
RzAnalysisPlugin rz_analysis_plugin_v810 = {
@ -452,7 +452,7 @@ RzAnalysisPlugin rz_analysis_plugin_v810 = {
.bits = 32,
.op = v810_op,
.esil = true,
.set_reg_profile = set_reg_profile,
.get_reg_profile = get_reg_profile,
};
#ifndef RZ_PLUGIN_INCORE

6
librz/analysis/p/analysis_z80.c
View file

@ -369,7 +369,7 @@ static int z80_analysis_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, co
return ilen;
}
static bool set_reg_profile(RzAnalysis *analysis) {
static char *get_reg_profile(RzAnalysis *analysis) {
const char *p =
"=PC mpc\n"
"=SP sp\n"
@ -408,7 +408,7 @@ static bool set_reg_profile(RzAnalysis *analysis) {
"gpr mbcram .16 16 0\n"
"gpr ime .1 18 0\n";
return rz_reg_set_profile_string(analysis->reg, p);
return strdup(p);
}
static int archinfo(RzAnalysis *analysis, int q) {
@ -420,7 +420,7 @@ RzAnalysisPlugin rz_analysis_plugin_z80 = {
.arch = "z80",
.license = "LGPL3",
.bits = 16,
.set_reg_profile = &set_reg_profile,
.get_reg_profile = &get_reg_profile,
.desc = "Z80 CPU code analysis plugin",
.archinfo = archinfo,
.op = &z80_analysis_op,

1
librz/include/rz_analysis.h
View file

@ -1231,7 +1231,6 @@ typedef struct rz_analysis_plugin_t {
// legacy rz_analysis_functions
RzAnalysisOpCallback op;
RzAnalysisRegProfCallback set_reg_profile;
RzAnalysisRegProfGetCallback get_reg_profile;
RzAnalysisFPBBCallback fingerprint_bb;
RzAnalysisFPFcnCallback fingerprint_fcn;

16
test/db/analysis/6502
View file

@ -10,3 +10,19 @@ EXPECT=<<EOF
5
EOF
RUN
NAME=6502 regs
FILE=
CMDS=<<EOF
e asm.arch=6502
ar
EOF
EXPECT=<<EOF
a = 0x00000000
x = 0x00000000
y = 0x00000000
flags = 0x00000000
sp = 0x00000000
pc = 0x00000000
EOF
RUN

265
test/db/analysis/amd29k Normal file
View file

@ -0,0 +1,265 @@
NAME=amd29k regs
FILE=
CMDS=<<EOF
e asm.arch=amd29k
ar
EOF
EXPECT=<<EOF
gp0 = 0x00000000
gp1 = 0x00000000
gp2 = 0x00000000
gp3 = 0x00000000
gp4 = 0x00000000
gp5 = 0x00000000
gp6 = 0x00000000
gp7 = 0x00000000
gp8 = 0x00000000
gp9 = 0x00000000
gp10 = 0x00000000
gp11 = 0x00000000
gp12 = 0x00000000
gp13 = 0x00000000
gp14 = 0x00000000
gp15 = 0x00000000
gp16 = 0x00000000
gp17 = 0x00000000
gp18 = 0x00000000
gp19 = 0x00000000
gp20 = 0x00000000
gp21 = 0x00000000
gp22 = 0x00000000
gp23 = 0x00000000
gp24 = 0x00000000
gp25 = 0x00000000
gp26 = 0x00000000
gp27 = 0x00000000
gp28 = 0x00000000
gp29 = 0x00000000
gp30 = 0x00000000
gp31 = 0x00000000
gp32 = 0x00000000
gp33 = 0x00000000
gp34 = 0x00000000
gp35 = 0x00000000
gp36 = 0x00000000
gp37 = 0x00000000
gp38 = 0x00000000
gp39 = 0x00000000
gp40 = 0x00000000
gp41 = 0x00000000
gp42 = 0x00000000
gp43 = 0x00000000
gp44 = 0x00000000
gp45 = 0x00000000
gp46 = 0x00000000
gp47 = 0x00000000
gp48 = 0x00000000
gp49 = 0x00000000
gp50 = 0x00000000
gp51 = 0x00000000
gp52 = 0x00000000
gp53 = 0x00000000
gp54 = 0x00000000
gp55 = 0x00000000
gp56 = 0x00000000
gp57 = 0x00000000
gp58 = 0x00000000
gp59 = 0x00000000
gp60 = 0x00000000
gp61 = 0x00000000
gp62 = 0x00000000
gp63 = 0x00000000
gp64 = 0x00000000
gp65 = 0x00000000
gp66 = 0x00000000
gp67 = 0x00000000
gp68 = 0x00000000
gp69 = 0x00000000
gp70 = 0x00000000
gp71 = 0x00000000
gp72 = 0x00000000
gp73 = 0x00000000
gp74 = 0x00000000
gp75 = 0x00000000
gp76 = 0x00000000
gp77 = 0x00000000
gp78 = 0x00000000
gp79 = 0x00000000
gp80 = 0x00000000
gp81 = 0x00000000
gp82 = 0x00000000
gp83 = 0x00000000
gp84 = 0x00000000
gp85 = 0x00000000
gp86 = 0x00000000
gp87 = 0x00000000
gp88 = 0x00000000
gp89 = 0x00000000
gp90 = 0x00000000
gp91 = 0x00000000
gp92 = 0x00000000
gp93 = 0x00000000
gp94 = 0x00000000
gp95 = 0x00000000
gp96 = 0x00000000
gp97 = 0x00000000
gp98 = 0x00000000
gp99 = 0x00000000
gp100 = 0x00000000
gp101 = 0x00000000
gp102 = 0x00000000
gp103 = 0x00000000
gp104 = 0x00000000
gp105 = 0x00000000
gp106 = 0x00000000
gp107 = 0x00000000
gp108 = 0x00000000
gp109 = 0x00000000
gp110 = 0x00000000
gp111 = 0x00000000
gp112 = 0x00000000
gp113 = 0x00000000
gp114 = 0x00000000
gp115 = 0x00000000
gp116 = 0x00000000
gp117 = 0x00000000
gp118 = 0x00000000
gp119 = 0x00000000
gp120 = 0x00000000
gp121 = 0x00000000
gp122 = 0x00000000
gp123 = 0x00000000
gp124 = 0x00000000
gp125 = 0x00000000
gp126 = 0x00000000
gp127 = 0x00000000
lr1 = 0x00000000
lr2 = 0x00000000
lr3 = 0x00000000
lr4 = 0x00000000
lr5 = 0x00000000
lr6 = 0x00000000
lr7 = 0x00000000
lr8 = 0x00000000
lr9 = 0x00000000
lr10 = 0x00000000
lr11 = 0x00000000
lr12 = 0x00000000
lr13 = 0x00000000
lr14 = 0x00000000
lr15 = 0x00000000
lr16 = 0x00000000
lr17 = 0x00000000
lr18 = 0x00000000
lr19 = 0x00000000
lr20 = 0x00000000
lr21 = 0x00000000
lr22 = 0x00000000
lr23 = 0x00000000
lr24 = 0x00000000
lr25 = 0x00000000
lr26 = 0x00000000
lr27 = 0x00000000
lr28 = 0x00000000
lr29 = 0x00000000
lr30 = 0x00000000
lr31 = 0x00000000
lr32 = 0x00000000
lr33 = 0x00000000
lr34 = 0x00000000
lr35 = 0x00000000
lr36 = 0x00000000
lr37 = 0x00000000
lr38 = 0x00000000
lr39 = 0x00000000
lr40 = 0x00000000
lr41 = 0x00000000
lr42 = 0x00000000
lr43 = 0x00000000
lr44 = 0x00000000
lr45 = 0x00000000
lr46 = 0x00000000
lr47 = 0x00000000
lr48 = 0x00000000
lr49 = 0x00000000
lr50 = 0x00000000
lr51 = 0x00000000
lr52 = 0x00000000
lr53 = 0x00000000
lr54 = 0x00000000
lr55 = 0x00000000
lr56 = 0x00000000
lr57 = 0x00000000
lr58 = 0x00000000
lr59 = 0x00000000
lr60 = 0x00000000
lr61 = 0x00000000
lr62 = 0x00000000
lr63 = 0x00000000
lr64 = 0x00000000
lr65 = 0x00000000
lr66 = 0x00000000
lr67 = 0x00000000
lr68 = 0x00000000
lr69 = 0x00000000
lr70 = 0x00000000
lr71 = 0x00000000
lr72 = 0x00000000
lr73 = 0x00000000
lr74 = 0x00000000
lr75 = 0x00000000
lr76 = 0x00000000
lr77 = 0x00000000
lr78 = 0x00000000
lr79 = 0x00000000
lr80 = 0x00000000
lr81 = 0x00000000
lr82 = 0x00000000
lr83 = 0x00000000
lr84 = 0x00000000
lr85 = 0x00000000
lr86 = 0x00000000
lr87 = 0x00000000
lr88 = 0x00000000
lr89 = 0x00000000
lr90 = 0x00000000
lr91 = 0x00000000
lr92 = 0x00000000
lr93 = 0x00000000
lr94 = 0x00000000
lr95 = 0x00000000
lr96 = 0x00000000
lr97 = 0x00000000
lr98 = 0x00000000
lr99 = 0x00000000
lr100 = 0x00000000
lr101 = 0x00000000
lr102 = 0x00000000
lr103 = 0x00000000
lr104 = 0x00000000
lr105 = 0x00000000
lr106 = 0x00000000
lr107 = 0x00000000
lr108 = 0x00000000
lr109 = 0x00000000
lr110 = 0x00000000
lr111 = 0x00000000
lr112 = 0x00000000
lr113 = 0x00000000
lr114 = 0x00000000
lr115 = 0x00000000
lr116 = 0x00000000
lr117 = 0x00000000
lr118 = 0x00000000
lr119 = 0x00000000
lr120 = 0x00000000
lr121 = 0x00000000
lr122 = 0x00000000
lr123 = 0x00000000
lr124 = 0x00000000
lr125 = 0x00000000
lr126 = 0x00000000
lr127 = 0x00000000
lr128 = 0x00000000
EOF
RUN

45
test/db/analysis/arc
View file

@ -1000,3 +1000,48 @@ size: 8
size: 4
EOF
RUN
NAME=ARC regs
FILE==
CMDS=<<EOF
e asm.arch=arc
e asm.bits=16
ar
EOF
EXPECT=<<EOF
r0 = 0x00000000
r1 = 0x00000000
r2 = 0x00000000
r3 = 0x00000000
r4 = 0x00000000
r5 = 0x00000000
r6 = 0x00000000
r7 = 0x00000000
r8 = 0x00000000
r9 = 0x00000000
r10 = 0x00000000
r11 = 0x00000000
r12 = 0x00000000
r13 = 0x00000000
r14 = 0x00000000
r15 = 0x00000000
r16 = 0x00000000
r17 = 0x00000000
r18 = 0x00000000
r19 = 0x00000000
r20 = 0x00000000
r21 = 0x00000000
r22 = 0x00000000
r23 = 0x00000000
r24 = 0x00000000
r25 = 0x00000000
gp = 0x00000000
fp = 0x00000000
sp = 0x00000000
ilink1 = 0x00000000
ilink2 = 0x00000000
blink = 0x00000000
lp_count = 0x00000000
pcl = 0x00000000
EOF
RUN

54
test/db/analysis/avr
View file

@ -937,3 +937,57 @@ EXPECT=<<EOF
EOF
RUN
NAME=avr regs
FILE=
CMDS=<<EOF
e asm.arch=avr
ar
EOF
EXPECT=<<EOF
r0 = 0x00000000
r1 = 0x00000000
r2 = 0x00000000
r3 = 0x00000000
r4 = 0x00000000
r5 = 0x00000000
r6 = 0x00000000
r7 = 0x00000000
r8 = 0x00000000
r9 = 0x00000000
r10 = 0x00000000
r11 = 0x00000000
r12 = 0x00000000
r13 = 0x00000000
r14 = 0x00000000
r15 = 0x00000000
r16 = 0x00000000
r17 = 0x00000000
r18 = 0x00000000
r19 = 0x00000000
r20 = 0x00000000
r21 = 0x00000000
r22 = 0x00000000
r23 = 0x00000000
r24 = 0x00000000
r25 = 0x00000000
x = 0x00000000
y = 0x00000000
z = 0x00000000
pc = 0x00000000
sp = 0x00000000
sreg = 0x00000000
rampx = 0x00000000
rampy = 0x00000000
rampz = 0x00000000
rampd = 0x00000000
eind = 0x00000000
_prog = 0x00000000
_page = 0x00000000
_eeprom = 0x00000000
_ram = 0x00000000
_io = 0x00000000
_sram = 0x00000000
spmcsr = 0x00000000
EOF
RUN

29
test/db/analysis/cris Normal file
View file

@ -0,0 +1,29 @@
NAME=cris regs
FILE=
CMDS=<<EOF
e asm.arch=cris
ar
EOF
EXPECT=<<EOF
sp = 0x00000000
acr = 0x00000000
pc = 0x00000000
srp = 0x00000000
r0 = 0x00000000
r1 = 0x00000000
r2 = 0x00000000
r3 = 0x00000000
r4 = 0x00000000
r5 = 0x00000000
r6 = 0x00000000
r7 = 0x00000000
r8 = 0x00000000
r9 = 0x00000000
r10 = 0x00000000
r11 = 0x00000000
r12 = 0x00000000
r13 = 0x00000000
r14 = 0x00000000
r15 = 0x00000000
EOF
RUN

48
test/db/analysis/dalvik
View file

@ -41,3 +41,51 @@ entry0 0xc9e6 [CALL] invoke-virtual {v1}, Lcom/ice/tar/TarEntry;->getUserName()L
method.public.Lcom_ice_tar_TarEntry_.toString__Ljava_lang_String 0xf04a [CALL] invoke-virtual {v4}, Lcom/ice/tar/TarEntry;->getUserName()Ljava/lang/String;
EOF
RUN
NAME=Dalvik regs
FILE=
CMDS=<<EOF
e asm.arch=dalvik
ar
EOF
EXPECT=<<EOF
v0 = 0x00000000
v1 = 0x00000000
v2 = 0x00000000
v3 = 0x00000000
v4 = 0x00000000
v5 = 0x00000000
v6 = 0x00000000
v7 = 0x00000000
v8 = 0x00000000
v9 = 0x00000000
v10 = 0x00000000
v11 = 0x00000000
v12 = 0x00000000
v13 = 0x00000000
v14 = 0x00000000
v15 = 0x00000000
v16 = 0x00000000
v17 = 0x00000000
v18 = 0x00000000
v19 = 0x00000000
v20 = 0x00000000
v21 = 0x00000000
v22 = 0x00000000
v23 = 0x00000000
v24 = 0x00000000
v25 = 0x00000000
v26 = 0x00000000
v27 = 0x00000000
v28 = 0x00000000
v29 = 0x00000000
v30 = 0x00000000
v31 = 0x00000000
v32 = 0x00000000
v33 = 0x00000000
v34 = 0x00000000
ip = 0x00000000
sp = 0x00000000
bp = 0x00000000
EOF
RUN

17
test/db/analysis/gb Normal file
View file

@ -0,0 +1,17 @@
NAME=gb regs
CMDS=<<EOF
e asm.arch=gb
ar
EOF
EXPECT=<<EOF
mpc = 0x00000000
sp = 0x00000000
af = 0x00000000
bc = 0x00000000
de = 0x00000000
hl = 0x00000000
mbcrom = 0x00000000
mbcram = 0x00000000
ime = 0x00000000
EOF
RUN

19
test/db/analysis/h8300 Normal file
View file

@ -0,0 +1,19 @@
NAME=h8300 regs
FILE=
CMDS=<<EOF
e asm.arch=h8300
ar
EOF
EXPECT=<<EOF
r0 = 0x00000000
r1 = 0x00000000
r2 = 0x00000000
r3 = 0x00000000
r4 = 0x00000000
r5 = 0x00000000
r6 = 0x00000000
r7 = 0x00000000
pc = 0x00000000
ccr = 0x00000000
EOF
RUN

326
test/db/analysis/hexagon
View file

@ -353,4 +353,328 @@ EXPECT=<<EOF
0x00009684 # 4: | immext(##0xffffff40)
0x00009688 # 4: \ memh(R0+#0x0) = ##0xffffff7f
EOF
RUN
RUN
NAME=hexagon regs
FILE=
CMDS=<<EOF
e asm.arch=hexagon
ar~[0]
EOF
EXPECT=<<EOF
lc0
sa0
lc1
sa1
p3:0
c5
pc
ugp
gp
cs0
cs1
upcyclelo
upcyclehi
framelimit
framekey
pktcountlo
pktcounthi
utimerlo
utimerhi
m0
m1
usr
c1:0
c3:2
c5:4
c7:6
c9:8
c11:10
c13:12
c15:14
c17:16
c19:18
c31:30
r1:0
r3:2
r5:4
r7:6
r9:8
r13:12
r15:14
r17:16
r19:18
r21:20
r23:22
r25:24
r27:26
r11:10
r29:28
r31:30
gelr
gsr
gosp
gbadva
g4
g5
g6
g7
g8
g9
g10
g11
g12
g13
g14
g15
gpmucnt4
gpmucnt5
gpmucnt6
gpmucnt7
g20
g21
g22
g23
gpcyclelo
gpcyclehi
gpmucnt0
gpmucnt1
gpmucnt2
gpmucnt3
g30
g31
g1:0
g3:2
g5:4
g7:6
g9:8
g11:10
g13:12
g15:14
g17:16
g19:18
g21:20
g23:22
g25:24
g27:26
g29:28
g31:30
q0
q1
q2
q3
v3:0
v7:4
v11:8
v15:12
v19:16
v23:20
v27:24
v31:28
v0
v1
v2
v3
v4
v5
v6
v7
v8
v9
v10
v11
v12
v13
v14
v15
v16
v17
v18
v19
v20
v21
v22
v23
v24
v25
v26
v27
v28
v29
v30
v31
v1:0
v3:2
v5:4
v7:6
v9:8
v11:10
v13:12
v15:14
v17:16
v19:18
v21:20
v23:22
v25:24
v27:26
v29:28
v31:30
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r10
r11
r29
r30
r31
p0
p1
p2
p3
sgp0
sgp1
stid
elr
badva0
badva1
ssr
ccr
htid
badva
imask
gevb
s12
s13
s14
s15
evb
modectl
syscfg
s19
ipendad
vid
vid1
bestwait
s24
schedcfg
s26
cfgbase
diag
rev
pcyclelo
pcyclehi
isdbst
isdbcfg0
isdbcfg1
livelock
brkptpc0
brkptcfg0
brkptpc1
brkptcfg1
isdbmbxin
isdbmbxout
isdben
isdbgpr
pmucnt4
pmucnt5
pmucnt6
pmucnt7
pmucnt0
pmucnt1
pmucnt2
pmucnt3
pmuevtcfg
s53
pmuevtcfg1
pmustid1
timerlo
timerhi
s58
s59
s60
s61
s62
s63
commit1t
commit2t
commit3t
commit4t
commit5t
commit6t
pcycle1t
pcycle2t
pcycle3t
pcycle4t
pcycle5t
pcycle6t
stfinst
isdbcmd
isdbver
brkptinfo
rgdr3
s1:0
s3:2
s5:4
s7:6
s9:8
s11:10
s13:12
s15:14
s17:16
s19:18
s21:20
s23:22
s25:24
s27:26
s29:28
s31:30
s33:32
s35:34
s37:36
s39:38
s41:40
s43:42
s45:44
s47:46
s49:48
s51:50
s53:52
s55:54
s57:56
s59:58
s61:60
s63:62
s65:64
s67:66
s69:68
s71:70
s73:72
s75:74
s77:76
s79:78
EOF
RUN

29
test/db/analysis/i4004 Normal file
View file

@ -0,0 +1,29 @@
NAME=i4004 regs
FILE=
CMDS=<<EOF
e asm.arch=i4004
ar
EOF
EXPECT=<<EOF
r0 = 0x00000000
r1 = 0x00000000
r2 = 0x00000000
r3 = 0x00000000
r4 = 0x00000000
r5 = 0x00000000
r6 = 0x00000000
r7 = 0x00000000
r8 = 0x00000000
r9 = 0x00000000
r10 = 0x00000000
r11 = 0x00000000
r12 = 0x00000000
r13 = 0x00000000
r14 = 0x00000000
r15 = 0x00000000
PC = 0x00000000
PC1 = 0x00000000
PC2 = 0x00000000
PC3 = 0x00000000
EOF
RUN

14
test/db/analysis/java
View file

@ -1681,4 +1681,16 @@ CMDS=e scr.prompt=false ; aaa
REGEXP_FILTER_OUT=ignoreme
EXPECT=<<EOF
EOF
RUN
RUN
NAME=Java Regs
FILE=
CMDS=<<EOF
e asm.arch=java
ar~!garbage
EOF
EXPECT=<<EOF
pc = 0x00000000
EOF
EXPECT_ERR=
RUN

14
test/db/analysis/m680x
View file

@ -14,3 +14,17 @@ f bb.00027 = 0x00000027
f bb.0002c = 0x0000002c
EOF
RUN
NAME=m680x regs
FILE=
CMDS=<<EOF
e asm.arch=m680x
ar
EOF
EXPECT=<<EOF
pc = 0x00000000
sp = 0x00000000
a0 = 0x00000000
a1 = 0x00000000
EOF
RUN

55
test/db/analysis/m68k
View file

@ -82,3 +82,58 @@ goto 0x312
EOF
RUN
NAME=m68k regs
FILE=
CMDS=<<EOF
e asm.arch=m68k
ar
EOF
EXPECT=<<EOF
d0 = 0x00000000
d1 = 0x00000000
d2 = 0x00000000
d3 = 0x00000000
d4 = 0x00000000
d5 = 0x00000000
d6 = 0x00000000
d7 = 0x00000000
a0 = 0x00000000
a1 = 0x00000000
a2 = 0x00000000
a3 = 0x00000000
a4 = 0x00000000
a5 = 0x00000000
a6 = 0x00000000
a7 = 0x00000000
fp0 = 0x00000000
fp1 = 0x00000000
fp2 = 0x00000000
fp3 = 0x00000000
fp4 = 0x00000000
fp5 = 0x00000000
fp6 = 0x00000000
fp7 = 0x00000000
pc = 0x00000000
sr = 0x00000000
ccr = 0x00000000
sfc = 0x00000000
dfc = 0x00000000
usp = 0x00000000
vbr = 0x00000000
cacr = 0x00000000
caar = 0x00000000
msp = 0x00000000
isp = 0x00000000
tc = 0x00000000
itt0 = 0x00000000
itt1 = 0x00000000
dtt0 = 0x00000000
dtt1 = 0x00000000
mmusr = 0x00000000
urp = 0x00000000
srp = 0x00000000
fpcr = 0x00000000
fpsr = 0x00000000
fpiar = 0x00000000
EOF
RUN

58
test/db/analysis/mcore Normal file
View file

@ -0,0 +1,58 @@
NAME=mcore regs
FILE=
CMDS=<<EOF
e asm.arch=mcore
ar
EOF
EXPECT=<<EOF
r0 = 0x00000000
r1 = 0x00000000
r2 = 0x00000000
r3 = 0x00000000
r4 = 0x00000000
r5 = 0x00000000
r6 = 0x00000000
r7 = 0x00000000
r8 = 0x00000000
r9 = 0x00000000
r10 = 0x00000000
r11 = 0x00000000
r12 = 0x00000000
r13 = 0x00000000
r14 = 0x00000000
r15 = 0x00000000
psr = 0x00000000
vbr = 0x00000000
epsr = 0x00000000
fpsr = 0x00000000
epc = 0x00000000
fpc = 0x00000000
ss0 = 0x00000000
ss1 = 0x00000000
ss2 = 0x00000000
ss3 = 0x00000000
ss4 = 0x00000000
gcr = 0x00000000
gsr = 0x00000000
cpidr = 0x00000000
dcsr = 0x00000000
cwr = 0x00000000
cr16 = 0x00000000
cfr = 0x00000000
ccr = 0x00000000
capr = 0x00000000
pacr = 0x00000000
prsr = 0x00000000
cr22 = 0x00000000
cr23 = 0x00000000
cr24 = 0x00000000
cr25 = 0x00000000
cr26 = 0x00000000
cr27 = 0x00000000
cr28 = 0x00000000
cr29 = 0x00000000
cr30 = 0x00000000
cr31 = 0x00000000
pc = 0x00000000
EOF
RUN

43
test/db/analysis/mips
View file

@ -742,3 +742,46 @@ EXPECT=<<EOF
0x004020ac afa20014 sw v0, 0x14(sp)
EOF
RUN
NAME=mips.gnu regs
FILE=
CMDS=<<EOF
e asm.arch=mips.gnu
ar
EOF
EXPECT=<<EOF
zero = 0x00000000
at = 0x00000000
v0 = 0x00000000
v1 = 0x00000000
a0 = 0x00000000
a1 = 0x00000000
a2 = 0x00000000
a3 = 0x00000000
t0 = 0x00000000
t1 = 0x00000000
t2 = 0x00000000
t3 = 0x00000000
t4 = 0x00000000
t5 = 0x00000000
t6 = 0x00000000
t7 = 0x00000000
s0 = 0x00000000
s1 = 0x00000000
s2 = 0x00000000
s3 = 0x00000000
s4 = 0x00000000
s5 = 0x00000000
s6 = 0x00000000
s7 = 0x00000000
t8 = 0x00000000
t9 = 0x00000000
k0 = 0x00000000
k1 = 0x00000000
gp = 0x00000000
sp = 0x00000000
fp = 0x00000000
ra = 0x00000000
pc = 0x00000000
EOF
RUN

9
test/db/analysis/null Normal file
View file

@ -0,0 +1,9 @@
NAME=null regs
FILE=
CMDS=<<EOF
e asm.arch=x86 # populate reg profile
e analysis.arch=null # reset to null
ar
EOF
EXPECT=
RUN

110
test/db/analysis/pic Normal file
View file

@ -0,0 +1,110 @@
NAME=pic regs
FILE=
CMDS=<<EOF
e asm.arch=pic
?e =============== midrange
e asm.cpu=midrange
ar
?e =============== pic18
e asm.cpu=pic18
ar
EOF
EXPECT=<<EOF
=============== midrange
indf0 = 0x00000000
indf1 = 0x00000000
pcl = 0x00000000
status = 0x00000000
fsr0l = 0x00000000
fsr0h = 0x00000000
fsr1l = 0x00000000
fsr1h = 0x00000000
bsr = 0x00000000
wreg = 0x00000000
pclath = 0x00000000
intcon = 0x00000000
pc = 0x00000000
stkptr = 0x00000000
_sram = 0x00000000
_stack = 0x00000000
=============== pic18
pc = 0x00000000
bsr = 0x00000000
tos = 0x00000000
indf0 = 0x00000000
indf1 = 0x00000000
indf2 = 0x00000000
tblptr = 0x00000000
tblptru = 0x00000000
rcon = 0x00000000
memcon = 0x00000000
intcon = 0x00000000
intcon2 = 0x00000000
intcon3 = 0x00000000
pie1 = 0x00000000
porta = 0x00000000
trisa = 0x00000000
portb = 0x00000000
tisb = 0x00000000
latb = 0x00000000
portc = 0x00000000
trisc = 0x00000000
latc = 0x00000000
portd = 0x00000000
trisd = 0x00000000
latd = 0x00000000
pspcon = 0x00000000
porte = 0x00000000
trise = 0x00000000
late = 0x00000000
t0con = 0x00000000
t1con = 0x00000000
t2con = 0x00000000
tmr1h = 0x00000000
tmr0h = 0x00000000
tmr1l = 0x00000000
tmr2 = 0x00000000
pr2 = 0x00000000
ccpr1h = 0x00000000
postinc2 = 0x00000000
ccpr1l = 0x00000000
postdec2 = 0x00000000
ccp1con = 0x00000000
preinc2 = 0x00000000
ccpr2h = 0x00000000
plusw2 = 0x00000000
ccpr2l = 0x00000000
ccp2con = 0x00000000
status = 0x00000000
prod = 0x00000000
osccon = 0x00000000
tmr3h = 0x00000000
lvdcon = 0x00000000
tmr3l = 0x00000000
wdtcon = 0x00000000
t3con = 0x00000000
spbrg = 0x00000000
postinc0 = 0x00000000
rcreg = 0x00000000
postdec0 = 0x00000000
txreg = 0x00000000
preinc0 = 0x00000000
txsta = 0x00000000
plusw0 = 0x00000000
rcsta = 0x00000000
sspbuf = 0x00000000
wreg = 0x00000000
sspadd = 0x00000000
sspstat = 0x00000000
postinc1 = 0x00000000
sspcon1 = 0x00000000
postdec1 = 0x00000000
sspcon2 = 0x00000000
preinc1 = 0x00000000
adresh = 0x00000000
plusw1 = 0x00000000
adresl = 0x00000000
adcon0 = 0x00000000
stkptr = 0x00000000
EOF
RUN

33
test/db/analysis/sh
View file

@ -71,3 +71,36 @@ EOF
EXPECT=<<EOF
EOF
RUN
NAME=SuperH regs
FILE=
CMDS=<<EOF
e asm.arch=sh
ar
EOF
EXPECT=<<EOF
r0 = 0x00000000
r1 = 0x00000000
r2 = 0x00000000
r3 = 0x00000000
r4 = 0x00000000
r5 = 0x00000000
r6 = 0x00000000
r7 = 0x00000000
r8 = 0x00000000
r9 = 0x00000000
r10 = 0x00000000
r11 = 0x00000000
r12 = 0x00000000
r13 = 0x00000000
r14 = 0x00000000
r15 = 0x00000000
pc = 0x00000000
pr = 0x00000000
sr = 0x00000000
gbr = 0x00000000
vbr = 0x00000000
mach = 0x00000000
macl = 0x00000000
EOF
RUN

97
test/db/analysis/sparc
View file

@ -330,3 +330,100 @@ EXPECT=<<EOF
0x0001bcf8 0x0001bd00 00:0000 8
EOF
RUN
NAME=sparc regs
FILE=
CMDS=<<EOF
e asm.arch=sparc
ar
EOF
EXPECT=<<EOF
psr = 0x00000000
pc = 0x00000000
npc = 0x00000000
y = 0x00000000
g0 = 0x00000000
g1 = 0x00000000
g2 = 0x00000000
g3 = 0x00000000
g4 = 0x00000000
g5 = 0x00000000
g6 = 0x00000000
g7 = 0x00000000
o0 = 0x00000000
o1 = 0x00000000
o2 = 0x00000000
o3 = 0x00000000
o4 = 0x00000000
o5 = 0x00000000
o6 = 0x00000000
sp = 0x00000000
o7 = 0x00000000
l0 = 0x00000000
l1 = 0x00000000
l2 = 0x00000000
l3 = 0x00000000
l4 = 0x00000000
l5 = 0x00000000
l6 = 0x00000000
l7 = 0x00000000
i0 = 0x00000000
i1 = 0x00000000
i2 = 0x00000000
i3 = 0x00000000
i4 = 0x00000000
i5 = 0x00000000
i6 = 0x00000000
fp = 0x00000000
i7 = 0x00000000
EOF
RUN
NAME=sparc.gnu regs
FILE=
CMDS=<<EOF
e asm.arch=sparc.gnu
ar
EOF
EXPECT=<<EOF
g0 = 0x00000000
g1 = 0x00000000
g2 = 0x00000000
g3 = 0x00000000
g4 = 0x00000000
g5 = 0x00000000
g6 = 0x00000000
g7 = 0x00000000
o0 = 0x00000000
o1 = 0x00000000
o2 = 0x00000000
o3 = 0x00000000
o4 = 0x00000000
o5 = 0x00000000
o6 = 0x00000000
o7 = 0x00000000
l0 = 0x00000000
l1 = 0x00000000
l2 = 0x00000000
l3 = 0x00000000
l4 = 0x00000000
l5 = 0x00000000
l6 = 0x00000000
l7 = 0x00000000
i0 = 0x00000000
i1 = 0x00000000
i2 = 0x00000000
i3 = 0x00000000
i4 = 0x00000000
i5 = 0x00000000
i6 = 0x00000000
i7 = 0x00000000
ccr = 0x00000000
pc = 0x00000000
ncp = 0x00000000
y = 0x00000000
asi = 0x00000000
fprs = 0x00000000
fsr = 0x00000000
EOF
RUN

15
test/db/analysis/spc700 Normal file
View file

@ -0,0 +1,15 @@
NAME=spc700 regs
FILE=
CMDS=<<EOF
e asm.arch=spc700
ar
EOF
EXPECT=<<EOF
a = 0x00000000
x = 0x00000000
y = 0x00000000
flags = 0x00000000
sp = 0x00000000
pc = 0x00000000
EOF
RUN

33
test/db/analysis/sysz
View file

@ -46,3 +46,36 @@ EXPECT=<<EOF
]
EOF
RUN
NAME=sysz regs
FILE=
CMDS=<<EOF
e asm.arch=sysz
ar
EOF
EXPECT=<<EOF
sb = 0x00000000
sl = 0x00000000
fp = 0x00000000
ip = 0x00000000
sp = 0x00000000
lr = 0x00000000
pc = 0x00000000
r0 = 0x00000000
r1 = 0x00000000
r2 = 0x00000000
r3 = 0x00000000
r4 = 0x00000000
r5 = 0x00000000
r6 = 0x00000000
r7 = 0x00000000
r8 = 0x00000000
r9 = 0x00000000
r10 = 0x00000000
r11 = 0x00000000
r12 = 0x00000000
r13 = 0x00000000
r14 = 0x00000000
r15 = 0x00000000
EOF
RUN

36
test/db/analysis/tricore
View file

@ -156,3 +156,39 @@ EXPECT=<<EOF
0x80000068 0d00c004 isync ; synchronize instructions
EOF
RUN
NAME=tricore regs
FILE=
CMDS=<<EOF
e asm.arch=tricore
ar
EOF
EXPECT=<<EOF
p0 = 0x00000000
p2 = 0x00000000
p4 = 0x00000000
p6 = 0x00000000
p8 = 0x00000000
p10 = 0x00000000
p12 = 0x00000000
p14 = 0x00000000
e0 = 0x00000000
e2 = 0x00000000
e4 = 0x00000000
e6 = 0x00000000
e8 = 0x00000000
e10 = 0x00000000
e12 = 0x00000000
e14 = 0x00000000
PSW = 0x00000000
PCXI = 0x00000000
FCX = 0x00000000
LCX = 0x00000000
ISP = 0x00000000
ICR = 0x00000000
PIPN = 0x00000000
BIV = 0x00000000
BTV = 0x00000000
pc = 0x00000000
EOF
RUN

43
test/db/analysis/v810 Normal file
View file

@ -0,0 +1,43 @@
NAME=v810 regs
FILE=
CMDS=<<EOF
e asm.arch=v810
ar
EOF
EXPECT=<<EOF
r0 = 0x00000000
r1 = 0x00000000
r2 = 0x00000000
r3 = 0x00000000
r4 = 0x00000000
r5 = 0x00000000
r6 = 0x00000000
r7 = 0x00000000
r8 = 0x00000000
r9 = 0x00000000
r10 = 0x00000000
r11 = 0x00000000
r12 = 0x00000000
r13 = 0x00000000
r14 = 0x00000000
r15 = 0x00000000
r16 = 0x00000000
r17 = 0x00000000
r18 = 0x00000000
r19 = 0x00000000
r20 = 0x00000000
r21 = 0x00000000
r22 = 0x00000000
r23 = 0x00000000
r24 = 0x00000000
r25 = 0x00000000
r26 = 0x00000000
r27 = 0x00000000
r28 = 0x00000000
r29 = 0x00000000
r30 = 0x00000000
r31 = 0x00000000
pc = 0x00000000
psw = 0x00000000
EOF
RUN

19
test/db/analysis/z80
View file

@ -11,3 +11,22 @@ EXPECT=<<EOF
0x00000016 3 7 fcn.00000016
EOF
RUN
NAME=z80 regs
FILE=
CMDS=<<EOF
e asm.arch=z80
ar
EOF
EXPECT=<<EOF
mpc = 0x00000000
sp = 0x00000000
af = 0x00000000
bc = 0x00000000
de = 0x00000000
hl = 0x00000000
mbcrom = 0x00000000
mbcram = 0x00000000
ime = 0x00000000
EOF
RUN