Deprecate RzSyscallPort and move the existing sysregs to SDB (#1160)
This commit is contained in:
Aswin C
GitHub
parent
2e4becf7c6
commit
92b5783fa1
11 changed files with 453 additions and 137 deletions
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@ -605,6 +605,9 @@ static bool cb_asmarch(void *user, void *data) {
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rz_analysis_set_big_endian(core->analysis, bigbin);
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rz_core_analysis_cc_init(core);
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const char *dir_prefix = rz_config_get(core->config, "dir.prefix");
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rz_sysreg_set_arch(core->analysis->syscall, node->value, dir_prefix);
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return true;
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}
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@ -3385,9 +3385,8 @@ static void ds_print_sysregs(RDisasmState *ds) {
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// Syscalls first
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case RZ_ANALYSIS_OP_TYPE_IO: {
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const int imm = (int)ds->analop.val;
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RzSyscall *sc = core->analysis->syscall;
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const char *ioname = rz_syscall_get_io(sc, imm);
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if (ioname && *ioname) {
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const char *ioname = rz_sysreg_get(core->analysis->syscall, "mmio", imm);
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if (ioname) {
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CMT_ALIGN;
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ds_comment(ds, true, "; IO %s", ioname);
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ds->has_description = true;
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@ -3399,7 +3398,7 @@ static void ds_print_sysregs(RDisasmState *ds) {
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case RZ_ANALYSIS_OP_TYPE_LOAD:
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case RZ_ANALYSIS_OP_TYPE_STORE: {
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const int imm = (int)ds->analop.ptr;
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const char *sr = rz_syscall_sysreg(core->analysis->syscall, "reg", imm);
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const char *sr = rz_sysreg_get(core->analysis->syscall, "reg", imm);
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if (sr) {
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CMT_ALIGN;
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ds_comment(ds, true, "; REG %s - %s", sr, "");
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@ -24,10 +24,15 @@ typedef struct rz_syscall_item_t {
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char *sargs;
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} RzSyscallItem;
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typedef struct rz_syscall_port_t {
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int port;
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const char *name;
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} RzSyscallPort;
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typedef struct rz_sysreg_item_t {
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char *type;
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char *name;
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char *comment;
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} RzSysregItem;
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typedef struct rz_type_db_sysreg {
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HtUP /* <ut64 , RzSysregItem> */ *port;
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} RzSysregsDB;
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typedef struct rz_syscall_t {
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FILE *fd;
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@ -38,9 +43,8 @@ typedef struct rz_syscall_t {
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char *cpu;
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// database
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RzSyscallItem *sysptr;
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RzSyscallPort *sysport;
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Sdb *db;
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Sdb *srdb;
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RzSysregsDB *srdb;
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int refs;
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} RzSyscall;
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@ -94,12 +98,15 @@ RZ_API bool rz_syscall_setup(RzSyscall *s, const char *arch, int bits, const cha
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RZ_API RzSyscallItem *rz_syscall_get(RzSyscall *ctx, int num, int swi);
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RZ_API int rz_syscall_get_num(RzSyscall *ctx, const char *str);
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RZ_API const char *rz_syscall_get_i(RzSyscall *ctx, int num, int swi);
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RZ_API const char *rz_syscall_sysreg(RzSyscall *s, const char *type, ut64 num);
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RZ_API RzList *rz_syscall_list(RzSyscall *ctx);
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RZ_API int rz_syscall_get_swi(RzSyscall *s);
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/* io */
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RZ_API const char *rz_syscall_get_io(RzSyscall *s, int ioport);
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RZ_API const char *rz_sysreg_get(RzSyscall *s, const char *type, ut64 num);
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RZ_API bool rz_sysreg_set_arch(RzSyscall *s, const char *arch, const char *dir_prefix);
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RZ_API bool rz_type_db_load_sysregs_sdb(RzSysregsDB *sysregdb, const char *path);
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RZ_API RzSysregsDB *rz_sysregs_db_new();
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RZ_API RZ_OWN RzSysregItem *rz_sysreg_item_new(RZ_NULLABLE const char *name);
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RZ_API void rz_sysreg_item_free(RzSysregItem *sysregitem);
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#endif
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#ifdef __cplusplus
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255
librz/reg/d/avr-ATmega8-8.sdb.txt
Normal file
255
librz/reg/d/avr-ATmega8-8.sdb.txt
Normal file
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@ -0,0 +1,255 @@
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SREG=reg
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SREG.address=0x3f
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SREG.comment=SREG Flags
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SPH=reg
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SPH.address=0x3e
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SPH.comment=Stack higher bits SP8 SP10
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SPL=reg
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SPL.address=0x3d
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SPL.comment=Stack lower bits SP0 SP7
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OCR0=reg
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OCR0.address=0x3c
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OCR0.comment=Timer Counter0 Output Compare Register
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GICR=reg
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GICR.address=0x3b
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GICR.comment=General Interrupt Control Register
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GIFR=reg
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GIFR.address=0x3a
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GIFR.comment=General Interrupt Flag Register
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TIMSK=reg
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TIMSK.address=0x39
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TIMSK.comment=Timer-Counter Interrupt Mask
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TIFR=reg
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TIFR.address=0x38
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TIFR.comment=Timer-Counter Interrupt Flag Register
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SPMCR=reg
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SPMCR.address=0x37
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SPMCR.comment=Store Program Memory Control Register
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TWCR=reg
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TWCR.address=0x36
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TWCR.comment=I2C (Two wire) Control Register
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MCUCR=reg
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MCUCR.address=0x35
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MCUCR.comment=MCU (Power Management) Control Register
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MCUCSR=reg
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MCUCSR.address=0x34
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MCUCSR.comment=MCU Control and Status Register Watchdog Brown out Power on
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TCCR0=reg
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TCCR0.address=0x33
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TCCR0.comment=Timer-Counter Control Register
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TCNT0=reg
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TCNT0.address=0x32
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TCNT0.comment=Timer-Counter Register 0 (8 bits)
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OSCCAL=reg
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OSCCAL.address=0x31
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OSCCAL.comment=(Internal) Oscillator Calibration Register
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SFIOR=reg
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SFIOR.address=0x30
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SFIOR.comment=Special Function IO Register
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TCCR1A=reg
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TCCR1A.address=0x2f
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TCCR1A.comment=Timer-Counter Control Register 1A (16 bits) Used for (fast) PWM
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TCCR1B=reg
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TCCR1B=0x2e
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TCCR1B.comment=Timer-Counter Control Register 1B (16 bits) PWM mode select
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TCNT1H=reg
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TCNT1H.address=0x2d
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TCNT1H.comment=Timer-Counter1 Register High byte
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TCNT1L=reg
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TCNT1L.address=0x2c
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TCNT1L.comment=Timer-Counter1 Register Low byte
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OCR1AH=reg
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OCR1AH.address=0x2b
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OCR1AH.comment=Timer-Counter1 Output Compare Register A High byte
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OCR1AL=reg
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OCR1AL.address=0x2a
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OCR1AL.comment=Timer-Counter1 Output Compare Register A Low byte
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OCR1BH=reg
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OCR1BH.address=0x29
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OCR1BH.comment=Timer-Counter1 Output Compare Register B High byte
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OCR1BL=reg
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OCR1BL.address=0x28
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OCR1BL.comment=Timer-Counter1 Output Compare Register B Low byte
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ICR1H=reg
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ICR1H.address=0x27
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ICR1H.comment=Timer-Counter1 Input Capture Register High byte
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ICR1L=reg
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ICR1L.address=0x26
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ICR1L.comment=Timer-Counter1 Input Capture Register Low byte
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TCCR2=reg
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TCCR2.address=0x25
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TCCR2.comment=Timer-Counter2 Control Register (8 bits)
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TCNT2=reg
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TCNT2.address=0x24
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TCNT2.comment=Timer-Counter2 (8 bits)
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OCR2=reg
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OCR2.address=0x23
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OCR2.comment=Timer-Counter2 Output Compare Register
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ASSR=reg
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ASSR.address=0x22
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ASSR.comment=Asynchronous Operation of the Timer-Counter
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WDTCR=reg
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WDTCR.address=0x21
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WDTCR.comment=Watchdog Timer Control Register
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UBRRH=reg
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UBRRH.address=0x20
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UBRRH.comment=USART Baud Rate Registers=High byte and Control Aka setting serial port speed
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EEARH=reg
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EEARH.address=0x1f
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EEARH.comment=EEPROM Address Register High byte
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EEARL=reg
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EEARL.address=0x1e
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EEARL.comment=EEPROM Address Register Low byte
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EEDR=reg
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EEDR.address=0x1d
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EEDR.comment= EEPROM Data Register
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EECR=reg
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EECR.address=0x1c
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EECR.comment= EEPROM Control Register
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PORTA=reg
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PORTA.address=0x1b
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PORTA.comment= Output pins-pullups address for port A
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DDRA=reg
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DDRA.address=0x1a
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DDRA.comment= Data Direction Register for Port A
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PINA=reg
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PINA.address=0x19
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PINA.comment= Input Pins Address for Port A
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SPDR=reg
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SPDR.address=0x0f
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SPDR.comment= SPI Data Register
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SPSR=reg
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SPSR.address=0x0e
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SPSR.comment= SPI Status Register
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SPCR=reg
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SPCR.address=0x0d
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SPCR.comment= SPI Control Register
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UDR=reg
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UDR.address=0x0c
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UDR.comment= USART I-O Data Register
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UCSRA=reg
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UCSRA.address=0x0b
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UCSRA.comment= USART Control and Status Register A
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UCSRB=reg
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UCSRB.address=0x0a
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UCSRB.comment= USART Control and Status Register B
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UBRRL=reg
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UBRRL.address=0x09
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UBRRL.comment= USART Baud Rate Registers Low byte Aka setting serial port speed
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ACSR=reg
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ACSR.address=0x08
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ACSR.comment= Analog Comparator Control and Status Register
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ADMUX=reg
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ADMUX.address=0x07
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ADMUX.comment= ADC Multiplexer Selection Register
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ADCSRA=reg
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ADCSRA.address=0x06
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ADCSRA.comment= ADC Control and Status Register A
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ADCH=reg
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ADCH.address=0x05
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ADCH.comment= ADC Data Register High byte
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ADCL=reg
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ADCL.address=0x04
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ADCL.comment= ADC Data Register Low byte
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TWDR=reg
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TWDR.address=0x03
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TWDR.comment= I2C (Two wire) Serial Interface Data Register
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TWAR=reg
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TWAR.address=0x02
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TWAR.comment= I2C (Two wire) Serial Interface (Slave) Address Register
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TWSR=reg
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TWSR.address=0x01
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TWSR.comment= I2C (Two wire) Serial Interface Status Register
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TWBR=reg
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TWBR.address=0x99
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TWBR.comment= I2C (Two wire) Serial Interface Bit Rate Register
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PORTB=mmio
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PORTB.address=0x18
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PORTB.comment=Output pins/pullups address for port B
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DDRB=mmio
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DDRB.address=0x17
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DDRB.comment=Data Direction Register for Port B
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PINB=mmio
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PINB.address=0x16
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PINB.comment=Input Pins Address for Port B
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PORTC=mmio
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PORTC.address=0x15
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PORTC.comment=Output pins/pullups address for port C
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DDRC=mmio
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DDRC.address=0x14
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DDRC.comment=Data Direction Register for Port C
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PINC=mmio
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PINC.address=0x13
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PINC.comment=Input Pins Address for Port C
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PORTD=mmio
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PORTD.address=0x12
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PORTD.comment=Output pins/pullups address for port D
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DDRD=mmio
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DDRD.address=0x11
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DDRD.comment=Data Direction Register for Port D
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PIND=mmio
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PIND.address=0x10
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PIND.comment=Input Pins Address for Port D
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16
librz/reg/d/meson.build
Normal file
16
librz/reg/d/meson.build
Normal file
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@ -0,0 +1,16 @@
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sdb_files = [
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'avr-ATmega8-8'
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]
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foreach file : sdb_files
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outfile = '@0@.sdb'.format(file)
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custom_target(outfile,
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input: '@0@.sdb.txt'.format(file),
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output: outfile,
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command: sdb_gen_cmd,
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depends: sdb_exe,
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build_by_default: true,
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install: true,
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install_dir: join_paths(rizin_sdb, 'reg')
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)
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endforeach
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@ -1,4 +0,0 @@
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TWBR=0x00,0
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TWSR=0x01,0
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TWAR=0x02,0
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@ -1,81 +0,0 @@
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// SPDX-FileCopyrightText: 2010-2020 pancake <pancake@nopcode.org>
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// SPDX-FileCopyrightText: 2016 Roman Valls Guimera <brainstorm@nopcode.org>
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// SPDX-License-Identifier: LGPL-3.0-only
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#include "rz_syscall.h"
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RzSyscallPort sysport_x86[] = {
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{ 0x3, "HELLO WORLD" },
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{ 0x378, "lp1" },
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{ 0, NULL }
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};
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// XXX: This is for Atmega8A, check other datasheets Register Summary to be sure about your MCU:
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// http://www.atmel.com/Images/Atmel-2486-8-bit-AVR-microcontroller-ATmega8_L_datasheet.pdf
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RzSyscallPort sysport_avr[] = {
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{ 0x3f, "SREG: flags" },
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{ 0x3e, "SPH: Stack higher bits SP8-SP10" },
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{ 0x3d, "SPL: Stack lower bits SP0-SP7" },
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{ 0x3c, "OCR0: Timer/Counter0 Output Compare Register." },
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{ 0x3b, "GICR: General Interrupt Control Register" },
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{ 0x3a, "GIFR: General Interrupt Flag Register" },
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{ 0x39, "TIMSK: Timer/Counter Interrupt Mask" },
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{ 0x38, "TIFR: Timer/Counter Interrupt Flag Register" },
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{ 0x37, "SPMCR: Store Program Memory Control Register" },
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{ 0x36, "TWCR: I2C (Two-wire) Control Register" },
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{ 0x35, "MCUCR: MCU (Power Management) Control Register" },
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{ 0x34, "MCUCSR: MCU Control and Status Register. Watchdog, Brown-out, Power-on..." },
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{ 0x33, "TCCR0: Timer/Counter Control Register 0" },
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{ 0x32, "TCNT0: Timer/Counter Register 0 (8 bits)" },
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{ 0x31, "OSCCAL: (Internal) Oscillator Calibration Register" },
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{ 0x30, "SFIOR: Special Function IO Register" },
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{ 0x2f, "TCCR1A: Timer/Counter Control Register 1A (16 bits). Used for (fast) PWM." },
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{ 0x2e, "TCCR1B: Timer/Counter Control Register 1B (16 bits). PWM mode select." },
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{ 0x2d, "TCNT1H: Timer/Counter1 Register High byte." },
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{ 0x2c, "TCNT1L: Timer/Counter1 Register Low byte." },
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{ 0x2b, "OCR1AH: Timer/Counter1 Output Compare Register A High byte." },
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{ 0x2a, "OCR1AL: Timer/Counter1 Output Compare Register A Low byte." },
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{ 0x29, "OCR1BH: Timer/Counter1 Output Compare Register B High byte." },
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{ 0x28, "OCR1BL: Timer/Counter1 Output Compare Register B Low byte." },
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{ 0x27, "ICR1H: Timer/Counter1 Input Capture Register High byte." },
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{ 0x26, "ICR1L: Timer/Counter1 Input Capture Register Low byte." },
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{ 0x25, "TCCR2: Timer/Counter2 Control Register (8 bits)." },
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{ 0x24, "TCNT2: Timer/Counter2 (8 bits)." },
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{ 0x23, "OCR2: Timer/Counter2 Output Compare Register." },
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{ 0x22, "ASSR: Asynchronous Operation of the Timer/Counter." },
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{ 0x21, "WDTCR: Watchdog Timer Control Register." },
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{ 0x20, "UBRRH, UCSRC: USART Baud Rate Registers, High byte and Control. A.k.a setting serial port speed." },
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{ 0x1f, "EEARH: EEPROM Address Register High byte." },
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{ 0x1e, "EEARL: EEPROM Address Register Low byte." },
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{ 0x1d, "EEDR: EEPROM Data Register." },
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{ 0x1c, "EECR: EEPROM Control Register." },
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{ 0x1b, "PORTA: Output pins/pullups address for port A." },
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{ 0x1a, "DDRA: Data Direction Register for Port A." },
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{ 0x19, "PINA: Input Pins Address for Port A." },
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{ 0x18, "PORTB: Output pins/pullups address for port B." },
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{ 0x17, "DDRB: Data Direction Register for Port B." },
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{ 0x16, "PINB: Input Pins Address for Port B." },
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{ 0x15, "PORTC: Output pins/pullups address for port C." },
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{ 0x14, "DDRC: Data Direction Register for Port C." },
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{ 0x13, "PINC: Input Pins Address for Port C." },
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{ 0x12, "PORTD: Output pins/pullups address for port D." },
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{ 0x11, "DDRD: Data Direction Register for Port D." },
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{ 0x10, "PIND: Input Pins Address for Port D." },
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{ 0x0f, "SPDR: SPI Data Register." },
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{ 0x0e, "SPSR: SPI Status Register." },
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{ 0x0d, "SPCR: SPI Control Register." },
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{ 0x0c, "UDR: USART I/O Data Register." },
|
||||
{ 0x0b, "UCSRA: USART Control and Status Register A." },
|
||||
{ 0x0a, "UCSRB: USART Control and Status Register B." },
|
||||
{ 0x09, "UBRRL: USART Baud Rate Registers Low byte. A.k.a setting serial port speed." },
|
||||
{ 0x08, "ACSR: Analog Comparator Control and Status Register." },
|
||||
{ 0x07, "ADMUX: ADC Multiplexer Selection Register." },
|
||||
{ 0x06, "ADCSRA: ADC Control and Status Register A." },
|
||||
{ 0x05, "ADCH: ADC Data Register High byte." },
|
||||
{ 0x04, "ADCL: ADC Data Register Low byte." },
|
||||
{ 0x03, "TWDR: I2C (Two-wire) Serial Interface Data Register." },
|
||||
{ 0x02, "TWAR: I2C (Two-wire) Serial Interface (Slave) Address Register." },
|
||||
{ 0x01, "TWSR: I2C (Two-wire) Serial Interface Status Register." },
|
||||
{ 0x00, "TWBR: I2C (Two-wire) Serial Interface Bit Rate Register." },
|
||||
{ 0, NULL }
|
||||
};
|
||||
|
|
@ -1,6 +1,5 @@
|
|||
rz_syscall_sources = [
|
||||
'syscall.c',
|
||||
'ioports.c'
|
||||
]
|
||||
|
||||
rz_syscall = library('rz_syscall', rz_syscall_sources,
|
||||
|
|
|
|||
|
|
@ -9,32 +9,63 @@
|
|||
|
||||
RZ_LIB_VERSION(rz_syscall);
|
||||
|
||||
// TODO: now we use sdb
|
||||
extern RzSyscallPort sysport_x86[];
|
||||
extern RzSyscallPort sysport_avr[];
|
||||
|
||||
RZ_API RzSyscall *rz_syscall_ref(RzSyscall *sc) {
|
||||
sc->refs++;
|
||||
return sc;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Creates a new RzSysregItem type
|
||||
*
|
||||
* \param name Name of the callable type
|
||||
*/
|
||||
RZ_API RZ_OWN RzSysregItem *rz_sysreg_item_new(RZ_NULLABLE const char *name) {
|
||||
RzSysregItem *sysregitem = RZ_NEW0(RzSysregItem);
|
||||
if (!sysregitem) {
|
||||
return NULL;
|
||||
}
|
||||
sysregitem->comment = NULL;
|
||||
sysregitem->type = NULL;
|
||||
sysregitem->name = name ? strdup(name) : NULL;
|
||||
return sysregitem;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Creates a new RzSysregDB type
|
||||
*/
|
||||
RZ_API RzSysregsDB *rz_sysregs_db_new() {
|
||||
RzSysregsDB *sysregdb = RZ_NEW0(RzSysregsDB);
|
||||
if (!sysregdb) {
|
||||
return NULL;
|
||||
}
|
||||
sysregdb->port = ht_up_new0();
|
||||
if (!sysregdb->port) {
|
||||
return NULL;
|
||||
}
|
||||
return sysregdb;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Creates a new RzSyscall type
|
||||
*/
|
||||
RZ_API RzSyscall *rz_syscall_new(void) {
|
||||
RzSyscall *rs = RZ_NEW0(RzSyscall);
|
||||
if (rs) {
|
||||
rs->sysport = sysport_x86;
|
||||
rs->srdb = sdb_new0(); // sysregs database
|
||||
rs->srdb = rz_sysregs_db_new(); // sysregs database
|
||||
rs->db = sdb_new0();
|
||||
}
|
||||
return rs;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Frees an RzSyscall type
|
||||
*/
|
||||
RZ_API void rz_syscall_free(RzSyscall *s) {
|
||||
if (s) {
|
||||
if (s->refs > 0) {
|
||||
s->refs--;
|
||||
return;
|
||||
}
|
||||
sdb_free(s->srdb);
|
||||
sdb_free(s->db);
|
||||
free(s->os);
|
||||
free(s->cpu);
|
||||
|
|
@ -43,6 +74,19 @@ RZ_API void rz_syscall_free(RzSyscall *s) {
|
|||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Frees an RzSysregItem type
|
||||
*/
|
||||
RZ_API void rz_sysreg_item_free(RzSysregItem *s) {
|
||||
if (!s) {
|
||||
return;
|
||||
}
|
||||
free(s->comment);
|
||||
free(s->name);
|
||||
free(s->type);
|
||||
free(s);
|
||||
}
|
||||
|
||||
static bool load_sdb(Sdb **db, const char *name) {
|
||||
rz_return_val_if_fail(db, false);
|
||||
char *sdb_path = rz_str_rz_prefix(RZ_SDB);
|
||||
|
|
@ -84,6 +128,83 @@ static inline bool sysregs_reload_needed(RzSyscall *s, const char *arch, int bit
|
|||
return !s->cpu || strcmp(s->cpu, cpu);
|
||||
}
|
||||
|
||||
static bool sdb_load_sysregs(RzSysregsDB *sysregdb, Sdb *sdb) {
|
||||
rz_return_val_if_fail(sysregdb && sdb, NULL);
|
||||
RzSysregItem *sysregitem;
|
||||
SdbKv *kv;
|
||||
SdbListIter *iter;
|
||||
SdbList *l = sdb_foreach_list(sdb, false);
|
||||
char *argument_key, *comment, *name;
|
||||
ls_foreach (l, iter, kv) {
|
||||
if (!strcmp(sdbkv_value(kv), "mmio") || !strcmp(sdbkv_value(kv), "reg")) {
|
||||
name = sdbkv_key(kv);
|
||||
sysregitem = rz_sysreg_item_new(name);
|
||||
argument_key = rz_str_newf("%s.address", name);
|
||||
|
||||
if (!argument_key) {
|
||||
return NULL;
|
||||
}
|
||||
ut64 address = sdb_num_get(sdb, argument_key, NULL);
|
||||
if (!address) {
|
||||
rz_sysreg_item_free(sysregitem);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
argument_key = rz_str_newf("%s.comment", name);
|
||||
comment = sdb_get(sdb, argument_key, NULL);
|
||||
sysregitem->type = sdbkv_value(kv);
|
||||
sysregitem->name = strdup(name);
|
||||
sysregitem->comment = strdup(comment);
|
||||
|
||||
ht_up_insert(sysregdb->port, address, sysregitem);
|
||||
}
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool sdb_load_by_path(RZ_NONNULL RzSysregsDB *sysregdb, const char *path) {
|
||||
Sdb *db = sdb_new(0, path, 0);
|
||||
bool result = sdb_load_sysregs(sysregdb, db);
|
||||
sdb_close(db);
|
||||
sdb_free(db);
|
||||
return result;
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Loads the RzSysregDB from the path to the hashtable
|
||||
*
|
||||
* \param s reference to RzSysregDB
|
||||
* \param path reference to path of the SDB file
|
||||
*/
|
||||
RZ_API bool rz_type_db_load_sysregs_sdb(RzSysregsDB *sysregdb, const char *path) {
|
||||
if (!rz_file_exists(path)) {
|
||||
return false;
|
||||
}
|
||||
return sdb_load_by_path(sysregdb, path);
|
||||
}
|
||||
|
||||
/**
|
||||
* \brief Sets the architecture for sysregs during analysis and
|
||||
* loads up the sysregs SDB database
|
||||
*
|
||||
* \param s reference to RzSyscall
|
||||
* \param arch reference to value of asm.arch
|
||||
* \param dir_prefix reference to value of directory prefix or the value of dir.prefix
|
||||
*/
|
||||
RZ_API bool rz_sysreg_set_arch(RzSyscall *s, const char *arch, const char *dir_prefix) {
|
||||
char *path = sdb_fmt(RZ_JOIN_4_PATHS("%s", RZ_SDB, "reg", "%s-%s-%d.sdb"), dir_prefix,
|
||||
arch, s->cpu, s->bits);
|
||||
|
||||
s->srdb = rz_sysregs_db_new();
|
||||
if (path) {
|
||||
if (!rz_type_db_load_sysregs_sdb(s->srdb, path)) {
|
||||
s->srdb = NULL;
|
||||
return false;
|
||||
}
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
// TODO: should be renamed to rz_syscall_use();
|
||||
RZ_API bool rz_syscall_setup(RzSyscall *s, const char *arch, int bits, const char *cpu, const char *os) {
|
||||
bool syscall_changed, sysregs_changed;
|
||||
|
|
@ -113,13 +234,8 @@ RZ_API bool rz_syscall_setup(RzSyscall *s, const char *arch, int bits, const cha
|
|||
|
||||
if (!strcmp(os, "any")) { // ignored
|
||||
return true;
|
||||
}
|
||||
if (!strcmp(arch, "avr")) {
|
||||
s->sysport = sysport_avr;
|
||||
} else if (!strcmp(os, "darwin") || !strcmp(os, "osx") || !strcmp(os, "macos")) {
|
||||
os = "darwin";
|
||||
} else if (!strcmp(arch, "x86")) {
|
||||
s->sysport = sysport_x86;
|
||||
}
|
||||
|
||||
if (syscall_changed) {
|
||||
|
|
@ -135,11 +251,10 @@ RZ_API bool rz_syscall_setup(RzSyscall *s, const char *arch, int bits, const cha
|
|||
}
|
||||
|
||||
if (sysregs_changed) {
|
||||
char *dbName = rz_str_newf(RZ_JOIN_2_PATHS("sysregs", "%s-%d-%s"),
|
||||
arch, bits, cpu);
|
||||
char *dbName = rz_str_newf(RZ_JOIN_2_PATHS("reg", "%s-%s-%d"),
|
||||
arch, cpu, bits);
|
||||
if (dbName) {
|
||||
if (!load_sdb(&s->srdb, dbName)) {
|
||||
sdb_free(s->srdb);
|
||||
if (!rz_type_db_load_sysregs_sdb(s->srdb, dbName)) {
|
||||
s->srdb = NULL;
|
||||
}
|
||||
free(dbName);
|
||||
|
|
@ -287,27 +402,21 @@ RZ_API RzList *rz_syscall_list(RzSyscall *s) {
|
|||
return list;
|
||||
}
|
||||
|
||||
/* io and sysregs */
|
||||
RZ_API const char *rz_syscall_get_io(RzSyscall *s, int ioport) {
|
||||
/**
|
||||
* \brief Searches the sysregs SDB database inside librz/reg/d for the type (mmio/reg) and
|
||||
* returns its value as a string
|
||||
*
|
||||
* \param s reference to RzSyscall
|
||||
* \param type reference to the type of key: mmio/reg
|
||||
* \param port reference to the io port
|
||||
*/
|
||||
RZ_API const char *rz_sysreg_get(RzSyscall *s, const char *type, ut64 port) {
|
||||
rz_return_val_if_fail(s, NULL);
|
||||
int i;
|
||||
const char *name = rz_syscall_sysreg(s, "io", ioport);
|
||||
if (name) {
|
||||
return name;
|
||||
}
|
||||
for (i = 0; s->sysport[i].name; i++) {
|
||||
if (ioport == s->sysport[i].port) {
|
||||
return s->sysport[i].name;
|
||||
}
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
RZ_API const char *rz_syscall_sysreg(RzSyscall *s, const char *type, ut64 num) {
|
||||
rz_return_val_if_fail(s, NULL);
|
||||
if (!s->db) {
|
||||
if (!s->srdb) {
|
||||
return NULL;
|
||||
}
|
||||
const char *key = sdb_fmt("%s,%" PFMT64d, type, num);
|
||||
return sdb_const_get(s->db, key, 0);
|
||||
RzSysregItem *item = ht_up_find(s->srdb->port, port, NULL);
|
||||
if (item)
|
||||
return item->comment;
|
||||
return NULL;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -541,6 +541,7 @@ subdir('librz/analysis/d')
|
|||
subdir('librz/asm/d')
|
||||
subdir('librz/bin/d')
|
||||
subdir('librz/syscall/d')
|
||||
subdir('librz/reg/d')
|
||||
subdir('librz/cons/d')
|
||||
subdir('librz/magic/d')
|
||||
subdir('librz/flag/d')
|
||||
|
|
|
|||
|
|
@ -64,9 +64,21 @@ RUN
|
|||
|
||||
NAME=avr DISasm: IO-Ports
|
||||
FILE=bins/firmware/arduino_avr.bin
|
||||
CMDS=pd 1 @ 0x00000170~?IO
|
||||
CMDS=pd 13 @ 0x00000282
|
||||
EXPECT=<<EOF
|
||||
1
|
||||
0x00000282 in r24, 0x12 ; IO Output pins/pullups address for port D
|
||||
0x00000284 subi r24, 0x80
|
||||
0x00000286 out 0x12, r24 ; IO Output pins/pullups address for port D
|
||||
0x00000288 ret
|
||||
0x0000028a ldi r22, 0x7d
|
||||
0x0000028c ldi r23, 0x01
|
||||
0x0000028e ldi r24, 0x2f
|
||||
0x00000290 ldi r25, 0x02
|
||||
0x00000292 call 0x8e6
|
||||
0x00000296 in r24, 0x18 ; IO Output pins/pullups address for port B
|
||||
0x00000298 subi r24, 0x80
|
||||
0x0000029a out 0x18, r24 ; IO Output pins/pullups address for port B
|
||||
0x0000029c ret
|
||||
EOF
|
||||
RUN
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue