Removing GNU tricore analysis and asm plugin
This commit is contained in:
billow
Anton Kochkov
parent
0cf4cd75b3
commit
b1ab2adf6e
10 changed files with 0 additions and 5347 deletions
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@ -56,7 +56,6 @@ if get_option('use_gpl')
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'riscv',
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'sh',
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'sparc_gnu',
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'tricore',
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'vax',
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'xtensa',
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'z80',
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@ -245,7 +244,6 @@ if get_option('use_gpl')
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'p/analysis_riscv.c',
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'p/analysis_sh.c',
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'p/analysis_sparc_gnu.c',
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'p/analysis_tricore.c',
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'p/analysis_vax.c',
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'p/analysis_xtensa.c',
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'p/analysis_z80.c',
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@ -1,92 +0,0 @@
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// SPDX-FileCopyrightText: 2020 curly <bhattrishi8@gmail.com>
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// SPDX-License-Identifier: LGPL-3.0-only
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#include <string.h>
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#include <rz_types.h>
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#include <rz_lib.h>
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#include <rz_asm.h>
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#include <rz_analysis.h>
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// #include "../../asm/arch/tricore/gnu/tricore-opc.c"
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static char *get_reg_profile(RzAnalysis *analysis) {
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const char *p =
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"=PC pc\n"
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"=SP a10\n"
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"=A0 a0\n"
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"gpr p0 .64 0 0\n"
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"gpr a0 .32 0 0\n"
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"gpr a1 .32 4 0\n"
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"gpr p2 .64 8 0\n"
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"gpr a2 .32 8 0\n"
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"gpr a3 .32 12 0\n"
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"gpr p4 .64 16 0\n"
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"gpr a4 .32 16 0\n"
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"gpr a5 .32 20 0\n"
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"gpr p6 .64 24 0\n"
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"gpr a6 .32 24 0\n"
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"gpr a7 .32 28 0\n"
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"gpr p8 .64 32 0\n"
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"gpr a8 .32 32 0\n"
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"gpr a9 .32 36 0\n"
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"gpr p10 .64 40 0\n"
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"gpr a10 .32 40 0\n"
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"gpr a11 .32 44 0\n"
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"gpr p12 .64 48 0\n"
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"gpr a12 .32 48 0\n"
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"gpr a13 .32 52 0\n"
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"gpr p14 .64 56 0\n"
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"gpr a14 .32 56 0\n"
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"gpr a15 .32 60 0\n"
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"gpr e0 .64 64 0\n"
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"gpr d0 .32 64 0\n"
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"gpr d1 .32 68 0\n"
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"gpr e2 .64 72 0\n"
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"gpr d2 .32 72 0\n"
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"gpr d3 .32 76 0\n"
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"gpr e4 .64 80 0\n"
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"gpr d4 .32 80 0\n"
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"gpr d5 .32 84 0\n"
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"gpr e6 .64 88 0\n"
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"gpr d6 .32 88 0\n"
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"gpr d7 .32 92 0\n"
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"gpr e8 .64 96 0\n"
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"gpr d8 .32 96 0\n"
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"gpr d9 .32 100 0\n"
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"gpr e10 .64 104 0\n"
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"gpr d10 .32 104 0\n"
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"gpr d11 .32 108 0\n"
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"gpr e12 .64 112 0\n"
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"gpr d12 .32 112 0\n"
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"gpr d13 .32 114 0\n"
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"gpr e14 .64 118 0\n"
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"gpr d14 .32 118 0\n"
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"gpr d15 .32 120 0\n"
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"gpr PSW .32 124 0\n"
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"gpr PCXI .32 128 0\n"
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"gpr FCX .32 132 0\n"
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"gpr LCX .32 136 0\n"
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"gpr ISP .32 140 0\n"
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"gpr ICR .32 144 0\n"
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"gpr PIPN .32 148 0\n"
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"gpr BIV .32 152 0\n"
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"gpr BTV .32 156 0\n"
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"gpr pc .32 160 0\n";
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return strdup(p);
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}
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RzAnalysisPlugin rz_analysis_plugin_tricore = {
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.name = "tricore",
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.desc = "TRICORE analysis plugin",
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.license = "LGPL3",
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.arch = "tricore",
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.bits = 32,
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.get_reg_profile = get_reg_profile,
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};
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#ifndef RZ_PLUGIN_INCORE
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RZ_API RzLibStruct rizin_plugin = {
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.type = RZ_LIB_TYPE_ANALYSIS,
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.data = &rz_analysis_plugin_tricore,
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.version = RZ_VERSION
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};
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#endif
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@ -1,445 +0,0 @@
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// SPDX-FileCopyrightText: 1998-2003 Free Software Foundation, Inc.
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// SPDX-License-Identifier: GPL-1.0-or-later
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/* Definitions dealing with TriCore/PCP opcodes and core registers.
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Copyright (C) 1998-2003 Free Software Foundation, Inc.
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Contributed by Michael Schumacher (mike@hightec-rt.com).
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This file is part of GDB, GAS, and the GNU binutils.
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GDB, GAS, and the GNU binutils are free software; you can redistribute
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them and/or modify them under the terms of the GNU General Public
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License as published by the Free Software Foundation; either version
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1, or (at your option) any later version.
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GDB, GAS, and the GNU binutils are distributed in the hope that they
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will be useful, but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
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the GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this file; see the file COPYING. If not, write to the Free
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Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
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02110-1335 USA
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*/
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/* Supported TriCore and PCP instruction set architectures. */
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typedef enum _tricore_opcode_arch_val {
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TRICORE_GENERIC = 0x00000000,
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TRICORE_RIDER_A = 0x00000001,
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TRICORE_RIDER_B = 0x00000002,
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TRICORE_RIDER_D = TRICORE_RIDER_B,
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TRICORE_V2 = 0x00000004,
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TRICORE_PCP = 0x00000010,
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TRICORE_PCP2 = 0x00000020
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} tricore_isa;
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#define bfd_mach_rider_a 0x0001
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#define bfd_mach_rider_b 0x0002
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#define bfd_mach_rider_c 0x0003
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#define bfd_mach_rider_2 0x0004
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#define bfd_mach_rider_d 0x0002
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#define bfd_mach_rider_mask 0x000f
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#define SEC_ARCH_BIT_0 0x008
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/* Some handy definitions for upward/downward compatibility of insns. */
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#define TRICORE_V2_UP TRICORE_V2
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#define TRICORE_RIDER_D_UP (TRICORE_RIDER_D | TRICORE_V2_UP)
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#define TRICORE_RIDER_B_UP (TRICORE_RIDER_B | TRICORE_RIDER_D_UP)
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#define TRICORE_RIDER_B_DN TRICORE_RIDER_B
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#define TRICORE_RIDER_D_DN (TRICORE_RIDER_D | TRICORE_RIDER_B_DN)
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#define TRICORE_V2_DN (TRICORE_V2 | TRICORE_RIDER_D_DN)
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/* The various instruction formats of the TriCore architecture. */
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typedef enum _tricore_fmt {
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/* 32-bit formats */
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TRICORE_FMT_ABS,
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TRICORE_FMT_ABSB,
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TRICORE_FMT_B,
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TRICORE_FMT_BIT,
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TRICORE_FMT_BO,
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TRICORE_FMT_BOL,
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TRICORE_FMT_BRC,
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TRICORE_FMT_BRN,
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TRICORE_FMT_BRR,
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TRICORE_FMT_RC,
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TRICORE_FMT_RCPW,
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TRICORE_FMT_RCR,
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TRICORE_FMT_RCRR,
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TRICORE_FMT_RCRW,
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TRICORE_FMT_RLC,
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TRICORE_FMT_RR,
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TRICORE_FMT_RR1,
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TRICORE_FMT_RR2,
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TRICORE_FMT_RRPW,
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TRICORE_FMT_RRR,
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TRICORE_FMT_RRR1,
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TRICORE_FMT_RRR2,
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TRICORE_FMT_RRRR,
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TRICORE_FMT_RRRW,
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TRICORE_FMT_SYS,
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/* 16-bit formats */
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TRICORE_FMT_SB,
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TRICORE_FMT_SBC,
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TRICORE_FMT_SBR,
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TRICORE_FMT_SBRN,
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TRICORE_FMT_SC,
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TRICORE_FMT_SLR,
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TRICORE_FMT_SLRO,
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TRICORE_FMT_SR,
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TRICORE_FMT_SRC,
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TRICORE_FMT_SRO,
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TRICORE_FMT_SRR,
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TRICORE_FMT_SRRS,
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TRICORE_FMT_SSR,
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TRICORE_FMT_SSRO,
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TRICORE_FMT_MAX /* Sentinel. */
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} tricore_fmt;
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#if defined(__STDC__) || defined(ALMOST_STDC)
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#define F(x) TRICORE_FMT_##x
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#elif defined(_MSC_VER)
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#define F(x) TRICORE_FMT_##x
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#else
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#define F(x) TRICORE_FMT_ /**/ x
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#endif
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/* Opcode masks for the instruction formats above. */
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extern unsigned long tricore_mask_abs;
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extern unsigned long tricore_mask_absb;
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extern unsigned long tricore_mask_b;
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extern unsigned long tricore_mask_bit;
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extern unsigned long tricore_mask_bo;
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extern unsigned long tricore_mask_bol;
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extern unsigned long tricore_mask_brc;
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extern unsigned long tricore_mask_brn;
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extern unsigned long tricore_mask_brr;
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extern unsigned long tricore_mask_rc;
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extern unsigned long tricore_mask_rcpw;
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extern unsigned long tricore_mask_rcr;
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extern unsigned long tricore_mask_rcrr;
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extern unsigned long tricore_mask_rcrw;
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extern unsigned long tricore_mask_rlc;
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extern unsigned long tricore_mask_rr;
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extern unsigned long tricore_mask_rr1;
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extern unsigned long tricore_mask_rr2;
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extern unsigned long tricore_mask_rrpw;
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extern unsigned long tricore_mask_rrr;
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extern unsigned long tricore_mask_rrr1;
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extern unsigned long tricore_mask_rrr2;
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extern unsigned long tricore_mask_rrrr;
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extern unsigned long tricore_mask_rrrw;
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extern unsigned long tricore_mask_sys;
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extern unsigned long tricore_mask_sb;
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extern unsigned long tricore_mask_sbc;
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extern unsigned long tricore_mask_sbr;
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extern unsigned long tricore_mask_sbrn;
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extern unsigned long tricore_mask_sc;
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extern unsigned long tricore_mask_slr;
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extern unsigned long tricore_mask_slro;
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extern unsigned long tricore_mask_sr;
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extern unsigned long tricore_mask_src;
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extern unsigned long tricore_mask_sro;
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extern unsigned long tricore_mask_srr;
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extern unsigned long tricore_mask_srrs;
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extern unsigned long tricore_mask_ssr;
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extern unsigned long tricore_mask_ssro;
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extern unsigned long tricore_opmask[];
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extern void tricore_init_arch_vars PARAMS((unsigned long));
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/* This structure describes TriCore opcodes. */
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struct tricore_opcode {
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const char *name; /* The opcode's mnemonic name. */
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const int len32; /* 1 if it's a 32-bit insn. */
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const unsigned long opcode; /* The binary code of this opcode. */
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const unsigned long lose; /* Mask for bits that must not be set. */
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const tricore_fmt format; /* The instruction format. */
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const int nr_operands; /* The number of operands. */
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const char *args; /* Kinds of operands (see below). */
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const char *fields; /* Where to put the operands (see below). */
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const tricore_isa isa; /* Instruction set architecture. */
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int insind; /* The insn's index (computed at runtime). */
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int inslast; /* Index of last insn w/ that name (dito). */
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};
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extern struct tricore_opcode tricore_opcodes[];
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extern const int tricore_numopcodes;
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extern unsigned long tricore_opmask[];
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/* This structure describes PCP/PCP2 opcodes. */
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struct pcp_opcode {
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const char *name; /* The opcode's mnemonic name. */
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const int len32; /* 1 if it's a 32-bit insn. */
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const unsigned long opcode; /* The binary code of this opcode. */
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const unsigned long lose; /* Mask for bits that must not be set. */
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const int fmt_group; /* The group ID of the instruction format. */
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const int ooo; /* 1 if operands may be given out of order. */
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const int nr_operands; /* The number of operands. */
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const char *args; /* Kinds of operands (see below), */
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const tricore_isa isa; /* PCP instruction set architecture. */
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int insind; /* The insn's index (computed at runtime). */
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int inslast; /* Index of last insn w/ that name (dito). */
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};
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extern struct pcp_opcode pcp_opcodes[];
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extern const int pcp_numopcodes;
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/* This structure describes TriCore core registers (SFRs). */
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struct tricore_core_register {
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const char *name; /* The name of the register ($-prepended). */
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const unsigned long addr; /* The memory address of the register. */
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const tricore_isa isa; /* Instruction set architecture. */
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};
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extern const struct tricore_core_register tricore_sfrs[];
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extern const int tricore_numsfrs;
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/* Kinds of operands for TriCore instructions:
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d A simple data register (%d0-%d15).
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g A simple data register with an 'l' suffix.
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G A simple data register with an 'u' suffix.
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- A simple data register with an 'll' suffix.
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+ A simple data register with an 'uu' suffix.
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l A simple data register with an 'lu' suffix.
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L A simple data register with an 'ul' suffix.
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D An extended data register (d-register pair; %e0, %e2, ..., %e14).
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i Implicit data register %d15.
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a A simple address register (%a0-%a15).
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A An extended address register (a-register pair; %a0, %a2, ..., %a14).
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I Implicit address register %a15.
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P Implicit stack register %a10.
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c A core register ($psw, $pc etc.).
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1 A 1-bit zero-extended constant.
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2 A 2-bit zero-extended constant.
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3 A 3-bit zero-extended constant.
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4 A 4-bit sign-extended constant.
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f A 4-bit zero-extended constant.
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5 A 5-bit zero-extended constant.
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F A 5-bit sign-extended constant.
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v A 5-bit zero-extended constant with bit 0 == 0 (=> 4bit/2).
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6 A 6-bit zero-extended constant with bits 0,1 == 0 (=> 4bit/4).
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8 A 8-bit zero-extended constant.
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9 A 9-bit sign-extended constant.
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n A 9-bit zero-extended constant.
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k A 10-bit zero-extended constant with bits 0,1 == 0 (=> 8bit/4).
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0 A 10-bit sign-extended constant.
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q A 15-bit zero-extended constant.
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w A 16-bit sign-extended constant.
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W A 16-bit zero-extended constant.
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M A 32-bit memory address.
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m A 4-bit PC-relative offset (zero-extended, /2).
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r A 4-bit PC-relative offset (one-extended, /2).
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x A 5-bit PC-relative offset (zero-extended, /2).
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R A 8-bit PC-relative offset (sign-extended, /2).
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o A 15-bit PC-relative offset (sign-extended, /2).
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O A 24-bit PC-relative offset (sign-extended, /2).
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t A 18-bit absolute memory address (segmented).
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T A 24-bit absolute memory address (segmented, /2).
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U A symbol whose value isn't known yet.
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@ Register indirect ([%an]).
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& SP indirect ([%sp] or [%a10]).
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< Pre-incremented register indirect ([+%an]).
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> Post-incremented register indirect ([%an+]).
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* Circular address mode ([%An+c]).
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# Bitreverse address mode ([%An+r]).
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? Indexed address mode ([%An+i]).
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S Implicit base ([%a15]).
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*/
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/* The instruction fields where operands are stored. */
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#define FMT_ABS_NONE '0'
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#define FMT_ABS_OFF18 '1'
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#define FMT_ABS_S1_D '2'
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#define FMT_ABSB_NONE '0'
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#define FMT_ABSB_OFF18 '1'
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#define FMT_ABSB_B '2'
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#define FMT_ABSB_BPOS3 '3'
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#define FMT_B_NONE '0'
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#define FMT_B_DISP24 '1'
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#define FMT_BIT_NONE '0'
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#define FMT_BIT_D '1'
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#define FMT_BIT_P2 '2'
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#define FMT_BIT_P1 '3'
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#define FMT_BIT_S2 '4'
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#define FMT_BIT_S1 '5'
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#define FMT_BO_NONE '0'
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#define FMT_BO_OFF10 '1'
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#define FMT_BO_S2 '2'
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#define FMT_BO_S1_D '3'
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#define FMT_BOL_NONE '0'
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#define FMT_BOL_OFF16 '1'
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#define FMT_BOL_S2 '2'
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#define FMT_BOL_S1_D '3'
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#define FMT_BRC_NONE '0'
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#define FMT_BRC_DISP15 '1'
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#define FMT_BRC_CONST4 '2'
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#define FMT_BRC_S1 '3'
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#define FMT_BRN_NONE '0'
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#define FMT_BRN_DISP15 '1'
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#define FMT_BRN_N '2'
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#define FMT_BRN_S1 '3'
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#define FMT_BRR_NONE '0'
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#define FMT_BRR_DISP15 '1'
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#define FMT_BRR_S2 '2'
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#define FMT_BRR_S1 '3'
|
||||
#define FMT_RC_NONE '0'
|
||||
#define FMT_RC_D '1'
|
||||
#define FMT_RC_CONST9 '2'
|
||||
#define FMT_RC_S1 '3'
|
||||
#define FMT_RCPW_NONE '0'
|
||||
#define FMT_RCPW_D '1'
|
||||
#define FMT_RCPW_P '2'
|
||||
#define FMT_RCPW_W '3'
|
||||
#define FMT_RCPW_CONST4 '4'
|
||||
#define FMT_RCPW_S1 '5'
|
||||
#define FMT_RCR_NONE '0'
|
||||
#define FMT_RCR_D '1'
|
||||
#define FMT_RCR_S3 '2'
|
||||
#define FMT_RCR_CONST9 '3'
|
||||
#define FMT_RCR_S1 '4'
|
||||
#define FMT_RCRR_NONE '0'
|
||||
#define FMT_RCRR_D '1'
|
||||
#define FMT_RCRR_S3 '2'
|
||||
#define FMT_RCRR_CONST4 '3'
|
||||
#define FMT_RCRR_S1 '4'
|
||||
#define FMT_RCRW_NONE '0'
|
||||
#define FMT_RCRW_D '1'
|
||||
#define FMT_RCRW_S3 '2'
|
||||
#define FMT_RCRW_W '3'
|
||||
#define FMT_RCRW_CONST4 '4'
|
||||
#define FMT_RCRW_S1 '5'
|
||||
#define FMT_RLC_NONE '0'
|
||||
#define FMT_RLC_D '1'
|
||||
#define FMT_RLC_CONST16 '2'
|
||||
#define FMT_RLC_S1 '3'
|
||||
#define FMT_RR_NONE '0'
|
||||
#define FMT_RR_D '1'
|
||||
#define FMT_RR_N '2'
|
||||
#define FMT_RR_S2 '3'
|
||||
#define FMT_RR_S1 '4'
|
||||
#define FMT_RR1_NONE '0'
|
||||
#define FMT_RR1_D '1'
|
||||
#define FMT_RR1_N '2'
|
||||
#define FMT_RR1_S2 '3'
|
||||
#define FMT_RR1_S1 '4'
|
||||
#define FMT_RR2_NONE '0'
|
||||
#define FMT_RR2_D '1'
|
||||
#define FMT_RR2_S2 '2'
|
||||
#define FMT_RR2_S1 '3'
|
||||
#define FMT_RRPW_NONE '0'
|
||||
#define FMT_RRPW_D '1'
|
||||
#define FMT_RRPW_P '2'
|
||||
#define FMT_RRPW_W '3'
|
||||
#define FMT_RRPW_S2 '4'
|
||||
#define FMT_RRPW_S1 '5'
|
||||
#define FMT_RRR_NONE '0'
|
||||
#define FMT_RRR_D '1'
|
||||
#define FMT_RRR_S3 '2'
|
||||
#define FMT_RRR_N '3'
|
||||
#define FMT_RRR_S2 '4'
|
||||
#define FMT_RRR_S1 '5'
|
||||
#define FMT_RRR1_NONE '0'
|
||||
#define FMT_RRR1_D '1'
|
||||
#define FMT_RRR1_S3 '2'
|
||||
#define FMT_RRR1_N '3'
|
||||
#define FMT_RRR1_S2 '4'
|
||||
#define FMT_RRR1_S1 '5'
|
||||
#define FMT_RRR2_NONE '0'
|
||||
#define FMT_RRR2_D '1'
|
||||
#define FMT_RRR2_S3 '2'
|
||||
#define FMT_RRR2_S2 '3'
|
||||
#define FMT_RRR2_S1 '4'
|
||||
#define FMT_RRRR_NONE '0'
|
||||
#define FMT_RRRR_D '1'
|
||||
#define FMT_RRRR_S3 '2'
|
||||
#define FMT_RRRR_S2 '3'
|
||||
#define FMT_RRRR_S1 '4'
|
||||
#define FMT_RRRW_NONE '0'
|
||||
#define FMT_RRRW_D '1'
|
||||
#define FMT_RRRW_S3 '2'
|
||||
#define FMT_RRRW_W '3'
|
||||
#define FMT_RRRW_S2 '4'
|
||||
#define FMT_RRRW_S1 '5'
|
||||
#define FMT_SYS_NONE '0'
|
||||
#define FMT_SYS_S1_D '1'
|
||||
#define FMT_SB_NONE '0'
|
||||
#define FMT_SB_DISP8 '1'
|
||||
#define FMT_SBC_NONE '0'
|
||||
#define FMT_SBC_CONST4 '1'
|
||||
#define FMT_SBC_DISP4 '2'
|
||||
#define FMT_SBR_NONE '0'
|
||||
#define FMT_SBR_S2 '1'
|
||||
#define FMT_SBR_DISP4 '2'
|
||||
#define FMT_SBRN_NONE '0'
|
||||
#define FMT_SBRN_N '1'
|
||||
#define FMT_SBRN_DISP4 '2'
|
||||
#define FMT_SC_NONE '0'
|
||||
#define FMT_SC_CONST8 '1'
|
||||
#define FMT_SLR_NONE '0'
|
||||
#define FMT_SLR_S2 '1'
|
||||
#define FMT_SLR_D '2'
|
||||
#define FMT_SLRO_NONE '0'
|
||||
#define FMT_SLRO_OFF4 '1'
|
||||
#define FMT_SLRO_D '2'
|
||||
#define FMT_SR_NONE '0'
|
||||
#define FMT_SR_S1_D '1'
|
||||
#define FMT_SRC_NONE '0'
|
||||
#define FMT_SRC_CONST4 '1'
|
||||
#define FMT_SRC_S1_D '2'
|
||||
#define FMT_SRO_NONE '0'
|
||||
#define FMT_SRO_S2 '1'
|
||||
#define FMT_SRO_OFF4 '2'
|
||||
#define FMT_SRR_NONE '0'
|
||||
#define FMT_SRR_S2 '1'
|
||||
#define FMT_SRR_S1_D '2'
|
||||
#define FMT_SRRS_NONE '0'
|
||||
#define FMT_SRRS_S2 '1'
|
||||
#define FMT_SRRS_S1_D '2'
|
||||
#define FMT_SRRS_N '3'
|
||||
#define FMT_SSR_NONE '0'
|
||||
#define FMT_SSR_S2 '1'
|
||||
#define FMT_SSR_S1 '2'
|
||||
#define FMT_SSRO_NONE '0'
|
||||
#define FMT_SSRO_OFF4 '1'
|
||||
#define FMT_SSRO_S1 '2'
|
||||
|
||||
/* Kinds of operands for PCP instructions:
|
||||
a Condition code 0-7 (CONDCA).
|
||||
b Condition code 8-15 (CONDCB).
|
||||
c CNC=[0,1,2].
|
||||
d DST{+,-}.
|
||||
e A constant expression.
|
||||
E An indirect constant expression.
|
||||
f SIZE=[8,16,32].
|
||||
g ST=[0,1].
|
||||
h EC=[0,1].
|
||||
i INT=[0,1].
|
||||
j EP=[0,1].
|
||||
k SET (const value 1).
|
||||
l CLR (const value 0).
|
||||
m DAC=[0,1].
|
||||
n CNT0=[1..8] for COPY, or [2,4,8] for BCOPY.
|
||||
o RTA=[0,1].
|
||||
p EDA=[0,1].
|
||||
q SDB=[0,1].
|
||||
r A direct register (R0-R7).
|
||||
R An indirect register ([R0]-[R7]).
|
||||
s SRC{+,-}.
|
||||
u A direct symbol whose value isn't known yet.
|
||||
U An indirect symbol whose value isn't known yet.
|
||||
*/
|
||||
|
||||
/* End of tricore.h. */
|
||||
|
|
@ -1,312 +0,0 @@
|
|||
/* BFD support for Infineon's TriCore architecture.
|
||||
Copyright (C) 1998-2003 Free Software Foundation, Inc.
|
||||
Contributed by Michael Schumacher (mike@hightec-rt.com).
|
||||
|
||||
This file is part of BFD, the Binary File Descriptor library.
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335 USA */
|
||||
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <sys/types.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
// #include "bfd.h"
|
||||
#include "sysdep.h"
|
||||
#include "disas-asm.h"
|
||||
// #include "libbfd.h"
|
||||
#include "opcode/tricore.h"
|
||||
|
||||
/* Opcode masks for TriCore's various instruction formats. */
|
||||
|
||||
unsigned long tricore_mask_abs;
|
||||
unsigned long tricore_mask_absb;
|
||||
unsigned long tricore_mask_b;
|
||||
unsigned long tricore_mask_bit;
|
||||
unsigned long tricore_mask_bo;
|
||||
unsigned long tricore_mask_bol;
|
||||
unsigned long tricore_mask_brc;
|
||||
unsigned long tricore_mask_brn;
|
||||
unsigned long tricore_mask_brr;
|
||||
unsigned long tricore_mask_rc;
|
||||
unsigned long tricore_mask_rcpw;
|
||||
unsigned long tricore_mask_rcr;
|
||||
unsigned long tricore_mask_rcrr;
|
||||
unsigned long tricore_mask_rcrw;
|
||||
unsigned long tricore_mask_rlc;
|
||||
unsigned long tricore_mask_rr;
|
||||
unsigned long tricore_mask_rr1;
|
||||
unsigned long tricore_mask_rr2;
|
||||
unsigned long tricore_mask_rrpw;
|
||||
unsigned long tricore_mask_rrr;
|
||||
unsigned long tricore_mask_rrr1;
|
||||
unsigned long tricore_mask_rrr2;
|
||||
unsigned long tricore_mask_rrrr;
|
||||
unsigned long tricore_mask_rrrw;
|
||||
unsigned long tricore_mask_sys;
|
||||
unsigned long tricore_mask_sb;
|
||||
unsigned long tricore_mask_sbc;
|
||||
unsigned long tricore_mask_sbr;
|
||||
unsigned long tricore_mask_sbrn;
|
||||
unsigned long tricore_mask_sc;
|
||||
unsigned long tricore_mask_slr;
|
||||
unsigned long tricore_mask_slro;
|
||||
unsigned long tricore_mask_sr;
|
||||
unsigned long tricore_mask_src;
|
||||
unsigned long tricore_mask_sro;
|
||||
unsigned long tricore_mask_srr;
|
||||
unsigned long tricore_mask_srrs;
|
||||
unsigned long tricore_mask_ssr;
|
||||
unsigned long tricore_mask_ssro;
|
||||
unsigned long tricore_opmask[TRICORE_FMT_MAX];
|
||||
|
||||
static int
|
||||
bfd_default_scan(const bfd_arch_info_type *info, const char *string) {
|
||||
return true;
|
||||
}
|
||||
|
||||
static const bfd_arch_info_type *
|
||||
bfd_default_compatible(const bfd_arch_info_type *a,
|
||||
const bfd_arch_info_type *b) {
|
||||
if (a->arch != b->arch) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (a->bits_per_word != b->bits_per_word) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
if (a->mach > b->mach) {
|
||||
return a;
|
||||
}
|
||||
|
||||
if (b->mach > a->mach) {
|
||||
return b;
|
||||
}
|
||||
|
||||
return a;
|
||||
}
|
||||
|
||||
void tricore_init_arch_vars PARAMS((unsigned long));
|
||||
|
||||
/* Describe the various flavours of the TriCore architecture. */
|
||||
|
||||
static const bfd_arch_info_type arch_info_struct[] = {
|
||||
/* Rider-A ISA. */
|
||||
{
|
||||
32, /* 32 bits per word. */
|
||||
32, /* 32 bits per address. */
|
||||
8, /* 8 bits per byte. */
|
||||
bfd_arch_tricore, /* Architecture type. */
|
||||
bfd_mach_rider_a, /* Machine type. */
|
||||
"tricore", /* Name of architecture (internal use). */
|
||||
"TriCore:Rider-A", /* Name of architecture to print. */
|
||||
3, /* Align sections on 8 byte boundaries. */
|
||||
false, /* No, this is ain't the default arch type. */
|
||||
bfd_default_compatible, /* We're compatible with ourselves. */
|
||||
bfd_default_scan, /* Let BFD find the default arch. */
|
||||
&arch_info_struct[1] /* Next TriCore architecture. */
|
||||
},
|
||||
|
||||
/* Rider-D ISA. */
|
||||
{
|
||||
32, /* 32 bits per word. */
|
||||
32, /* 32 bits per address. */
|
||||
8, /* 8 bits per byte. */
|
||||
bfd_arch_tricore, /* Architecture type. */
|
||||
bfd_mach_rider_d, /* Machine type. */
|
||||
"tricore", /* Name of architecture (internal use). */
|
||||
"TriCore:Rider-D", /* Name of architecture to print. */
|
||||
3, /* Align sections on 8 byte boundaries. */
|
||||
false, /* No, this is ain't the default arch type. */
|
||||
bfd_default_compatible, /* We're compatible with ourselves. */
|
||||
bfd_default_scan, /* Let BFD find the default arch. */
|
||||
&arch_info_struct[2] /* Next TriCore architecture. */
|
||||
},
|
||||
|
||||
/* TriCore V2 ISA. */
|
||||
{
|
||||
32, /* 32 bits per word. */
|
||||
32, /* 32 bits per address. */
|
||||
8, /* 8 bits per byte. */
|
||||
bfd_arch_tricore, /* Architecture type. */
|
||||
bfd_mach_rider_2, /* Machine type. */
|
||||
"tricore", /* Name of architecture (internal use). */
|
||||
"TriCore:V2", /* Name of architecture to print. */
|
||||
3, /* Align sections on 8 byte boundaries. */
|
||||
false, /* No, this is ain't the default arch type. */
|
||||
bfd_default_compatible, /* We're compatible with ourselves. */
|
||||
bfd_default_scan, /* Let BFD find the default arch. */
|
||||
(bfd_arch_info_type *)0 /* No more arch types for TriCore. */
|
||||
}
|
||||
};
|
||||
|
||||
const bfd_arch_info_type bfd_tricore_arch = {
|
||||
/* Rider-B ISA. */
|
||||
32, /* 32 bits per word. */
|
||||
32, /* 32 bits per address. */
|
||||
8, /* 8 bits per byte. */
|
||||
bfd_arch_tricore, /* Architecture type. */
|
||||
bfd_mach_rider_b, /* Machine type. */
|
||||
"tricore", /* Name of architecture (internal use). */
|
||||
"TriCore:Rider-B", /* Name of architecture to print. */
|
||||
3, /* Align sections on 8 byte boundaries. */
|
||||
true, /* Yes, this is the default arch type. */
|
||||
bfd_default_compatible, /* We're compatible with ourselves. */
|
||||
bfd_default_scan, /* Let BFD find the default arch. */
|
||||
&arch_info_struct[0] /* Next arch type for TriCore. */
|
||||
};
|
||||
|
||||
/* Initialize the architecture-specific variables. This must be called
|
||||
by the assembler and disassembler prior to encoding/decoding any
|
||||
TriCore instructions; the linker (or more precisely, the specific
|
||||
back-end, bfd/elf32-tricore.c:tricore_elf32_relocate_section) will
|
||||
also have to call this if it ever accesses the variables below, but
|
||||
it currently doesn't. */
|
||||
|
||||
void tricore_init_arch_vars(unsigned long mach) {
|
||||
switch (mach & bfd_mach_rider_mask) {
|
||||
case bfd_mach_rider_a:
|
||||
tricore_mask_abs = 0x0c0000ff;
|
||||
tricore_mask_absb = 0x0c0000ff;
|
||||
tricore_mask_b = 0x000000ff;
|
||||
tricore_mask_bit = 0x006000ff;
|
||||
tricore_mask_bo = 0x0fc000ff;
|
||||
tricore_mask_bol = 0x000000ff;
|
||||
tricore_mask_brc = 0x800000ff;
|
||||
tricore_mask_brn = 0x8000007f;
|
||||
tricore_mask_brr = 0x800000ff;
|
||||
tricore_mask_rc = 0x0fe000ff;
|
||||
tricore_mask_rcpw = 0x006000ff;
|
||||
tricore_mask_rcr = 0x00e000ff;
|
||||
tricore_mask_rcrr = 0x00e000ff;
|
||||
tricore_mask_rcrw = 0x00e000ff;
|
||||
tricore_mask_rlc = 0x000000ff;
|
||||
tricore_mask_rr = 0x0ff000ff;
|
||||
tricore_mask_rrpw = 0x006000ff;
|
||||
tricore_mask_rrr = 0x00f000ff;
|
||||
tricore_mask_rrr1 = 0x00fc00ff;
|
||||
tricore_mask_rrr2 = 0x00ff00ff;
|
||||
tricore_mask_rrrr = 0x00e000ff;
|
||||
tricore_mask_rrrw = 0x00e000ff;
|
||||
tricore_mask_sys = 0x07c000ff;
|
||||
tricore_mask_sb = 0x00ff;
|
||||
tricore_mask_sbc = 0x00ff;
|
||||
tricore_mask_sbr = 0x00ff;
|
||||
tricore_mask_sbrn = 0x007f;
|
||||
tricore_mask_sc = 0x00ff;
|
||||
tricore_mask_slr = 0x00ff;
|
||||
tricore_mask_slro = 0x00ff;
|
||||
tricore_mask_sr = 0xf0ff;
|
||||
tricore_mask_src = 0x00ff;
|
||||
tricore_mask_sro = 0x00ff;
|
||||
tricore_mask_srr = 0x00ff;
|
||||
tricore_mask_srrs = 0x003f;
|
||||
tricore_mask_ssr = 0x00ff;
|
||||
tricore_mask_ssro = 0x00ff;
|
||||
break;
|
||||
|
||||
case bfd_mach_rider_b: /* Same as bfd_mach_rider_d! */
|
||||
case bfd_mach_rider_2:
|
||||
tricore_mask_abs = 0x0c0000ff;
|
||||
tricore_mask_absb = 0x0c0000ff;
|
||||
tricore_mask_b = 0x000000ff;
|
||||
tricore_mask_bit = 0x006000ff;
|
||||
tricore_mask_bo = 0x0fc000ff;
|
||||
tricore_mask_bol = 0x000000ff;
|
||||
tricore_mask_brc = 0x800000ff;
|
||||
tricore_mask_brn = 0x8000007f;
|
||||
tricore_mask_brr = 0x800000ff;
|
||||
tricore_mask_rc = 0x0fe000ff;
|
||||
tricore_mask_rcpw = 0x006000ff;
|
||||
tricore_mask_rcr = 0x00e000ff;
|
||||
tricore_mask_rcrr = 0x00e000ff;
|
||||
tricore_mask_rcrw = 0x00e000ff;
|
||||
tricore_mask_rlc = 0x000000ff;
|
||||
tricore_mask_rr = 0x0ff300ff;
|
||||
tricore_mask_rr1 = 0x0ffc00ff;
|
||||
tricore_mask_rr2 = 0x0fff00ff;
|
||||
tricore_mask_rrpw = 0x006000ff;
|
||||
tricore_mask_rrr = 0x00f300ff;
|
||||
tricore_mask_rrr1 = 0x00fc00ff;
|
||||
tricore_mask_rrr2 = 0x00ff00ff;
|
||||
tricore_mask_rrrr = 0x00e000ff;
|
||||
tricore_mask_rrrw = 0x00e000ff;
|
||||
if ((mach & bfd_mach_rider_mask) == bfd_mach_rider_2) {
|
||||
tricore_mask_sys = 0x0fc000ff;
|
||||
} else {
|
||||
tricore_mask_sys = 0x07c000ff;
|
||||
}
|
||||
tricore_mask_sb = 0x00ff;
|
||||
tricore_mask_sbc = 0x00ff;
|
||||
tricore_mask_sbr = 0x00ff;
|
||||
tricore_mask_sbrn = 0x00ff;
|
||||
tricore_mask_sc = 0x00ff;
|
||||
tricore_mask_slr = 0x00ff;
|
||||
tricore_mask_slro = 0x00ff;
|
||||
tricore_mask_sr = 0xf0ff;
|
||||
tricore_mask_src = 0x00ff;
|
||||
tricore_mask_sro = 0x00ff;
|
||||
tricore_mask_srr = 0x00ff;
|
||||
tricore_mask_srrs = 0x003f;
|
||||
tricore_mask_ssr = 0x00ff;
|
||||
tricore_mask_ssro = 0x00ff;
|
||||
break;
|
||||
}
|
||||
|
||||
/* Now fill in tricore_opmask[]. */
|
||||
|
||||
tricore_opmask[TRICORE_FMT_ABS] = tricore_mask_abs;
|
||||
tricore_opmask[TRICORE_FMT_ABSB] = tricore_mask_absb;
|
||||
tricore_opmask[TRICORE_FMT_B] = tricore_mask_b;
|
||||
tricore_opmask[TRICORE_FMT_BIT] = tricore_mask_bit;
|
||||
tricore_opmask[TRICORE_FMT_BO] = tricore_mask_bo;
|
||||
tricore_opmask[TRICORE_FMT_BOL] = tricore_mask_bol;
|
||||
tricore_opmask[TRICORE_FMT_BRC] = tricore_mask_brc;
|
||||
tricore_opmask[TRICORE_FMT_BRN] = tricore_mask_brn;
|
||||
tricore_opmask[TRICORE_FMT_BRR] = tricore_mask_brr;
|
||||
tricore_opmask[TRICORE_FMT_RC] = tricore_mask_rc;
|
||||
tricore_opmask[TRICORE_FMT_RCPW] = tricore_mask_rcpw;
|
||||
tricore_opmask[TRICORE_FMT_RCR] = tricore_mask_rcr;
|
||||
tricore_opmask[TRICORE_FMT_RCRR] = tricore_mask_rcrr;
|
||||
tricore_opmask[TRICORE_FMT_RCRW] = tricore_mask_rcrw;
|
||||
tricore_opmask[TRICORE_FMT_RLC] = tricore_mask_rlc;
|
||||
tricore_opmask[TRICORE_FMT_RR] = tricore_mask_rr;
|
||||
tricore_opmask[TRICORE_FMT_RR1] = tricore_mask_rr1;
|
||||
tricore_opmask[TRICORE_FMT_RR2] = tricore_mask_rr2;
|
||||
tricore_opmask[TRICORE_FMT_RRPW] = tricore_mask_rrpw;
|
||||
tricore_opmask[TRICORE_FMT_RRR] = tricore_mask_rrr;
|
||||
tricore_opmask[TRICORE_FMT_RRR1] = tricore_mask_rrr1;
|
||||
tricore_opmask[TRICORE_FMT_RRR2] = tricore_mask_rrr2;
|
||||
tricore_opmask[TRICORE_FMT_RRRR] = tricore_mask_rrrr;
|
||||
tricore_opmask[TRICORE_FMT_RRRW] = tricore_mask_rrrw;
|
||||
tricore_opmask[TRICORE_FMT_SYS] = tricore_mask_sys;
|
||||
tricore_opmask[TRICORE_FMT_SB] = tricore_mask_sb;
|
||||
tricore_opmask[TRICORE_FMT_SBC] = tricore_mask_sbc;
|
||||
tricore_opmask[TRICORE_FMT_SBR] = tricore_mask_sbr;
|
||||
tricore_opmask[TRICORE_FMT_SBRN] = tricore_mask_sbrn;
|
||||
tricore_opmask[TRICORE_FMT_SC] = tricore_mask_sc;
|
||||
tricore_opmask[TRICORE_FMT_SLR] = tricore_mask_slr;
|
||||
tricore_opmask[TRICORE_FMT_SLRO] = tricore_mask_slro;
|
||||
tricore_opmask[TRICORE_FMT_SR] = tricore_mask_sr;
|
||||
tricore_opmask[TRICORE_FMT_SRC] = tricore_mask_src;
|
||||
tricore_opmask[TRICORE_FMT_SRO] = tricore_mask_sro;
|
||||
tricore_opmask[TRICORE_FMT_SRR] = tricore_mask_srr;
|
||||
tricore_opmask[TRICORE_FMT_SRRS] = tricore_mask_srrs;
|
||||
tricore_opmask[TRICORE_FMT_SSR] = tricore_mask_ssr;
|
||||
tricore_opmask[TRICORE_FMT_SSRO] = tricore_mask_ssro;
|
||||
}
|
||||
|
||||
/* End of cpu-tricore.c. */
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -68,7 +68,6 @@ if get_option('use_gpl')
|
|||
'nios2',
|
||||
'riscv',
|
||||
'sparc_gnu',
|
||||
'tricore',
|
||||
'vax',
|
||||
'xtensa',
|
||||
'z80',
|
||||
|
|
@ -263,9 +262,6 @@ if get_option('use_gpl')
|
|||
#'arch/riscv/riscv.c',
|
||||
'arch/sparc/gnu/sparc-dis.c',
|
||||
'arch/sparc/gnu/sparc-opc.c',
|
||||
'arch/tricore/gnu/cpu-tricore.c',
|
||||
'arch/tricore/gnu/tricore-dis.c',
|
||||
'arch/tricore/gnu/tricore-opc.c',
|
||||
'arch/vax/vax-dis.c',
|
||||
'arch/xtensa/gnu/elf32-xtensa.c',
|
||||
'arch/xtensa/gnu/xtensa-dis.c',
|
||||
|
|
@ -281,7 +277,6 @@ if get_option('use_gpl')
|
|||
'p/asm_nios2.c',
|
||||
'p/asm_riscv.c',
|
||||
'p/asm_sparc_gnu.c',
|
||||
'p/asm_tricore.c',
|
||||
'p/asm_vax.c',
|
||||
'p/asm_xtensa.c',
|
||||
'p/asm_z80.c',
|
||||
|
|
|
|||
|
|
@ -1,115 +0,0 @@
|
|||
// SPDX-FileCopyrightText: 2016 pancake <pancake@nopcode.org>
|
||||
// SPDX-License-Identifier: LGPL-3.0-only
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdarg.h>
|
||||
#include <string.h>
|
||||
|
||||
#include <rz_types.h>
|
||||
#include <rz_lib.h>
|
||||
#include <rz_util.h>
|
||||
#include <rz_asm.h>
|
||||
|
||||
#include "disas-asm.h"
|
||||
|
||||
static unsigned long Offset = 0;
|
||||
static RzStrBuf *buf_global = NULL;
|
||||
static ut8 bytes[128];
|
||||
enum {
|
||||
TRICORE_GENERIC = 0x00000000,
|
||||
TRICORE_RIDER_A = 0x00000001,
|
||||
TRICORE_RIDER_B = 0x00000002,
|
||||
TRICORE_RIDER_D = TRICORE_RIDER_B,
|
||||
TRICORE_V2 = 0x00000004,
|
||||
TRICORE_PCP = 0x00000010,
|
||||
TRICORE_PCP2 = 0x00000020
|
||||
};
|
||||
|
||||
static int cpu_to_mach(char *cpu_type) {
|
||||
if (cpu_type && *cpu_type) {
|
||||
if (!strcmp(cpu_type, "generic")) {
|
||||
return TRICORE_GENERIC;
|
||||
}
|
||||
if (!strcmp(cpu_type, "rider-a")) {
|
||||
return TRICORE_RIDER_A;
|
||||
}
|
||||
if ((!strcmp(cpu_type, "rider-b")) || (!strcmp(cpu_type, "rider-d"))) {
|
||||
return TRICORE_RIDER_B;
|
||||
}
|
||||
if (!strcmp(cpu_type, "v2")) {
|
||||
return TRICORE_V2;
|
||||
}
|
||||
if (!strcmp(cpu_type, "pcp")) {
|
||||
return TRICORE_PCP;
|
||||
}
|
||||
if (!strcmp(cpu_type, "pcp2")) {
|
||||
return TRICORE_PCP2;
|
||||
}
|
||||
}
|
||||
return TRICORE_RIDER_B;
|
||||
}
|
||||
|
||||
static int tricore_buffer_read_memory(bfd_vma memaddr, bfd_byte *myaddr, ut32 length, struct disassemble_info *info) {
|
||||
int delta = memaddr - Offset;
|
||||
if (delta >= 0 && length + delta < sizeof(bytes)) {
|
||||
memcpy(myaddr, bytes + delta, length);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int symbol_at_address(bfd_vma addr, struct disassemble_info *info) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void memory_error_func(int status, bfd_vma memaddr, struct disassemble_info *info) {
|
||||
//--
|
||||
}
|
||||
|
||||
DECLARE_GENERIC_PRINT_ADDRESS_FUNC()
|
||||
DECLARE_GENERIC_FPRINTF_FUNC()
|
||||
|
||||
static int disassemble(RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) {
|
||||
struct disassemble_info disasm_obj;
|
||||
buf_global = &op->buf_asm;
|
||||
Offset = a->pc;
|
||||
memcpy(bytes, buf, RZ_MIN(len, 8)); // TODO handle thumb
|
||||
|
||||
/* prepare disassembler */
|
||||
memset(&disasm_obj, '\0', sizeof(struct disassemble_info));
|
||||
disasm_obj.disassembler_options = (a->bits == 64) ? "64" : "";
|
||||
disasm_obj.buffer = bytes;
|
||||
disasm_obj.read_memory_func = &tricore_buffer_read_memory;
|
||||
disasm_obj.symbol_at_address_func = &symbol_at_address;
|
||||
disasm_obj.memory_error_func = &memory_error_func;
|
||||
disasm_obj.print_address_func = &generic_print_address_func;
|
||||
disasm_obj.endian = BFD_ENDIAN_LITTLE;
|
||||
disasm_obj.fprintf_func = &generic_fprintf_func;
|
||||
disasm_obj.stream = stdout;
|
||||
|
||||
// cpu type
|
||||
disasm_obj.mach = cpu_to_mach(a->cpu);
|
||||
|
||||
op->size = print_insn_tricore((bfd_vma)Offset, &disasm_obj);
|
||||
if (op->size == -1) {
|
||||
rz_asm_op_set_asm(op, " (data)");
|
||||
}
|
||||
return op->size;
|
||||
}
|
||||
|
||||
RzAsmPlugin rz_asm_plugin_tricore = {
|
||||
.name = "tricore",
|
||||
.arch = "tricore",
|
||||
.license = "GPL3",
|
||||
.bits = 32,
|
||||
.endian = RZ_SYS_ENDIAN_LITTLE,
|
||||
.desc = "Siemens TriCore CPU",
|
||||
.disassemble = &disassemble,
|
||||
};
|
||||
|
||||
#ifndef RZ_PLUGIN_INCORE
|
||||
RZ_API RzLibStruct rizin_plugin = {
|
||||
.type = RZ_LIB_TYPE_ASM,
|
||||
.data = &rz_asm_plugin_tricore,
|
||||
.version = RZ_VERSION
|
||||
};
|
||||
#endif
|
||||
|
|
@ -2260,7 +2260,6 @@ extern RzAnalysisPlugin rz_analysis_plugin_spc700;
|
|||
extern RzAnalysisPlugin rz_analysis_plugin_sysz;
|
||||
extern RzAnalysisPlugin rz_analysis_plugin_tms320;
|
||||
extern RzAnalysisPlugin rz_analysis_plugin_tms320c64x;
|
||||
extern RzAnalysisPlugin rz_analysis_plugin_tricore;
|
||||
extern RzAnalysisPlugin rz_analysis_plugin_v810;
|
||||
extern RzAnalysisPlugin rz_analysis_plugin_v850;
|
||||
extern RzAnalysisPlugin rz_analysis_plugin_vax;
|
||||
|
|
|
|||
|
|
@ -266,7 +266,6 @@ extern RzAsmPlugin rz_asm_plugin_spc700;
|
|||
extern RzAsmPlugin rz_asm_plugin_sysz;
|
||||
extern RzAsmPlugin rz_asm_plugin_tms320;
|
||||
extern RzAsmPlugin rz_asm_plugin_tms320c64x;
|
||||
extern RzAsmPlugin rz_asm_plugin_tricore;
|
||||
extern RzAsmPlugin rz_asm_plugin_v810;
|
||||
extern RzAsmPlugin rz_asm_plugin_v850;
|
||||
extern RzAsmPlugin rz_asm_plugin_vax;
|
||||
|
|
|
|||
Loading…
Reference in a new issue