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Fix grammar across the code

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This commit is contained in:
Anton Kochkov 2019-06-18 13:13:08 +08:00
parent 1da215dcac
commit b22d9f3065
47 changed files with 89 additions and 89 deletions
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4
.appveyor.yml
View file

@ -33,10 +33,10 @@ environment:
# Init
init:
# Build dependant custom commands
# Build dependent custom commands
- cmd: "%init_command%"
# Required softwares for building
# Required software for building
install:
# Update environment variables
- ps: $env:R2_VERSION = ( python sys\\version.py )

2
.github/ISSUE_TEMPLATE/bug_report.md vendored
View file

@ -8,7 +8,7 @@ about: Create a report to help us improve
Make sure you are testing using the latest git version of radare2 before submitting any issue.
*If you would like to report a bug, please fill the template bellow*
*If you would like to report a bug, please fill the template below*
### Work environment

2
DEVELOPERS.md
View file

@ -177,7 +177,7 @@ R_API void public() {} ## public apis starting with constructor/destructor
* Why return int vs enum
The reason why many places in r2land functions return int instead of an enum type is because enums cant be OR'ed; otherwise, it breaks the usage within a switch statement and swig can't handle that stuff.
The reason why many places in r2land functions return int instead of an enum type is because enums can't be OR'ed; otherwise, it breaks the usage within a switch statement and swig can't handle that stuff.
```
r_core_wrap.cxx:28612:60: error: assigning to 'RRegisterType' from incompatible type 'long'

2
README.md
View file

@ -80,7 +80,7 @@ If you don't have root, or just want to install it in your home use:
$ sys/user.sh
Note that those scripts will install using configure+make using symlinks, so you
don't need to reinstall everytime you change something in the builddir.
don't need to reinstall every time you change something in the builddir.
* If you don't like symlinks use `sys/install.sh --install`
* To use capstone5 use the `--with-capstone5` flag.

2
binr/preload/alloc.c
View file

@ -121,7 +121,7 @@ int main() {
char *a = r_malloc (10);
if (!a) {
printf ("cant malloc\n");
printf ("can't malloc\n");
return 1;
}
strcpy (a, "hello");

2
binr/rules.mk
View file

@ -73,7 +73,7 @@ endif
endif
endif
# Dummy myclean rule that can be overriden by the t/ Makefile
# Dummy myclean rule that can be overridden by the t/ Makefile
# TODO: move to config.mk ? it must be a precondition
myclean:

2
doc/capstone.md
View file

@ -19,7 +19,7 @@ You can link capstone dynamically (by using --with-syscapstone), this will skip
download and build steps of capstone inside `shlr/capstone`.and just link against the version
of capstone found in the system. That's what distros usually want.
NOTE: that buliding against capstone-master is cursedd, because cs-master reports v5, but code
NOTE: that building against capstone-master is cursedd, because cs-master reports v5, but code
is from v4, so it fails to compile because of missing enums and archs.
v5

2
doc/debug-internals.md
View file

@ -50,7 +50,7 @@ Radare supports a multitude of different types of breakpoints.
(`??` is there a list? sw, hw, and trace? anything else??)
libr/bp/bp.c // main breakpoint management code
libr/bp/io.c // setting and reseting(??) breakpoints
libr/bp/io.c // setting and resetting(??) breakpoints
libr/bp/parser.h // header for breakpoint parser (??)
libr/bp/parser.c // code for breakpoint parser (??)
libr/bp/plugin.c // breakpoint plugin management

2
doc/dospart
View file

@ -237,7 +237,7 @@ e0 Reserved by
e1 DOS access or SpeedStor 12-bit FAT extended partitionKevin Cummings reports in alt.os.linux:
e3 DOS R/O or SpeedStor
e4 SpeedStor 16-bit FAT extended partition < 1024 cyl.
e5 Tandy MSDOS with
e5 Tandy MS-DOS with
e6 Storage Dimensions SpeedStor
e8 LUKS
eb BeOS BFSBeOS is an operating system that runs on Power PCs and on Intel PCs.

8
doc/esil.md
View file

@ -119,7 +119,7 @@ ESIL Flags
==========
ESIL VM have an internal state flags that can are read only and can be used to
export those values to the underlaying CPU flags. This is because the ESIL vm
export those values to the underlying CPU flags. This is because the ESIL vm
defines all the flag changes, while the CPUs only update the flags under
certain conditions or specific instructions.
@ -144,9 +144,9 @@ Variables
Bitarrays
=========
What to do with them? What about bit arithmetics if use variables instead of registers?
What to do with them? What about bit arithmetic if use variables instead of registers?
Arithmetics
Arithmetic
===========
1. ADD ("+")
2. MUL ("*")
@ -155,7 +155,7 @@ Arithmetics
5. MOD ("%")
Bit arithmetics
Bit arithmetic
===============
1. AND "&"
2. OR "|"

2
doc/intro.md
View file

@ -573,7 +573,7 @@ Show differences between original and patched on x86_32
## rafind2 - Search
```
-Z: Look for Zero terminated strings
-s str: Look for specifc string
-s str: Look for specific string
```
## ragg2 - Shellcode generator, C/opcode compiler

2
doc/io.md
View file

@ -15,7 +15,7 @@ The base address is used to reallocate all vaddr offsets.
Reading/writing ops should be done in a loop checking for the section boundaries.
The sections must be asociated to a file, but we should be able to display/use them all in case of having non forced fd. This is, when not having overlapped files in memory.
The sections must be associated to a file, but we should be able to display/use them all in case of having non forced fd. This is, when not having overlapped files in memory.
The write ops should only obey to the global io configuration and ignore the section permissions (maybe just throw a warning?)

2
doc/license.md
View file

@ -22,7 +22,7 @@ Some parts of r2 are under the GPL license, here's a list of them:
* GNU binutils disassemblers (libr/asm)
* GRUB filesystems (libr/fs)
If you are going to use r2 in your propietary product bear in mind to build it without those parts, which may infect your program. Please refer to the FSF or GNU sites to understand how licenses work.
If you are going to use r2 in your proprietary product bear in mind to build it without those parts, which may infect your program. Please refer to the FSF or GNU sites to understand how licenses work.
As long as r2pipe, or webui access is done via a textual interface which requires no reverse engineering or linking for integration other programs will not be affected by the license rules.

2
doc/macos.md
View file

@ -53,7 +53,7 @@ As said before, the signing process can also be done manually following the next
$ make -C binr/radare2 macossign
But this is not enough. As long as r2 code is splitted into several libraries, you should sign every single dependency (libr*).
But this is not enough. As long as r2 code is split into several libraries, you should sign every single dependency (libr*).
$ make -C binr/radare2 macos-sign-libs

2
doc/node.js/README.md
View file

@ -10,7 +10,7 @@ Description
This is the nodejs implementation of a websever
for radare2. This script can be executed from
inside r2 by using the following commnad:
inside r2 by using the following command:
> #!pipe node .

2
doc/oo.md
View file

@ -8,7 +8,7 @@ following some sane and basic OO concepts.
- Instances are used to keep states
- Enforces instance recycling
- Reduce creation/destruction of objects
- Easily interfaced with Vala thru the VAPIs
- Easily interfaced with Vala through the VAPIs
Global picture
--------------

6
doc/releases.md
View file

@ -6,15 +6,15 @@ each release and define the instructions for generating the distribution
tarball together with a scheduler.
* We try to release every 1/2 months
* Version numbering (actually we dont follow any rules for this)
* Codenames for releases MUST be funny (until we didnt get a name that can make
* Version numbering (actually we don't follow any rules for this)
* Codenames for releases MUST be funny (until we didn't get a name that can make
me laugh, we should not release anything!)
Before any release we have to:
- Remove warnings
We dont want to fall in the warning nightmare of r1. Releases should contain
We don't want to fall in the warning nightmare of r1. Releases should contain
no warnings with `gcc -Wall` or at least no dangerous ones.
- Sync Vala APIs

2
doc/siol.md
View file

@ -7,7 +7,7 @@ Top-Down-View of siol
+==================+
| Write-Mask |
+==================+
| Buffer | <--- maybe this could be deprectated, I see no usecase for the buffer
| Buffer | <--- maybe this could be deprecated, I see no usecase for the buffer
+==================+
| Cache (V) |
+==================+ +========================+

2
doc/vim2r2.js
View file

@ -169,7 +169,7 @@ if (typeof process !== 'undefined') {
});
});
} else {
/* asuming its being used as an api */
/* assuming its being used as an api */
}
}
}

2
doc/yara.md
View file

@ -16,7 +16,7 @@ malware family.
Requirements
------------
You can either install libyara with your prefered package manager, or you
You can either install libyara with your preferred package manager, or you
can execute `r2pm -i yara3-lib` and `r2pm -i yara3` in order to retrieve
latest source, compile, and install the library.

8
libr/anal/anal.c
View file

@ -602,7 +602,7 @@ R_API bool r_anal_noreturn_add(RAnal *anal, const char *name, ut64 addr) {
RAnalFunction *fcn = r_anal_get_fcn_in (anal, addr, -1);
RFlagItem *fi = anal->flb.get_at (anal->flb.f, addr, false);
if (!fcn && !fi) {
eprintf ("Cant find Function at given address\n");
eprintf ("Can't find Function at given address\n");
return false;
}
tmp_name = fcn ? fcn->name: fi->name;
@ -614,10 +614,10 @@ R_API bool r_anal_noreturn_add(RAnal *anal, const char *name, ut64 addr) {
if (name) {
sdb_bool_set (TDB, K_NORET_FUNC (name), true, 0);
} else {
eprintf ("Cant find prototype for: %s\n", tmp_name);
eprintf ("Can't find prototype for: %s\n", tmp_name);
}
} else {
eprintf ("Cant find prototype for: %s\n", tmp_name);
eprintf ("Can't find prototype for: %s\n", tmp_name);
}
//return false;
}
@ -656,7 +656,7 @@ R_API bool r_anal_noreturn_drop(RAnal *anal, const char *expr) {
free (tmp);
return true;
}
eprintf ("Cant find prototype for %s in types databse", fcnname);
eprintf ("Can't find prototype for %s in types database", fcnname);
#endif
return false;
}

4
libr/anal/arch/gb/meta_gb_cmt.c
View file

@ -17,10 +17,10 @@ void meta_gb_hardware_cmt(RAnal *a, const ut8 hw, ut64 addr) {
r_meta_set_string(a, R_META_TYPE_COMMENT, addr, "JOYPAD"); //Moar context for this (which Key is affected)
break;
case 1:
r_meta_set_string(a, R_META_TYPE_COMMENT, addr, "Serial tranfer data");
r_meta_set_string(a, R_META_TYPE_COMMENT, addr, "Serial transfer data");
break;
case 2:
r_meta_set_string(a, R_META_TYPE_COMMENT, addr, "Serial tranfer data - Ctl");
r_meta_set_string(a, R_META_TYPE_COMMENT, addr, "Serial transfer data - Ctl");
break;
case 4:
r_meta_set_string(a, R_META_TYPE_COMMENT, addr, "DIV");

2
libr/anal/diff.c
View file

@ -292,5 +292,5 @@ R_API int r_anal_diff_eval(RAnal *anal) {
if (anal && anal->cur && anal->cur->diff_eval) {
return (anal->cur->diff_eval (anal));
}
return true; // XXX: shouldnt this be false?
return true; // XXX: shouldn't this be false?
}

18
libr/anal/esil.c
View file

@ -209,8 +209,8 @@ static int internal_esil_mem_read(RAnalEsil *esil, ut64 addr, ut8 *buf, int len)
}
//TODO: Check if error return from read_at.(on previous version of r2 this call always return len)
(void)esil->anal->iob.read_at (esil->anal->iob.io, addr, buf, len);
// check if request addres is mapped , if dont fire trap and esil ioer callback
// now with siol, read_at return true/false cant be used to check error vs len
// check if request address is mapped , if don't fire trap and esil ioer callback
// now with siol, read_at return true/false can't be used to check error vs len
if (!esil->anal->iob.is_valid_offset (esil->anal->iob.io, addr, false)) {
if (esil->iotrap) {
esil->trap = R_ANAL_TRAP_READ_ERR;
@ -234,8 +234,8 @@ static int internal_esil_mem_read_no_null(RAnalEsil *esil, ut64 addr, ut8 *buf,
}
//TODO: Check if error return from read_at.(on previous version of r2 this call always return len)
(void)esil->anal->iob.read_at (esil->anal->iob.io, addr, buf, len);
// check if request addres is mapped , if dont fire trap and esil ioer callback
// now with siol, read_at return true/false cant be used to check error vs len
// check if request address is mapped , if don't fire trap and esil ioer callback
// now with siol, read_at return true/false can't be used to check error vs len
if (!esil->anal->iob.is_valid_offset (esil->anal->iob.io, addr, false)) {
if (esil->iotrap) {
esil->trap = R_ANAL_TRAP_READ_ERR;
@ -297,8 +297,8 @@ static int internal_esil_mem_write(RAnalEsil *esil, ut64 addr, const ut8 *buf, i
if (esil->anal->iob.write_at (esil->anal->iob.io, addr, buf, len)) {
ret = len;
}
// check if request addres is mapped , if dont fire trap and esil ioer callback
// now with siol, write_at return true/false cant be used to check error vs len
// check if request address is mapped , if don't fire trap and esil ioer callback
// now with siol, write_at return true/false can't be used to check error vs len
if (!esil->anal->iob.is_valid_offset (esil->anal->iob.io, addr, false)) {
if (esil->iotrap) {
esil->trap = R_ANAL_TRAP_WRITE_ERR;
@ -323,8 +323,8 @@ static int internal_esil_mem_write_no_null(RAnalEsil *esil, ut64 addr, const ut8
if (esil->anal->iob.write_at (esil->anal->iob.io, addr, buf, len)) {
ret = len;
}
// check if request addres is mapped , if dont fire trap and esil ioer callback
// now with siol, write_at return true/false cant be used to check error vs len
// check if request address is mapped , if don't fire trap and esil ioer callback
// now with siol, write_at return true/false can't be used to check error vs len
if (!esil->anal->iob.is_valid_offset (esil->anal->iob.io, addr, false)) {
if (esil->iotrap) {
esil->trap = R_ANAL_TRAP_WRITE_ERR;
@ -3190,7 +3190,7 @@ R_API int r_anal_esil_setup(RAnalEsil *esil, RAnal *anal, int romem, int stats,
if (nonull) {
// this is very questionable, most platforms allow accessing NULL
// never writes zero to PC, BP, SP, why? because writing
// zeros to these registers is equivalent to acessing NULL
// zeros to these registers is equivalent to accessing NULL
// pointer somehow
esil->cb.reg_write = internal_esil_reg_write_no_null;
esil->cb.mem_read = internal_esil_mem_read_no_null;

2
libr/anal/esil_interrupt.c
View file

@ -89,7 +89,7 @@ R_API int r_anal_esil_fire_interrupt(RAnalEsil *esil, ut32 intr_num) {
}
RAnalEsilInterrupt *intr = _get_interrupt (esil, intr_num);
#if 0
// we dont want this warning
// we don't want this warning
if (!intr) {
eprintf ("Warning no interrupt handler registered for 0x%x\n", intr_num);
}

10
libr/anal/fcn.c
View file

@ -730,7 +730,7 @@ static bool try_get_delta_jmptbl_info(RAnal *anal, RAnalFunction *fcn, ut64 jmp_
if (!buf) {
return false;
}
// search for a cmp register with a resonable size
// search for a cmp register with a reasonable size
anal->iob.read_at (anal->iob.io, lea_addr, (ut8 *)buf, search_sz);
for (i = 0; i + 8 < search_sz; i++) {
@ -835,7 +835,7 @@ static bool try_get_jmptbl_info(RAnal *anal, RAnalFunction *fcn, ut64 addr, RAna
if (!bb_buf) {
return false;
}
// search for a cmp register with a resonable size
// search for a cmp register with a reasonable size
anal->iob.read_at (anal->iob.io, prev_bb->addr, (ut8 *) bb_buf, prev_bb->size);
isValid = false;
@ -1546,7 +1546,7 @@ repeat:
if (is_arm && last_is_mov_lr_pc) {
break;
}
/* fall thru */
/* fall through */
case R_ANAL_OP_TYPE_MJMP:
case R_ANAL_OP_TYPE_IJMP:
case R_ANAL_OP_TYPE_IRJMP:
@ -2046,7 +2046,7 @@ R_API bool r_anal_fcn_add_bb(RAnal *anal, RAnalFunction *fcn, ut64 addr, ut64 si
if (size > anal->opt.bb_max_size) {
r_warn_if_reached ();
if (anal->verbose) {
eprintf ("warning: cant allocate such big bb of %"PFMT64d" bytes at 0x%08"PFMT64x"\n", (st64)size, addr);
eprintf ("warning: can't allocate such big bb of %"PFMT64d" bytes at 0x%08"PFMT64x"\n", (st64)size, addr);
}
return false;
}
@ -2063,7 +2063,7 @@ R_API bool r_anal_fcn_add_bb(RAnal *anal, RAnalFunction *fcn, ut64 addr, ut64 si
}
}
if (mid) {
// eprintf ("Basic Block overlaps another one that should be shrinked\n");
// eprintf ("Basic Block overlaps another one that should be shrunk\n");
if (bbi) {
/* shrink overlapped basic block */
bbi->size = addr - (bbi->addr);

2
libr/anal/hint.c
View file

@ -68,7 +68,7 @@ R_API void r_anal_hint_set_newbits(RAnal *a, ut64 addr, int bits) {
setHint (a, "Bits:", addr, NULL, bits);
}
// TOOD: add helpers for newendian and newbank
// TODO: add helpers for newendian and newbank
R_API void r_anal_hint_set_fail(RAnal *a, ut64 addr, ut64 ptr) {
setHint (a, "fail:", addr, NULL, ptr);

4
libr/anal/meta.c
View file

@ -17,7 +17,7 @@ DatabaseName:
'anal.meta'
Keys:
'meta.<type>.count=<int>' number of added metas where 'type' is a single char
'meta.<type>.<last>=<array>' splitted array, each block contains K elements
'meta.<type>.<last>=<array>' split array, each block contains K elements
'meta.<type>.<addr>=<string>' string representing extra information of the meta type at given address
'range.<baddr>=<array>' store valid addresses in a base range array
#endif
@ -452,7 +452,7 @@ static RAnalMetaItem *r_meta_find_(RAnal *a, ut64 at, int type, int where, int e
static RAnalMetaItem mi = {0};
// XXX: return allocated item? wtf
if (where != R_META_WHERE_HERE) {
eprintf ("THIS WAS NOT SUPOSED TO HAPPEN\n");
eprintf ("THIS WAS NOT SUPPOSED TO HAPPEN\n");
return NULL;
}

2
libr/anal/op.c
View file

@ -409,7 +409,7 @@ R_API const char *r_anal_optype_to_string(int t) {
/* nothing */
break;
}
t &= R_ANAL_OP_TYPE_MASK; // ignore the modifier bits... we dont want this!
t &= R_ANAL_OP_TYPE_MASK; // ignore the modifier bits... we don't want this!
#if 0
int i;
// this is slower than a switch table :(

2
libr/anal/p/anal_6502.c
View file

@ -313,7 +313,7 @@ static int _6502_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int le
}
memset (op, '\0', sizeof (RAnalOp));
op->size = snes_op_get_size (1, 1, &snes_op[data[0]]); //snes-arch is similiar to nes/6502
op->size = snes_op_get_size (1, 1, &snes_op[data[0]]); //snes-arch is similar to nes/6502
op->addr = addr;
op->type = R_ANAL_OP_TYPE_UNK;
op->id = data[0];

2
libr/anal/p/anal_8051.c
View file

@ -120,7 +120,7 @@ static void set_cpu_model(RAnal *anal, bool force) {
cpu = cpu_models[0].name;
}
// if cpu model changed, reinitalize emulation
// if cpu model changed, reinitialize emulation
if (force || !cpu_curr_model || r_str_casecmp (cpu, cpu_curr_model->name)) {
// find model by name
int i = 0;

14
libr/anal/p/anal_arc.c
View file

@ -239,7 +239,7 @@ static int arcompact_genops(RAnalOp *op, ut64 addr, ut32 words[2]) {
if ((fields.format == 1 || fields.format == 2) && fields.b == ARC_REG_PCL) {
/* dst = PCL + src */
op->ptr = (addr & ~3) + fields.imm;
op->refptr = 1; /* HACK! we dont actually know what size it is */
op->refptr = 1; /* HACK! we don't actually know what size it is */
}
case 0x01: /* add with carry */
case 0x14: /* add with left shift by 1 */
@ -454,7 +454,7 @@ static int arcompact_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, in
/* no unaligned code */
if (addr % 2 != 0) {
/* this fixes some of the reverse dissassembly issues */
/* this fixes some of the reverse disassembly issues */
op->type = R_ANAL_OP_TYPE_ILL;
return 0;
}
@ -503,8 +503,8 @@ static int arcompact_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, in
} else {
/* Branch Unconditional Far 0x00 [0x1] */
fields.limm |= (fields.c & 0x0f) << 21;
/* the & 0xf clearly shows we dont overflow */
/* TODO: dont generate code to show this */
/* the & 0xf clearly shows we don't overflow */
/* TODO: don't generate code to show this */
fields.limm = SEX_S25 (fields.limm);
op->type = R_ANAL_OP_TYPE_JMP;
}
@ -550,8 +550,8 @@ static int arcompact_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, in
} else {
/* Branch and Link Unconditional Far, 0x01, [0x0, 0x1] */
fields.imm |= (fields.c & 0x0f) << 21;
/* the & 0xf clearly shows we dont overflow */
/* TODO: dont generate code to show this */
/* the & 0xf clearly shows we don't overflow */
/* TODO: don't generate code to show this */
fields.imm = SEX_S25 (fields.imm);
op->type = R_ANAL_OP_TYPE_CALL;
}
@ -839,7 +839,7 @@ static int arcompact_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, in
case 0x1e:
op->type = R_ANAL_OP_TYPE_TRAP;
/* TODO: the description sounds more like a */
/* R_ANAL_OP_TYPE_SWI, but I dont know what */
/* R_ANAL_OP_TYPE_SWI, but I don't know what */
/* difference that would make to radare */
break;
case 0x1f:

2
libr/anal/p/anal_arm_cs.c
View file

@ -2030,7 +2030,7 @@ r4,r5,r6,3,sp,[*],12,sp,+=
(ut64)MEMDISP(1), pc, mask, REG(0));
} else {
int disp = MEMDISP(1);
// not refptr, because we cant grab the reg value statically op->refptr = 4;
// not refptr, because we can't grab the reg value statically op->refptr = 4;
if (disp < 0) {
r_strbuf_appendf (&op->esil, "0x%"PFMT64x",%s,-,0xffffffff,&,[4],0x%x,&,%s,=",
(ut64)-disp, MEMBASE(1), mask, REG(0));

2
libr/anal/p/anal_bf.c
View file

@ -29,7 +29,7 @@ static int bf_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len, R
return 1;
}
/* Ayeeee! What's inside op? Do we have an initialized RAnalOp? Are we going to have a leak here? :-( */
memset (op, 0, sizeof (RAnalOp)); /* We need to refactorize this. Something like r_anal_op_init would be more appropiate */
memset (op, 0, sizeof (RAnalOp)); /* We need to refactorize this. Something like r_anal_op_init would be more appropriate */
r_strbuf_init (&op->esil);
op->size = 1;
op->id = getid (buf[0]);

10
libr/anal/p/anal_dalvik.c
View file

@ -67,7 +67,7 @@ static int dalvik_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int l
switch (data[0]) {
case 0xca: // rem-float:
op->family = R_ANAL_OP_FAMILY_FPU;
/* pass thru */
/* pass through */
case 0x1b: // const-string/jumbo
case 0x14: // const
case 0x15: // const
@ -171,7 +171,7 @@ static int dalvik_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int l
case 0x88: // float-to-long
case 0x86: // long-to-double
op->family = R_ANAL_OP_FAMILY_FPU;
/* pass thru */
/* pass through */
case 0x81: // int-to-long
case 0x82: // int-to-float
case 0x85: // long-to-float
@ -357,7 +357,7 @@ static int dalvik_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int l
case 0xcf: // rem-double
case 0xaf: // rem-double
op->family = R_ANAL_OP_FAMILY_FPU;
/* pass thru */
/* pass through */
case 0xb4: // rem-int/2addr
case 0xdc: // rem-int/lit8
case 0xd4: // rem-int
@ -383,7 +383,7 @@ static int dalvik_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int l
break;
case 0xc9: // div-float
op->family = R_ANAL_OP_FAMILY_FPU;
/* pass thru */
/* pass through */
case 0x93: // div-int
case 0xd3: // div-int/lit16
case 0xdb: // div-int/lit8
@ -650,7 +650,7 @@ static int dalvik_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int l
case 0xa7: // sub-float
case 0xcc: // sub-double
op->family = R_ANAL_OP_FAMILY_FPU;
/* fall thru */
/* fall through */
case 0xc7:
case 0xbc:
case 0x91:

2
libr/anal/p/anal_gb.c
View file

@ -1216,7 +1216,7 @@ static int gb_anop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data, int len
break;
case 0x76:
op->type = R_ANAL_OP_TYPE_CJMP;
op->eob = true; //halt migth wait for interrupts
op->eob = true; //halt might wait for interrupts
op->fail = addr + ilen;
if (len > 1) {
op->jump = addr + gbOpLength (gb_op[data[1]].type) + ilen;

6
libr/anal/p/anal_java.c
View file

@ -219,7 +219,7 @@ static int handle_bb_cf_recursive_descent (RAnal *anal, RAnalState *state) {
IFDBG eprintf ("Handling a control flow change @ 0x%04"PFMT64x".\n", addr);
ut64 control_type = r_anal_ex_map_anal_ex_to_anal_op_type (bb->type2);
// XXX - transition to type2 control flow condtions
// XXX - transition to type2 control flow conditions
switch (control_type) {
case R_ANAL_OP_TYPE_CALL:
IFDBG eprintf (" - Handling a call @ 0x%04"PFMT64x".\n", addr);
@ -412,7 +412,7 @@ static int handle_bb_cf_linear_sweep (RAnal *anal, RAnalState *state) {
IFDBG eprintf ("Handling a control flow change @ 0x%04"PFMT64x".\n", addr);
ut32 control_type = r_anal_ex_map_anal_ex_to_anal_op_type (bb->type2);
// XXX - transition to type2 control flow condtions
// XXX - transition to type2 control flow conditions
switch (control_type) {
case R_ANAL_OP_TYPE_CALL:
IFDBG eprintf (" - Handling a call @ 0x%04"PFMT64x"\n", addr);
@ -712,7 +712,7 @@ static int java_switch_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *data,
for (cur_case = 0; cur_case <= max_val - min_val; pos += 4, cur_case++) {
//ut32 value = (ut32)(UINT (data, pos));
if (pos + 4 >= len) {
// switch is too big cant read further
// switch is too big can't read further
break;
}
int offset = (int)(ut32)(R_BIN_JAVA_UINT (data, pos));

2
libr/anal/p/anal_mips_cs.c
View file

@ -853,7 +853,7 @@ static int analop(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len,
case MIPS_INS_BLEZALC:
case MIPS_INS_BGEZALC:
case MIPS_INS_BGTZALC:
// compact vesions (no delay)
// compact versions (no delay)
op->delay = 0;
op->fail = addr+4;
break;

2
libr/anal/p/anal_nios2.c
View file

@ -11,7 +11,7 @@ static int nios2_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *b, int len,
return 1;
}
/* Ayeeee! What's inside op? Do we have an initialized RAnalOp? Are we going to have a leak here? :-( */
memset (op, 0, sizeof (RAnalOp)); /* We need to refactorize this. Something like r_anal_op_init would be more appropiate */
memset (op, 0, sizeof (RAnalOp)); /* We need to refactorize this. Something like r_anal_op_init would be more appropriate */
r_strbuf_init (&op->esil);
op->size = 4;

4
libr/anal/p/anal_pic.c
View file

@ -727,7 +727,7 @@ static void pic18_cond_branch (RAnalOp *op, ut64 addr, const ut8 *buf, char *fla
}
static int anal_pic_pic18_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len) {
//TODO code should be refactored and brocken into smaller chuncks!!
//TODO code should be refactored and broken into smaller chunks!!
//TODO complete the esil emitter
if (len < 2) {
op->size = len;
@ -1047,7 +1047,7 @@ static int anal_pic_pic18_set_reg_profile(RAnal *esil) {
"#bsr max is 0b111\n"
"gpr bsr .8 4 0\n"
"#tos doesn't exist\n"
"#general rule of thumb any register of size >8 bits has no existance\n"
"#general rule of thumb any register of size >8 bits has no existence\n"
"gpr tos .32 5 0\n"
"gpr tosl .8 5 0\n"
"gpr tosh .8 6 0\n"

4
libr/anal/p/anal_sh.c
View file

@ -559,10 +559,10 @@ static int first_nibble_is_3(RAnal* anal, RAnalOp* op, ut16 code) {
"0xFFFFFF7F,sr,&=,"
"1,r%d,DUP,0x80000000,&,?{,0x80,sr,|=,},<<,sr,0x1,&,|,r%d,=," //shift Q<-Rn<-T
"DUP,!,!,?{,"
"r%d,NUM,"//Rn_old (before substract)
"r%d,NUM,"//Rn_old (before subtract)
"r%d,r%d,+=,"
"r%d,<,}{," //tmp0
"r%d,NUM,"//Rn_old (before substract)
"r%d,NUM,"//Rn_old (before subtract)
"r%d,r%d,-=,"
"r%d,>,}," //tmp0
"sr,0x80,&,!,!,^," //Q^tmp0

2
libr/anal/p/anal_sparc_gnu.c
View file

@ -84,7 +84,7 @@ enum {
FCC_UL = 0x3,
FCC_ULE = 0xe,
};
/* Define some additional conditions that are nor mapable to
/* Define some additional conditions that are nor mappable to
the existing R_ANAL_COND* ones and need to be handled in a
special way. */
enum {

2
libr/anal/p/anal_v850.c
View file

@ -209,7 +209,7 @@ static int v850_op(RAnal *anal, RAnalOp *op, ut64 addr, const ut8 *buf, int len,
break;
case V850_MOVEA:
op->type = R_ANAL_OP_TYPE_MOV;
// FIXME: to decide about reading 16/32 bit and use only macroses to access
// FIXME: to decide about reading 16/32 bit and use only macros to access
r_strbuf_appendf (&op->esil, "%s,0xffff,&,%u,+,%s,=", F6_RN1(word1), word2, F6_RN2(word1));
break;
case V850_SLDB:

4
libr/anal/p/anal_x86_cs.c
View file

@ -886,7 +886,7 @@ static void anop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len,
esilprintf (op, "eax,rax,=,31,rax,>>,?{,0xffffffff00000000,rax,|=,}");
break;
case X86_INS_AAA:
esilprintf (op, "0,cf,:=,0,af,:=,9,al,>,?{,10,al,-=,1,ah,+=,1,cf,:=,1,af,:=,}"); //dont
esilprintf (op, "0,cf,:=,0,af,:=,9,al,>,?{,10,al,-=,1,ah,+=,1,cf,:=,1,af,:=,}"); //don't
break;
case X86_INS_AAD:
arg0 = "0,zf,:=,0,sf,:=,0,pf,:=,10,ah,*,al,+,ax,=";
@ -1328,7 +1328,7 @@ static void anop_esil(RAnal *a, RAnalOp *op, ut64 addr, const ut8 *buf, int len,
/*
* Similar to BSF, except we naturally don't
* need to substract anything to create
* need to subtract anything to create
* a mask and return the result.
*/
esilprintf (op, "%s,!,?{,1,zf,=,BREAK,},0,zf,=,"

4
libr/anal/reflines.c
View file

@ -258,9 +258,9 @@ R_API RList* r_anal_reflines_fcn_get(RAnal *anal, RAnalFunction *fcn, int nlines
continue;
}
}
// Handles conditonal + unconditional jump
// Handles conditional + unconditional jump
if ((control_type & R_ANAL_BB_TYPE_CJMP) == R_ANAL_BB_TYPE_CJMP) {
// dont need to continue here is opc+len exceed function scope
// don't need to continue here is opc+len exceed function scope
if (linesout && bb->fail > 0LL && bb->fail != bb->addr + len) {
item = R_NEW0 (RAnalRefline);
if (!item) {

2
libr/anal/value.c
View file

@ -2,7 +2,7 @@
#include <r_anal.h>
R_API RAnalValue *r_anal_value_new() { //makro for this ?
R_API RAnalValue *r_anal_value_new() { //macro for this ?
return R_NEW0 (RAnalValue);
}

8
libr/anal/var.c
View file

@ -173,7 +173,7 @@ R_API int r_anal_var_retype(RAnal *a, ut64 addr, int scope, int delta, char kind
char *field_key = r_str_newf ("%s.%s", type_key, field);
char *field_type = sdb_array_get (TDB, field_key, 0, NULL);
ut64 field_offset = sdb_array_get_num (TDB, field_key, 1, NULL);
if (field_offset != 0) { // delete variables which are overlayed by structure
if (field_offset != 0) { // delete variables which are overlaid by structure
r_anal_var_delete (a, addr, kind, scope, delta + field_offset);
}
free (field_type);
@ -201,7 +201,7 @@ R_API int r_anal_var_delete_all(RAnal *a, ut64 addr, const char kind) {
// r_anal_var_delete (a, addr, kind, v->scope, v->delta);
r_anal_var_delete (a, addr, kind, 1, v->delta);
}
// XXX: i dont think we want to alocate and free by hand. r_anal_var_delete should be the list->free already
// XXX: i don't think we want to allocate and free by hand. r_anal_var_delete should be the list->free already
r_list_free (list);
}
return 0;
@ -291,7 +291,7 @@ R_API RAnalVar *r_anal_var_get_byname(RAnal *a, ut64 addr, const char *name) {
char *name_key = sdb_fmt ("var.0x%"PFMT64x ".%d.%s", addr, 1, name);
char *name_value = sdb_get (DB, name_key, 0);
if (!name_value) {
// eprintf ("Cant find key for %s\n", name_key);
// eprintf ("Can't find key for %s\n", name_key);
return NULL;
}
const char *comma = strchr (name_value, ',');
@ -908,7 +908,7 @@ R_API void r_anal_var_list_show(RAnal *anal, RAnalFunction *fcn, int kind, int m
}
switch (mode) {
case '*':
// we cant express all type info here :(
// we can't express all type info here :(
if (kind == R_ANAL_VAR_KIND_REG) { // registers
RRegItem *i = r_reg_index_get (anal->reg, var->delta);
if (!i) {