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Remove sdb_fmt() calls in RzAsm (#4130)

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Huzaifa 2024-01-22 17:50:27 +05:30 committed by GitHub
parent 02d4e67090
commit caca0799c6
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GPG key ID: B5690EEEBB952194
9 changed files with 86 additions and 92 deletions
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28
librz/asm/arch/pic/pic_baseline.c
View file

@ -190,11 +190,11 @@ const PicBaselineOpInfo *pic_baseline_get_op_info(PicBaselineOpcode opcode) {
return &pic_baseline_op_info[opcode];
}
int pic_baseline_disassemble(RzAsmOp *op, char *opbuf, const ut8 *b, int l) {
int pic_baseline_disassemble(RzAsmOp *op, const ut8 *b, int l) {
#define EMIT_INVALID \
{ \
op->size = 1; \
strcpy(opbuf, "invalid"); \
rz_asm_op_set_asm(op, "invalid"); \
return 1; \
}
if (!b || l < 2) {
@ -215,40 +215,40 @@ int pic_baseline_disassemble(RzAsmOp *op, char *opbuf, const ut8 *b, int l) {
#undef EMIT_INVALID
op->size = 2;
const char *buf_asm = "invalid";
switch (op_info->args) {
case PIC_BASELINE_OP_ARGS_NONE:
buf_asm = op_info->mnemonic;
rz_asm_op_set_asm(op, op_info->mnemonic);
break;
case PIC_BASELINE_OP_ARGS_2F:
buf_asm = sdb_fmt("%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_2F_MASK_F);
rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_2F_MASK_F);
break;
case PIC_BASELINE_OP_ARGS_3F:
buf_asm = sdb_fmt("%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_3F_MASK_F);
rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_3F_MASK_F);
break;
case PIC_BASELINE_OP_ARGS_3K:
buf_asm = sdb_fmt("%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_3K_MASK_K);
rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_3K_MASK_K);
break;
case PIC_BASELINE_OP_ARGS_1D_5F:
buf_asm = sdb_fmt("%s 0x%x, %c", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_1D_5F_MASK_F,
rz_asm_op_setf_asm(op, "%s 0x%x, %c", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_1D_5F_MASK_F,
(instr & PIC_BASELINE_OP_ARGS_1D_5F_MASK_D) >> 5 ? 'f' : 'w');
break;
case PIC_BASELINE_OP_ARGS_5F:
buf_asm = sdb_fmt("%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_5F_MASK_F);
rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_5F_MASK_F);
break;
case PIC_BASELINE_OP_ARGS_3B_5F:
buf_asm = sdb_fmt("%s 0x%x, 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_3B_5F_MASK_F,
rz_asm_op_setf_asm(op, "%s 0x%x, 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_3B_5F_MASK_F,
(instr & PIC_BASELINE_OP_ARGS_3B_5F_MASK_B) >> 5);
break;
case PIC_BASELINE_OP_ARGS_8K:
buf_asm = sdb_fmt("%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_8K_MASK_K);
rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_8K_MASK_K);
break;
case PIC_BASELINE_OP_ARGS_9K:
buf_asm = sdb_fmt("%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_9K_MASK_K);
rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_BASELINE_OP_ARGS_9K_MASK_K);
break;
default:
rz_asm_op_set_asm(op, "invalid");
break;
}
strcpy(opbuf, buf_asm);
return op->size;
}

2
librz/asm/arch/pic/pic_baseline.h
View file

@ -77,6 +77,6 @@ typedef enum {
PicBaselineOpcode pic_baseline_get_opcode(ut16 instr);
const PicBaselineOpInfo *pic_baseline_get_op_info(PicBaselineOpcode opcode);
int pic_baseline_disassemble(RzAsmOp *op, char *opbuf, const ut8 *b, int l);
int pic_baseline_disassemble(RzAsmOp *op, const ut8 *b, int l);
#endif // PIC_BASELINE_H

36
librz/asm/arch/pic/pic_midrange.c
View file

@ -156,14 +156,14 @@ const PicMidrangeOpInfo *pic_midrange_get_op_info(PicMidrangeOpcode opcode) {
return &pic_midrange_op_info[opcode];
}
int pic_midrange_disassemble(RzAsmOp *op, char *opbuf, const ut8 *b, int l) {
int pic_midrange_disassemble(RzAsmOp *op, const ut8 *b, int l) {
char fsr_op[6];
st16 branch;
#define EMIT_INVALID \
{ \
op->size = 2; \
strcpy(opbuf, "invalid"); \
rz_asm_op_set_asm(op, "invalid"); \
return 1; \
}
if (!b || l < 2) {
@ -185,53 +185,52 @@ int pic_midrange_disassemble(RzAsmOp *op, char *opbuf, const ut8 *b, int l) {
op->size = 2;
const char *buf_asm = NULL;
switch (op_info->args) {
case PIC_MIDRANGE_OP_ARGS_NONE:
buf_asm = op_info->mnemonic;
rz_asm_op_set_asm(op, op_info->mnemonic);
break;
case PIC_MIDRANGE_OP_ARGS_2F:
buf_asm = sdb_fmt("%s 0x%x", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_2F_MASK_F);
rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_2F_MASK_F);
break;
case PIC_MIDRANGE_OP_ARGS_7F:
buf_asm = sdb_fmt("%s 0x%x", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_7F_MASK_F);
rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_7F_MASK_F);
break;
case PIC_MIDRANGE_OP_ARGS_1D_7F:
buf_asm = sdb_fmt("%s 0x%x, %c", op_info->mnemonic,
rz_asm_op_setf_asm(op, "%s 0x%x, %c", op_info->mnemonic,
instr & PIC_MIDRANGE_OP_ARGS_1D_7F_MASK_F,
(instr & PIC_MIDRANGE_OP_ARGS_1D_7F_MASK_D) >> 7 ? 'f' : 'w');
break;
case PIC_MIDRANGE_OP_ARGS_1N_6K:
if (opcode == PIC_MIDRANGE_OPCODE_ADDFSR) {
buf_asm = sdb_fmt("%s FSR%d, 0x%x", op_info->mnemonic,
rz_asm_op_setf_asm(op, "%s FSR%d, 0x%x", op_info->mnemonic,
(instr & PIC_MIDRANGE_OP_ARGS_1N_6K_MASK_N) >>
6,
instr & PIC_MIDRANGE_OP_ARGS_1N_6K_MASK_K);
} else {
buf_asm = sdb_fmt("%s 0x%x[FSR%d]", op_info->mnemonic,
rz_asm_op_setf_asm(op, "%s 0x%x[FSR%d]", op_info->mnemonic,
instr & PIC_MIDRANGE_OP_ARGS_1N_6K_MASK_K,
(instr & PIC_MIDRANGE_OP_ARGS_1N_6K_MASK_N) >> 6);
}
break;
case PIC_MIDRANGE_OP_ARGS_3B_7F:
buf_asm = sdb_fmt("%s 0x%x, %d", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_3B_7F_MASK_F,
rz_asm_op_setf_asm(op, "%s 0x%x, %d", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_3B_7F_MASK_F,
(instr & PIC_MIDRANGE_OP_ARGS_3B_7F_MASK_B) >> 7);
break;
case PIC_MIDRANGE_OP_ARGS_4K:
buf_asm = sdb_fmt("%s 0x%x", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_4K_MASK_K);
rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_4K_MASK_K);
break;
case PIC_MIDRANGE_OP_ARGS_8K:
buf_asm = sdb_fmt("%s 0x%x", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_8K_MASK_K);
rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_8K_MASK_K);
break;
case PIC_MIDRANGE_OP_ARGS_9K:
branch = (instr & PIC_MIDRANGE_OP_ARGS_9K_MASK_K);
branch |= ((branch & 0x100) ? 0xfe00 : 0);
buf_asm = sdb_fmt("%s %s0x%x",
rz_asm_op_setf_asm(op, "%s %s0x%x",
op_info->mnemonic, branch < 0 ? "-" : "",
branch < 0 ? -branch : branch);
break;
case PIC_MIDRANGE_OP_ARGS_11K:
buf_asm = sdb_fmt("%s 0x%x", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_11K_MASK_K);
rz_asm_op_setf_asm(op, "%s 0x%x", op_info->mnemonic, instr & PIC_MIDRANGE_OP_ARGS_11K_MASK_K);
break;
case PIC_MIDRANGE_OP_ARGS_1N_2M:
snprintf(
@ -239,11 +238,12 @@ int pic_midrange_disassemble(RzAsmOp *op, char *opbuf, const ut8 *b, int l) {
PicMidrangeFsrOps[instr &
PIC_MIDRANGE_OP_ARGS_1N_2M_MASK_M],
(instr & PIC_MIDRANGE_OP_ARGS_1N_2M_MASK_N) >> 2);
buf_asm = sdb_fmt("%s %s", op_info->mnemonic, fsr_op);
rz_asm_op_setf_asm(op, "%s %s", op_info->mnemonic, fsr_op);
break;
default:
rz_asm_op_set_asm(op, "invalid");
break;
}
if (buf_asm) {
strcpy(opbuf, buf_asm);
}
return op->size;
}

2
librz/asm/arch/pic/pic_midrange.h
View file

@ -99,6 +99,6 @@ typedef enum {
PicMidrangeOpcode pic_midrange_get_opcode(ut16 instr);
const PicMidrangeOpInfo *pic_midrange_get_op_info(PicMidrangeOpcode opcode);
int pic_midrange_disassemble(RzAsmOp *op, char *opbuf, const ut8 *b, int l);
int pic_midrange_disassemble(RzAsmOp *op, const ut8 *b, int l);
#endif // PIC_MIDRANGE_H

37
librz/asm/arch/pic/pic_pic18.c
View file

@ -111,46 +111,44 @@ static struct {
{ 0x0, 0xffff, "invalid", NO_ARG },
};
int pic_pic18_disassemble(RzAsmOp *op, char *opbuf, const ut8 *b, int blen) {
int pic_pic18_disassemble(RzAsmOp *op, const ut8 *b, int blen) {
int i;
if (blen < 2) { // well noone loves reading bitstream of size zero or 1 !!
strcpy(opbuf, "invalid");
rz_asm_op_set_asm(op, "invalid");
op->size = blen;
return -1;
}
ut16 instr = rz_read_le16(b); // instruction
// if still redundan code is reported think of this of instr=0x2
const char *buf_asm = "invalid";
strcpy(opbuf, buf_asm);
// if still redundant code is reported think of this of instr=0x
for (i = 0; ops[i].opmin != (ops[i].opmin & instr) || ops[i].opmax != (ops[i].opmax | instr); i++) {
;
}
if (ops[i].opmin == 0 && ops[i].opmax == 0xffff) {
strcpy(opbuf, ops[i].name);
rz_asm_op_set_asm(op, ops[i].name);
op->size = 2;
return -1;
}
op->size = 2;
switch (ops[i].optype) {
case NO_ARG:
buf_asm = ops[i].name;
rz_asm_op_set_asm(op, ops[i].name);
break;
case N_T:
case K_T:
buf_asm = sdb_fmt("%s 0x%x", ops[i].name, instr & 0xff);
rz_asm_op_setf_asm(op, "%s 0x%x", ops[i].name, instr & 0xff);
break;
case DAF_T:
buf_asm = sdb_fmt("%s 0x%x, %d, %d", ops[i].name, instr & 0xff, (instr >> 9) & 1, (instr >> 8) & 1);
rz_asm_op_setf_asm(op, "%s 0x%x, %d, %d", ops[i].name, instr & 0xff, (instr >> 9) & 1, (instr >> 8) & 1);
break;
case AF_T:
buf_asm = sdb_fmt("%s 0x%x, %d", ops[i].name, instr & 0xff, (instr >> 8) & 1);
rz_asm_op_setf_asm(op, "%s 0x%x, %d", ops[i].name, instr & 0xff, (instr >> 8) & 1);
break;
case BAF_T:
buf_asm = sdb_fmt("%s 0x%x, %d, %d", ops[i].name, instr & 0xff, (instr >> 9) & 0x7, (instr >> 8) & 0x1);
rz_asm_op_setf_asm(op, "%s 0x%x, %d, %d", ops[i].name, instr & 0xff, (instr >> 9) & 0x7, (instr >> 8) & 0x1);
break;
case NEX_T:
buf_asm = sdb_fmt("%s 0x%x", ops[i].name, instr & 0x7ff);
rz_asm_op_setf_asm(op, "%s 0x%x", ops[i].name, instr & 0x7ff);
break;
case CALL_T:
if (blen < 4) {
@ -164,7 +162,7 @@ int pic_pic18_disassemble(RzAsmOp *op, char *opbuf, const ut8 *b, int blen) {
if (dword_instr >> 28 != 0xf) {
return -1;
}
buf_asm = sdb_fmt("%s 0x%x, %d", ops[i].name,
rz_asm_op_setf_asm(op, "%s 0x%x, %d", ops[i].name,
(dword_instr & 0xff) | (dword_instr >> 8 & 0xfff00), (dword_instr >> 8) & 0x1);
}
break;
@ -178,7 +176,7 @@ int pic_pic18_disassemble(RzAsmOp *op, char *opbuf, const ut8 *b, int blen) {
if (dword_instr >> 28 != 0xf) {
return -1;
}
buf_asm = sdb_fmt("%s 0x%x", ops[i].name,
rz_asm_op_setf_asm(op, "%s 0x%x", ops[i].name,
((dword_instr & 0xff) | ((dword_instr & 0xfff0000) >> 8)) * 2);
}
break;
@ -192,15 +190,15 @@ int pic_pic18_disassemble(RzAsmOp *op, char *opbuf, const ut8 *b, int blen) {
if (dword_instr >> 28 != 0xf) {
return -1;
}
buf_asm = sdb_fmt("%s 0x%x, 0x%x", ops[i].name,
rz_asm_op_setf_asm(op, "%s 0x%x, 0x%x", ops[i].name,
dword_instr & 0xfff, (dword_instr >> 16) & 0xfff);
}
break;
case SHK_T:
buf_asm = sdb_fmt("%s 0x%x", ops[i].name, instr & 0xf);
rz_asm_op_setf_asm(op, "%s 0x%x", ops[i].name, instr & 0xf);
break;
case S_T:
buf_asm = sdb_fmt("%s %d", ops[i].name, instr & 0x1);
rz_asm_op_setf_asm(op, "%s %d", ops[i].name, instr & 0x1);
break;
case LFSR_T: {
if (blen < 4) {
@ -212,13 +210,12 @@ int pic_pic18_disassemble(RzAsmOp *op, char *opbuf, const ut8 *b, int blen) {
return -1;
}
ut8 reg_n = (dword_instr >> 4) & 0x3;
buf_asm = sdb_fmt("%s %s, %d", ops[i].name, fsr[reg_n],
rz_asm_op_setf_asm(op, "%s %s, %d", ops[i].name, fsr[reg_n],
(dword_instr & 0xf) << 8 | ((dword_instr >> 16) & 0xff));
break;
}
default:
buf_asm = "unknown args";
rz_asm_op_set_asm(op, "unknown args");
};
strcpy(opbuf, buf_asm);
return op->size;
}

2
librz/asm/arch/pic/pic_pic18.h
View file

@ -7,6 +7,6 @@
#include <rz_asm.h>
int pic_pic18_disassemble(RzAsmOp *op, char *opbuf, const ut8 *b, int l);
int pic_pic18_disassemble(RzAsmOp *op, const ut8 *b, int l);
#endif // PIC_PIC18_H

2
librz/asm/arch/riscv/riscv.c
View file

@ -309,7 +309,7 @@ static int riscv_disassemble(RzAsm *a, RzAsmOp *rop, insn_t word, int xlen, int
get_insn_args (rz_asm_op_get_asm (rop), op->args, word, a->pc);
return 0;
}
rz_asm_op_set_asm (rop, sdb_fmt ("invalid word(%"PFMT64x")", (ut64)word));
rz_asm_op_setf_asm (rop, "invalid word(%"PFMT64x")", (ut64)word);
return -1;
}
return 0;

59
librz/asm/arch/z80/z80.c
View file

@ -8,7 +8,7 @@
#include <string.h>
#include "z80_tab.h"
static ut8 z80_op_24_branch_index_res (ut8 hex) {
static ut8 z80_op_24_branch_index_res(ut8 hex) {
if (hex < 0x40) {
return hex;
}
@ -22,10 +22,10 @@ static ut8 z80_op_24_branch_index_res (ut8 hex) {
case 0x76: return 0x46;
case 0x7e: return 0x47;
}
return (hex > 0x7f)? hex - 0x38: 0xc8;
return (hex > 0x7f) ? hex - 0x38 : 0xc8;
}
static int z80OpLength (const ut8 *buf, int len) {
static int z80OpLength(const ut8 *buf, int len) {
const z80_opcode *op;
int type = 0, ret = 0;
if (len < 1) {
@ -49,7 +49,7 @@ static int z80OpLength (const ut8 *buf, int len) {
if (type & Z80_OP8) {
ret++;
}
if ((type & Z80_ARG8) && !(type & Z80_ARG16)) { //XXX
if ((type & Z80_ARG8) && !(type & Z80_ARG16)) { // XXX
ret++;
}
if (type & Z80_OP16) {
@ -68,8 +68,8 @@ static int z80OpLength (const ut8 *buf, int len) {
}
// #include'd in asm/p/asm_z80.c
FUNC_ATTR_USED static int z80Disass (RzAsmOp *op, const ut8 *buf, int len) {
int ret = z80OpLength (buf, len);
FUNC_ATTR_USED static int z80Disass(RzAsmOp *op, const ut8 *buf, int len) {
int ret = z80OpLength(buf, len);
const z80_opcode *z_op;
const char **cb_tab;
ut8 res;
@ -77,55 +77,56 @@ FUNC_ATTR_USED static int z80Disass (RzAsmOp *op, const ut8 *buf, int len) {
return ret;
}
z_op = z80_op;
const char *buf_asm = "invalid";
switch (z_op[buf[0]].type) {
case Z80_OP8:
buf_asm = sdb_fmt ("%s", z_op[buf[0]].name);
rz_asm_op_set_asm(op, z_op[buf[0]].name);
break;
case Z80_OP8^Z80_ARG8:
buf_asm = sdb_fmt (z_op[buf[0]].name, buf[1]);
case Z80_OP8 ^ Z80_ARG8:
rz_asm_op_setf_asm(op, z_op[buf[0]].name, buf[1]);
break;
case Z80_OP8^Z80_ARG16:
buf_asm = sdb_fmt (z_op[buf[0]].name, buf[1]+(buf[2]<<8));
case Z80_OP8 ^ Z80_ARG16:
rz_asm_op_setf_asm(op, z_op[buf[0]].name, buf[1] + (buf[2] << 8));
break;
case Z80_OP16:
cb_tab = (const char **) z_op[buf[0]].op_moar;
buf_asm = sdb_fmt ("%s", cb_tab[buf[1]]);
cb_tab = (const char **)z_op[buf[0]].op_moar;
rz_asm_op_set_asm(op, cb_tab[buf[1]]);
break;
case Z80_OP_UNK ^ Z80_ENC1:
z_op = (const z80_opcode *)z_op[buf[0]].op_moar;
res = z80_ed_branch_index_res (buf[1]);
res = z80_ed_branch_index_res(buf[1]);
if (z_op[res].type == Z80_OP16) {
buf_asm = sdb_fmt ("%s", z_op[res].name);
rz_asm_op_set_asm(op, z_op[res].name);
}
if (z_op[res].type == (Z80_OP16^Z80_ARG16)) {
buf_asm = sdb_fmt (z_op[res].name, buf[2]+(buf[3]<<8));
if (z_op[res].type == (Z80_OP16 ^ Z80_ARG16)) {
rz_asm_op_setf_asm(op, z_op[res].name, buf[2] + (buf[3] << 8));
}
break;
case Z80_OP_UNK ^ Z80_ENC0:
z_op = (const z80_opcode *)z_op[buf[0]].op_moar;
res = z80_fddd_branch_index_res (buf[1]);
res = z80_fddd_branch_index_res(buf[1]);
if (z_op[res].type == Z80_OP16) {
buf_asm = sdb_fmt ("%s", z_op[res].name);
rz_asm_op_set_asm(op, z_op[res].name);
}
if (z_op[res].type == (Z80_OP16^Z80_ARG16)) {
buf_asm = sdb_fmt (z_op[res].name, buf[2]+(buf[3]<<8));
if (z_op[res].type == (Z80_OP16 ^ Z80_ARG16)) {
rz_asm_op_setf_asm(op, z_op[res].name, buf[2] + (buf[3] << 8));
}
if (z_op[res].type == (Z80_OP16^Z80_ARG8)) {
buf_asm = sdb_fmt (z_op[res].name, buf[2]);
if (z_op[res].type == (Z80_OP16 ^ Z80_ARG8)) {
rz_asm_op_setf_asm(op, z_op[res].name, buf[2]);
}
if (z_op[res].type == (Z80_OP24 ^ Z80_ARG8)) {
cb_tab = (const char **) z_op[res].op_moar;
buf_asm = sdb_fmt (cb_tab[z80_op_24_branch_index_res (buf[3])], buf[2]);
cb_tab = (const char **)z_op[res].op_moar;
rz_asm_op_setf_asm(op, cb_tab[z80_op_24_branch_index_res(buf[3])], buf[2]);
}
if (z_op[res].type == (Z80_OP16 ^ Z80_ARG8 ^ Z80_ARG16)) {
buf_asm = sdb_fmt (z_op[res].name, buf[2], buf[3]);
rz_asm_op_setf_asm(op, z_op[res].name, buf[2], buf[3]);
}
break;
default:
rz_asm_op_set_asm(op, "invalid");
break;
}
if (!strcmp (buf_asm, "invalid")) {
if (!strcmp(rz_asm_op_get_asm(op), "invalid")) {
ret = 0;
}
rz_asm_op_set_asm (op, buf_asm);
return ret;
}

10
librz/asm/p/asm_pic.c
View file

@ -11,17 +11,13 @@
static int asm_pic_disassemble(RzAsm *a, RzAsmOp *op, const ut8 *b, int l) {
int res = -1;
char opbuf[128];
const char *opstr = opbuf;
strcpy(opbuf, "invalid");
if (a->cpu && strcasecmp(a->cpu, "baseline") == 0) {
res = pic_baseline_disassemble(op, opbuf, b, l);
res = pic_baseline_disassemble(op, b, l);
} else if (a->cpu && strcasecmp(a->cpu, "midrange") == 0) {
res = pic_midrange_disassemble(op, opbuf, b, l);
res = pic_midrange_disassemble(op, b, l);
} else if (a->cpu && strcasecmp(a->cpu, "pic18") == 0) {
res = pic_pic18_disassemble(op, opbuf, b, l);
res = pic_pic18_disassemble(op, b, l);
}
rz_asm_op_set_asm(op, opstr);
return op->size = res;
}