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librz/arch: capstone v6 update (without MIPS) (#4662)

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* Bumps Capstone version to newest Capstone next (beyond first v6-Alpha1).
* Fixes leaks
* Fixes build and change to AArch64 and SystemZ compatibility headers.
* Marks M68k test as broken (see commit message).
* Fix AArch64 and SystemZ tests
* Handle op.size == 0 for x86 IL ops
This commit is contained in:
Rot127 2024-10-24 16:07:07 +00:00 committed by GitHub
parent 2fafb3dbe5
commit f82993a30d
No known key found for this signature in database
GPG key ID: B5690EEEBB952194
37 changed files with 1903 additions and 1864 deletions
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10
.github/workflows/ci.yml vendored
View file

@ -160,6 +160,16 @@ jobs:
timeout: 45
cflags: "-Wno-cpp"
allow_failure: true
- name: capstone-v6
os: ubuntu-22.04
build_system: meson
compiler: gcc
meson_options: -Dbuildtype=release -Duse_capstone_version=v6 --werror
run_tests: false
enabled: ${{ (github.event_name != 'pull_request' || contains(github.head_ref, 'capstone')) && needs.changes.outputs.edited == 'true' }}
timeout: 45
cflags: "-Wno-cpp"
allow_failure: false
- name: no-gpl-code
os: ubuntu-22.04
build_system: meson

2
doc/PACKAGERS.md
View file

@ -66,7 +66,7 @@ version of Capstone be dynamically linked at runtime. To do this, use the
`-Duse_sys_capstone=enabled` command line option when running `meson`.
You can override the version of Capstone Rizin will use by setting
`use_capstone_version` to one of `v4`, `v5` or `next`.
`use_capstone_version` to one of `v4`, `v5`, `v6` or `next`.
There are more bundled dependencies that can be swapped out for system versions.
At the time of writing, these are:

69
librz/arch/isa/arm/aarch64_meta_macros.h
View file

@ -1,69 +0,0 @@
// SPDX-FileCopyrightText: 2023 Rot127 <unisono@quyllur.org>
// SPDX-License-Identifier: LGPL-3.0-only
#ifndef AARCH64_META_MACROS_H
#define AARCH64_META_MACROS_H
#ifdef USE_SYS_CAPSTONE
/// Macro for meta programming.
/// Meant for projects using Capstone and need to support multiple
/// versions of it.
/// These macros replace several instances of the old "ARM64" with
/// the new "AArch64" name depending on the CS version.
#if CS_NEXT_VERSION < 6
#define CS_AARCH64(x) ARM64##x
#else
#define CS_AARCH64(x) AArch64##x
#endif
#if CS_NEXT_VERSION < 6
#define CS_AARCH64pre(x) x##ARM64
#else
#define CS_AARCH64pre(x) x##AARCH64
#endif
#if CS_NEXT_VERSION < 6
#define CS_AARCH64CC(x) ARM64_CC##x
#else
#define CS_AARCH64CC(x) AArch64CC##x
#endif
#if CS_NEXT_VERSION < 6
#define CS_AARCH64_VL_(x) ARM64_VAS_##x
#else
#define CS_AARCH64_VL_(x) AArch64Layout_VL_##x
#endif
#if CS_NEXT_VERSION < 6
#define CS_aarch64_ arm64
#else
#define CS_aarch64_ aarch64
#endif
#if CS_NEXT_VERSION < 6
#define CS_aarch64(x) arm64##x
#else
#define CS_aarch64(x) aarch64##x
#endif
#if CS_NEXT_VERSION < 6
#define CS_aarch64_op() cs_arm64_op
#define CS_aarch64_reg() arm64_reg
#define CS_aarch64_cc() arm64_cc
#define CS_cs_aarch64() cs_arm64
#define CS_aarch64_extender() arm64_extender
#define CS_aarch64_shifter() arm64_shifter
#define CS_aarch64_vas() arm64_vas
#else
#define CS_aarch64_op() cs_aarch64_op
#define CS_aarch64_reg() aarch64_reg
#define CS_aarch64_cc() AArch64CC_CondCode
#define CS_cs_aarch64() cs_aarch64
#define CS_aarch64_extender() aarch64_extender
#define CS_aarch64_shifter() aarch64_shifter
#define CS_aarch64_vas() AArch64Layout_VectorLayout
#endif
#endif // USE_SYS_CAPSTONE
#endif // AARCH64_META_MACROS_H

23
librz/arch/isa/arm/arm_accessors32.h
View file

@ -7,6 +7,9 @@
* cs_insn *insn
*/
#pragma GCC diagnostic ignored "-Wenum-compare"
#pragma GCC diagnostic ignored "-Wenum-conversion"
#define CAPSTONE_AARCH64_COMPAT_HEADER
#include <capstone/capstone.h>
#define REGID(x) insn->detail->arm.operands[x].reg
@ -27,14 +30,24 @@
#define ISMEM(x) (insn->detail->arm.operands[x].type == ARM_OP_MEM)
#define ISFPIMM(x) (insn->detail->arm.operands[x].type == ARM_OP_FP)
#define LSHIFT(x) insn->detail->arm.operands[x].mem.lshift
#define LSHIFT2(x) insn->detail->arm.operands[x].shift.value // Dangerous, returns value even if isn't LSL
#define OPCOUNT() insn->detail->arm.op_count
#define ISSHIFTED(x) (insn->detail->arm.operands[x].shift.type != ARM_SFT_INVALID && insn->detail->arm.operands[x].shift.value != 0)
#define SHIFTTYPE(x) insn->detail->arm.operands[x].shift.type
#if CS_NEXT_VERSION < 6
#define LSHIFT(x) insn->detail->arm.operands[x].mem.lshift
#else
#define LSHIFT(x) insn->detail->arm.operands[x].shift.value
#endif
#define LSHIFT2(x) insn->detail->arm.operands[x].shift.value // Dangerous, returns value even if isn't LSL
#define OPCOUNT() insn->detail->arm.op_count
#define ISSHIFTED(x) (insn->detail->arm.operands[x].shift.type != ARM_SFT_INVALID && insn->detail->arm.operands[x].shift.value != 0)
#define SHIFTTYPE(x) insn->detail->arm.operands[x].shift.type
#if CS_NEXT_VERSION < 6
#define SHIFTTYPEREG(x) (SHIFTTYPE(x) == ARM_SFT_ASR_REG || SHIFTTYPE(x) == ARM_SFT_LSL_REG || \
SHIFTTYPE(x) == ARM_SFT_LSR_REG || SHIFTTYPE(x) == ARM_SFT_ROR_REG || \
SHIFTTYPE(x) == ARM_SFT_RRX_REG)
#else
#define SHIFTTYPEREG(x) (SHIFTTYPE(x) == ARM_SFT_ASR_REG || SHIFTTYPE(x) == ARM_SFT_LSL_REG || \
SHIFTTYPE(x) == ARM_SFT_LSR_REG || SHIFTTYPE(x) == ARM_SFT_ROR_REG)
#endif
#define SHIFTVALUE(x) insn->detail->arm.operands[x].shift.value
#if CS_NEXT_VERSION >= 6

29
librz/arch/isa/arm/arm_accessors64.h
View file

@ -7,22 +7,23 @@
* cs_insn *insn
*/
#define CAPSTONE_AARCH64_COMPAT_HEADER
#include <capstone/capstone.h>
#define IMM64(x) (ut64)(insn->detail->CS_aarch64_.operands[x].imm)
#define INSOP64(x) insn->detail->CS_aarch64_.operands[x]
#define IMM64(x) (ut64)(insn->detail->arm64.operands[x].imm)
#define INSOP64(x) insn->detail->arm64.operands[x]
#define REGID64(x) insn->detail->CS_aarch64_.operands[x].reg
#define REGBASE64(x) insn->detail->CS_aarch64_.operands[x].mem.base
#define REGID64(x) insn->detail->arm64.operands[x].reg
#define REGBASE64(x) insn->detail->arm64.operands[x].mem.base
// s/index/base|reg/
#define HASMEMINDEX64(x) (insn->detail->CS_aarch64_.operands[x].mem.index != CS_AARCH64(_REG_INVALID))
#define MEMDISP64(x) (ut64) insn->detail->CS_aarch64_.operands[x].mem.disp
#define ISIMM64(x) (insn->detail->CS_aarch64_.operands[x].type == CS_AARCH64(_OP_IMM))
#define ISREG64(x) (insn->detail->CS_aarch64_.operands[x].type == CS_AARCH64(_OP_REG))
#define ISMEM64(x) (insn->detail->CS_aarch64_.operands[x].type == CS_AARCH64(_OP_MEM))
#define HASMEMINDEX64(x) (insn->detail->arm64.operands[x].mem.index != ARM64_REG_INVALID)
#define MEMDISP64(x) (ut64) insn->detail->arm64.operands[x].mem.disp
#define ISIMM64(x) (insn->detail->arm64.operands[x].type == ARM64_OP_IMM)
#define ISREG64(x) (insn->detail->arm64.operands[x].type == ARM64_OP_REG)
#define ISMEM64(x) (insn->detail->arm64.operands[x].type == ARM64_OP_MEM)
#define LSHIFT2_64(x) insn->detail->CS_aarch64_.operands[x].shift.value
#define OPCOUNT64() insn->detail->CS_aarch64_.op_count
#define LSHIFT2_64(x) insn->detail->arm64.operands[x].shift.value
#define OPCOUNT64() insn->detail->arm64.op_count
#if CS_NEXT_VERSION < 6
#define ISWRITEBACK64() (insn->detail->arm64.writeback == true)
@ -33,6 +34,6 @@
#define ISPREINDEX64() (((OPCOUNT64() == 2) && (ISMEM64(1)) && (ISWRITEBACK64())) || ((OPCOUNT64() == 3) && (ISMEM64(2)) && (ISWRITEBACK64())))
#define ISPOSTINDEX64() (((OPCOUNT64() == 3) && (ISIMM64(2)) && (ISWRITEBACK64())) || ((OPCOUNT64() == 4) && (ISIMM64(3)) && (ISWRITEBACK64())))
#else
#define ISPREINDEX64() (!insn->detail->CS_aarch64_.post_index && ISWRITEBACK64())
#define ISPOSTINDEX64() (insn->detail->CS_aarch64_.post_index && ISWRITEBACK64())
#endif
#define ISPREINDEX64() (!insn->detail->arm64.post_index && ISWRITEBACK64())
#define ISPOSTINDEX64() (insn->detail->arm64.post_index && ISWRITEBACK64())
#endif

6
librz/arch/isa/arm/arm_cs.h
View file

@ -5,8 +5,10 @@
#define RZ_ARM_CS_H
#include <rz_analysis.h>
#pragma GCC diagnostic ignored "-Wenum-compare"
#pragma GCC diagnostic ignored "-Wenum-conversion"
#define CAPSTONE_AARCH64_COMPAT_HEADER
#include <capstone/capstone.h>
#include "aarch64_meta_macros.h"
RZ_IPI int rz_arm_cs_analysis_op_32_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, csh *handle, cs_insn *insn, bool thumb);
RZ_IPI int rz_arm_cs_analysis_op_64_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, csh *handle, cs_insn *insn);
@ -19,7 +21,7 @@ RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, ARMCC_CondCode
#else
RZ_IPI const char *rz_arm32_cs_esil_prefix_cond(RzAnalysisOp *op, arm_cc cond_type);
#endif
RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, CS_aarch64_cc() cond_type);
RZ_IPI const char *rz_arm64_cs_esil_prefix_cond(RzAnalysisOp *op, ARM64CC_CondCode cond_type);
RZ_IPI RzILOpEffect *rz_arm_cs_32_il(csh *handle, cs_insn *insn, bool thumb);
RZ_IPI RzAnalysisILConfig *rz_arm_cs_32_il_config(bool big_endian);

5
librz/arch/isa/arm/arm_esil32.c
View file

@ -2,6 +2,9 @@
// SPDX-License-Identifier: LGPL-3.0-only
#include <rz_analysis.h>
#pragma GCC diagnostic ignored "-Wenum-compare"
#pragma GCC diagnostic ignored "-Wenum-conversion"
#define CAPSTONE_AARCH64_COMPAT_HEADER
#include <capstone/capstone.h>
#include "arm_cs.h"
@ -34,7 +37,9 @@ static const char *decode_shift(arm_shifter shift) {
case ARM_SFT_ROR:
case ARM_SFT_RRX:
case ARM_SFT_ROR_REG:
#if CS_NEXT_VERSION < 6
case ARM_SFT_RRX_REG:
#endif
return E_OP_RR;
default:

483
librz/arch/isa/arm/arm_esil64.c
View file

File diff suppressed because it is too large Load diff

8
librz/arch/isa/arm/arm_il32.c
View file

@ -3,6 +3,10 @@
#include <rz_analysis.h>
#include <rz_util/rz_assert.h>
#pragma GCC diagnostic ignored "-Wenum-compare"
#pragma GCC diagnostic ignored "-Wenum-conversion"
#define CAPSTONE_AARCH64_COMPAT_HEADER
#include <capstone/capstone.h>
#include "arm_cs.h"
@ -348,7 +352,9 @@ static bool is_reg_shift(arm_shifter type) {
case ARM_SFT_LSL_REG:
case ARM_SFT_LSR_REG:
case ARM_SFT_ROR_REG:
#if CS_NEXT_VERSION < 6
case ARM_SFT_RRX_REG:
#endif
return true;
default:
return false;
@ -401,7 +407,9 @@ shift(RzILOpBitVector *val, RZ_NULLABLE RzILOpBool **carry_out, arm_shifter type
SHIFTR0(val, dist),
SHIFTL0(DUP(val), NEG(DUP(dist))));
case ARM_SFT_RRX:
#if CS_NEXT_VERSION < 6
case ARM_SFT_RRX_REG:
#endif
if (carry_out) {
*carry_out = LSB(DUP(val));
}

1951
librz/arch/isa/arm/arm_il64.c
View file

File diff suppressed because it is too large Load diff

1
librz/arch/isa/arm/asm-arm.h
View file

@ -5,7 +5,6 @@
#define _INCLUDE_ARMASS_H_
#include <rz_types_base.h>
#include "aarch64_meta_macros.h"
int armass_assemble(const char *str, ut64 off, int thumb);

4
librz/arch/isa/x86/common.c
View file

@ -739,9 +739,9 @@ RZ_IPI RzILOpPure *x86_il_get_operand_bits(X86Op op, int analysis_bits, ut64 pc,
return x86_il_get_reg_bits(op.reg, analysis_bits, pc);
case X86_OP_IMM:
/* Immediate values are always sign extended */
return SN(op.size * BITS_PER_BYTE, op.imm);
return SN((op.size != 0 ? op.size : implicit_size) * BITS_PER_BYTE, op.imm);
case X86_OP_MEM:
return LOADW(BITS_PER_BYTE * op.size, x86_il_get_memaddr_bits(op.mem, analysis_bits, pc));
return LOADW((op.size != 0 ? op.size : implicit_size) * BITS_PER_BYTE, x86_il_get_memaddr_bits(op.mem, analysis_bits, pc));
default:
return NULL;
}

742
librz/arch/p/analysis/analysis_arm_cs.c
View file

File diff suppressed because it is too large Load diff

66
librz/arch/p/analysis/analysis_mips_cs.c
View file

@ -246,9 +246,11 @@ static int analyze_op_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8
ARG(0), ARG(1));
break;
case MIPS_INS_CMP:
#if CS_NEXT_VERSION < 6
case MIPS_INS_CMPU:
case MIPS_INS_CMPGU:
case MIPS_INS_CMPGDU:
#endif
case MIPS_INS_CMPI:
rz_strbuf_appendf(&op->esil, "%s,%s,==", ARG(1), ARG(0));
break;
@ -257,6 +259,7 @@ static int analyze_op_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8
"%s,%s,>>,31,%s,>>,?{,32,%s,32,-,0xffffffff,<<,0xffffffff,&,<<,}{,0,},|,%s,=",
ARG(2), ARG(1), ARG(1), ARG(2), ARG(0));
break;
#if CS_NEXT_VERSION < 6
case MIPS_INS_SHRAV:
case MIPS_INS_SHRAV_R:
case MIPS_INS_SHRA:
@ -272,6 +275,7 @@ static int analyze_op_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8
case MIPS_INS_SRL:
rz_strbuf_appendf(&op->esil, "%s,%s,>>,%s,=", ARG(2), ARG(1), ARG(0));
break;
#endif
case MIPS_INS_SLLV:
case MIPS_INS_SLL:
rz_strbuf_appendf(&op->esil, "%s,%s,<<,%s,=", ARG(2), ARG(1), ARG(0));
@ -320,7 +324,9 @@ static int analyze_op_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8
rz_strbuf_appendf(&op->esil, ES_TRAP_DS() "%s,%s,==,$z,?{," ES_J("%s") ",}",
ARG(0), ARG(1), ARG(2));
break;
#if CS_NEXT_VERSION < 6
case MIPS_INS_BZ:
#endif
case MIPS_INS_BEQZ:
case MIPS_INS_BEQZC:
rz_strbuf_appendf(&op->esil, ES_TRAP_DS() "%s,0,==,$z,?{," ES_J("%s") ",}",
@ -383,7 +389,9 @@ static int analyze_op_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8
case MIPS_INS_BTNEZ:
rz_strbuf_appendf(&op->esil, ES_TRAP_DS() "0,t,==,$z,!,?{," ES_J("%s") ",}", ARG(0));
break;
#if CS_NEXT_VERSION < 6
case MIPS_INS_MOV:
#endif
case MIPS_INS_MOVE:
PROTECT_ZERO() {
rz_strbuf_appendf(&op->esil, "%s,%s,=", ARG(1), REG(0));
@ -402,7 +410,9 @@ static int analyze_op_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8
ARG(2), ARG(1), REG(0));
}
break;
#if CS_NEXT_VERSION < 6
case MIPS_INS_FSUB:
#endif
case MIPS_INS_SUB:
case MIPS_INS_SUBU:
case MIPS_INS_DSUB:
@ -413,7 +423,9 @@ static int analyze_op_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8
}
break;
case MIPS_INS_NEG:
#if CS_NEXT_VERSION < 6
case MIPS_INS_NEGU:
#endif
rz_strbuf_appendf(&op->esil, "%s,0,-,%s,=,",
ARG(1), ARG(0));
break;
@ -452,7 +464,9 @@ static int analyze_op_esil(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8
}
} break;
case MIPS_INS_LI:
#if CS_NEXT_VERSION < 6
case MIPS_INS_LDI:
#endif
rz_strbuf_appendf(&op->esil, "0x%" PFMT64x ",%s,=", (ut64)IMM(1), ARG(0));
break;
case MIPS_INS_LUI:
@ -859,11 +873,20 @@ static int analyze_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const u
case MIPS_INS_JALR:
op->type = RZ_ANALYSIS_OP_TYPE_UCALL;
op->delay = 1;
#if CS_NEXT_VERSION < 6
if (REGID(0) == MIPS_REG_25) {
op->jump = t9_pre;
t9_pre = UT64_MAX;
op->type = RZ_ANALYSIS_OP_TYPE_RCALL;
}
#else
if (REGID(0) == MIPS_REG_T9 ||
REGID(0) == MIPS_REG_T9_64) {
op->jump = t9_pre;
t9_pre = UT64_MAX;
op->type = RZ_ANALYSIS_OP_TYPE_RCALL;
}
#endif
break;
case MIPS_INS_JAL:
case MIPS_INS_JALS:
@ -927,26 +950,30 @@ static int analyze_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const u
op->stackptr = -IMM(2);
}
break;
case MIPS_INS_SUB:
#if CS_NEXT_VERSION < 6
case MIPS_INS_SUBV:
case MIPS_INS_SUBVI:
case MIPS_INS_DSUBU:
case MIPS_INS_FSUB:
case MIPS_INS_FMSUB:
case MIPS_INS_SUBU:
case MIPS_INS_DSUB:
case MIPS_INS_SUBS_S:
case MIPS_INS_SUBS_U:
case MIPS_INS_SUBUH:
case MIPS_INS_SUBUH_R:
#endif
case MIPS_INS_SUB:
case MIPS_INS_DSUBU:
case MIPS_INS_SUBU:
case MIPS_INS_DSUB:
SET_VAL(op, 2);
op->sign = insn->id == MIPS_INS_SUB;
op->type = RZ_ANALYSIS_OP_TYPE_SUB;
break;
#if CS_NEXT_VERSION < 6
case MIPS_INS_MULV:
case MIPS_INS_MULT:
case MIPS_INS_MULSA:
case MIPS_INS_FMUL:
#endif
case MIPS_INS_MULT:
case MIPS_INS_MUL:
case MIPS_INS_DMULT:
case MIPS_INS_DMULTU:
@ -977,28 +1004,34 @@ static int analyze_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const u
case MIPS_INS_DIVU:
case MIPS_INS_DDIV:
case MIPS_INS_DDIVU:
case MIPS_INS_FDIV:
case MIPS_INS_DIV_S:
#if CS_NEXT_VERSION < 6
case MIPS_INS_FDIV:
case MIPS_INS_DIV_U:
#endif
op->type = RZ_ANALYSIS_OP_TYPE_DIV;
break;
#if CS_NEXT_VERSION < 6
case MIPS_INS_CMPGDU:
case MIPS_INS_CMPGU:
case MIPS_INS_CMPU:
#endif
case MIPS_INS_CMPI:
op->type = RZ_ANALYSIS_OP_TYPE_CMP;
break;
#if CS_NEXT_VERSION < 6
case MIPS_INS_BZ:
case MIPS_INS_BNZ:
case MIPS_INS_BNEG:
case MIPS_INS_BNEGI:
#endif
case MIPS_INS_J:
case MIPS_INS_B:
case MIPS_INS_BZ:
case MIPS_INS_BEQ:
case MIPS_INS_BNZ:
case MIPS_INS_BNE:
case MIPS_INS_BNEL:
case MIPS_INS_BEQL:
case MIPS_INS_BEQZ:
case MIPS_INS_BNEG:
case MIPS_INS_BNEGI:
case MIPS_INS_BNEZ:
case MIPS_INS_BTEQZ:
case MIPS_INS_BTNEZ:
@ -1053,10 +1086,19 @@ static int analyze_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const u
op->type = RZ_ANALYSIS_OP_TYPE_RET;
t9_pre = UT64_MAX;
}
#if CS_NEXT_VERSION < 6
if (REGID(0) == MIPS_REG_25) {
op->jump = t9_pre;
t9_pre = UT64_MAX;
}
#else
if (REGID(0) == MIPS_REG_T9 ||
REGID(0) == MIPS_REG_T9_64) {
op->jump = t9_pre;
t9_pre = UT64_MAX;
op->type = RZ_ANALYSIS_OP_TYPE_RCALL;
}
#endif
break;
case MIPS_INS_SLT:
@ -1067,6 +1109,7 @@ static int analyze_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const u
case MIPS_INS_SLTIU:
SET_VAL(op, 2);
break;
#if CS_NEXT_VERSION < 6
case MIPS_INS_SHRAV:
case MIPS_INS_SHRAV_R:
case MIPS_INS_SHRA:
@ -1076,8 +1119,9 @@ static int analyze_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const u
SET_VAL(op, 2);
break;
case MIPS_INS_SHRL:
case MIPS_INS_SRLV:
case MIPS_INS_SRL:
#endif
case MIPS_INS_SRLV:
op->type = RZ_ANALYSIS_OP_TYPE_SHR;
SET_VAL(op, 2);
break;

33
librz/arch/p/analysis/analysis_sysz.c
View file

@ -3,6 +3,9 @@
#include <rz_analysis.h>
#include <rz_lib.h>
#pragma GCC diagnostic ignored "-Wenum-compare"
#pragma GCC diagnostic ignored "-Wenum-conversion"
#define CAPSTONE_SYSTEMZ_COMPAT_HEADER
#include <capstone/capstone.h>
#include <capstone/systemz.h>
// instruction set: http://www.tachyonsoft.com/inst390m.htm
@ -96,35 +99,37 @@ static int analyze_op(RzAnalysis *a, RzAnalysisOp *op, ut64 addr, const ut8 *buf
case SYSZ_INS_BRCTG:
op->type = RZ_ANALYSIS_OP_TYPE_CJMP;
break;
case SYSZ_INS_JE:
#if CS_NEXT_VERSION < 6
case SYSZ_INS_JGE:
case SYSZ_INS_JHE:
case SYSZ_INS_JGHE:
case SYSZ_INS_JH:
case SYSZ_INS_JGH:
case SYSZ_INS_JLE:
case SYSZ_INS_JGLE:
case SYSZ_INS_JLH:
case SYSZ_INS_JGLH:
case SYSZ_INS_JL:
case SYSZ_INS_JGL:
case SYSZ_INS_JNE:
case SYSZ_INS_JGNE:
case SYSZ_INS_JNHE:
case SYSZ_INS_JGNHE:
case SYSZ_INS_JNH:
case SYSZ_INS_JGNH:
case SYSZ_INS_JNLE:
case SYSZ_INS_JGNLE:
case SYSZ_INS_JNLH:
case SYSZ_INS_JGNLH:
case SYSZ_INS_JNL:
case SYSZ_INS_JGNL:
case SYSZ_INS_JNO:
case SYSZ_INS_JGNO:
case SYSZ_INS_JO:
case SYSZ_INS_JGO:
case SYSZ_INS_JG:
#endif
case SYSZ_INS_JNE:
case SYSZ_INS_JNHE:
case SYSZ_INS_JNH:
case SYSZ_INS_JNL:
case SYSZ_INS_JE:
case SYSZ_INS_JHE:
case SYSZ_INS_JH:
case SYSZ_INS_JLE:
case SYSZ_INS_JLH:
case SYSZ_INS_JL:
case SYSZ_INS_JNLE:
case SYSZ_INS_JNLH:
case SYSZ_INS_JNO:
case SYSZ_INS_JO:
op->type = RZ_ANALYSIS_OP_TYPE_CJMP;
op->jump = INSOP(0).imm;
op->fail = addr + op->size;

5
librz/arch/p/asm/asm_arm_cs.c
View file

@ -4,6 +4,9 @@
#include <rz_asm.h>
#include <rz_lib.h>
#include <rz_util/ht_uu.h>
#pragma GCC diagnostic ignored "-Wenum-compare"
#pragma GCC diagnostic ignored "-Wenum-conversion"
#define CAPSTONE_AARCH64_COMPAT_HEADER
#include <capstone/capstone.h>
#include "arm/asm-arm.h"
#include "arm/arm_it.h"
@ -95,7 +98,7 @@ static int disassemble(RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) {
rz_strbuf_set(&op->buf_asm, "");
}
if (!ctx->cd || mode != ctx->omode) {
ret = (a->bits == 64) ? cs_open(CS_AARCH64pre(CS_ARCH_), mode, &ctx->cd) : cs_open(CS_ARCH_ARM, mode, &ctx->cd);
ret = (a->bits == 64) ? cs_open(CS_ARCH_ARM64, mode, &ctx->cd) : cs_open(CS_ARCH_ARM, mode, &ctx->cd);
if (ret) {
ret = -1;
goto beach;

2
librz/arch/p/asm/asm_sysz.c
View file

@ -7,6 +7,7 @@
#include <rz_lib.h>
#include "cs_helper.h"
#include <rz_util/rz_log.h>
CAPSTONE_DEFINE_PLUGIN_FUNCTIONS(sysz);
@ -25,6 +26,7 @@ static int sysz_disassemble(RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) {
if (!ctx->handle) {
ret = cs_open(CS_ARCH_SYSZ, mode, &ctx->handle);
if (ret) {
RZ_LOG_ERROR("Failed to initialize Capstone: '%s'\n", cs_strerror(ret));
return -1;
}
ctx->omode = mode;

3
librz/arch/p/asm/cs_helper.h
View file

@ -3,6 +3,9 @@
// SPDX-License-Identifier: LGPL-3.0-only
#include <rz_util.h>
#pragma GCC diagnostic ignored "-Wenum-compare"
#pragma GCC diagnostic ignored "-Wenum-conversion"
#define CAPSTONE_SYSTEMZ_COMPAT_HEADER
#include <capstone/capstone.h>
typedef struct {

2
meson_options.txt
View file

@ -21,7 +21,7 @@ option('rizin_bindings', type: 'string', value: '', description: 'Path where riz
option('checks_level', type: 'integer', value: 9999, description: 'Value between 0 and 3 to enable different level of assert (see RZ_CHECKS_LEVEL). By default its value depends on buildtype (2 on debug, 1 on release).')
option('use_sys_capstone', type: 'feature', value: 'disabled')
option('use_capstone_version', type: 'combo', choices: ['v4', 'v5', 'next'], value: 'next', description: 'Specify which version of capstone to use')
option('use_capstone_version', type: 'combo', choices: ['v4', 'v5', 'v6', 'next'], value: 'next', description: 'Specify which version of capstone to use')
option('use_sys_magic', type: 'feature', value: 'disabled')
option('use_sys_libzip', type: 'feature', value: 'disabled')
option('use_sys_libzip_openssl', type: 'boolean', value: false, description: 'Whether to use or not system openssl dependency to build libzip')

2
subprojects/capstone-next.wrap
View file

@ -1,6 +1,6 @@
[wrap-git]
url = https://github.com/capstone-engine/capstone.git
revision = eb4fc2d7612db10379adf7aeb287a7923dcc0fc7
revision = 32519c01efbcfb1bf29bdfc3ad0ad574aea369d9
directory = capstone-next
patch_directory = capstone-next
depth = 1

6
subprojects/capstone-v6.wrap Normal file
View file

@ -0,0 +1,6 @@
[wrap-git]
url = https://github.com/capstone-engine/capstone.git
revision = v6
patch_directory = capstone-6.0.0-alpha1
directory = capstone-6.0.0
depth = 1

25
subprojects/packagefiles/capstone-auto-sync-aarch64/meson.build → subprojects/packagefiles/capstone-6.0.0-alpha1/meson.build
View file

@ -1,6 +1,10 @@
project('capstone', 'c', version: '5.0.1', meson_version: '>=0.55.0')
project('capstone', 'c', version: 'next', meson_version: '>=0.55.0')
cs_files = [
'arch/Alpha/AlphaDisassembler.c',
'arch/Alpha/AlphaInstPrinter.c',
'arch/Alpha/AlphaMapping.c',
'arch/Alpha/AlphaModule.c',
'arch/AArch64/AArch64BaseInfo.c',
'arch/AArch64/AArch64Disassembler.c',
'arch/AArch64/AArch64DisassemblerExtension.c',
@ -13,6 +17,10 @@ cs_files = [
'arch/ARM/ARMInstPrinter.c',
'arch/ARM/ARMMapping.c',
'arch/ARM/ARMModule.c',
'arch/HPPA/HPPADisassembler.c',
'arch/HPPA/HPPAInstPrinter.c',
'arch/HPPA/HPPAMapping.c',
'arch/HPPA/HPPAModule.c',
'arch/M680X/M680XDisassembler.c',
'arch/M680X/M680XInstPrinter.c',
'arch/M680X/M680XModule.c',
@ -31,11 +39,12 @@ cs_files = [
'arch/Sparc/SparcInstPrinter.c',
'arch/Sparc/SparcMapping.c',
'arch/Sparc/SparcModule.c',
'arch/SystemZ/SystemZDisassembler.c',
'arch/SystemZ/SystemZInstPrinter.c',
'arch/SystemZ/SystemZMapping.c',
'arch/SystemZ/SystemZMCTargetDesc.c',
'arch/SystemZ/SystemZModule.c',
'arch/SystemZ/SystemZMapping.c',
'arch/SystemZ/SystemZDisassemblerExtension.c',
'arch/SystemZ/SystemZMCTargetDesc.c',
'arch/SystemZ/SystemZDisassembler.c',
'arch/TMS320C64x/TMS320C64xDisassembler.c',
'arch/TMS320C64x/TMS320C64xInstPrinter.c',
'arch/TMS320C64x/TMS320C64xMapping.c',
@ -72,20 +81,26 @@ libcapstone_c_args = [
'-DCAPSTONE_X86_REDUCE_NO',
'-DCAPSTONE_USE_SYS_DYN_MEM',
'-DCAPSTONE_DIET_NO',
'-DCAPSTONE_HAS_ALPHA',
'-DCAPSTONE_HAS_ARM',
'-DCAPSTONE_HAS_AARCH64',
'-DCAPSTONE_HAS_HPPA',
'-DCAPSTONE_HAS_M68K',
'-DCAPSTONE_HAS_M680X',
'-DCAPSTONE_HAS_MIPS',
'-DCAPSTONE_HAS_POWERPC',
'-DCAPSTONE_HAS_SPARC',
'-DCAPSTONE_HAS_SYSZ',
'-DCAPSTONE_HAS_SYSTEMZ',
'-DCAPSTONE_HAS_X86',
'-DCAPSTONE_HAS_XCORE',
'-DCAPSTONE_HAS_TMS320C64X',
'-DCAPSTONE_HAS_TRICORE',
]
if meson.get_compiler('c').has_argument('-Wmaybe-uninitialized')
libcapstone_c_args += '-Wno-maybe-uninitialized'
endif
libcapstone = library('capstone', cs_files,
c_args: libcapstone_c_args,
include_directories: capstone_includes,

3
subprojects/packagefiles/capstone-next/meson.build
View file

@ -39,6 +39,7 @@ cs_files = [
'arch/Sparc/SparcInstPrinter.c',
'arch/Sparc/SparcMapping.c',
'arch/Sparc/SparcModule.c',
'arch/SystemZ/SystemZDisassemblerExtension.c',
'arch/SystemZ/SystemZDisassembler.c',
'arch/SystemZ/SystemZInstPrinter.c',
'arch/SystemZ/SystemZMapping.c',
@ -89,7 +90,7 @@ libcapstone_c_args = [
'-DCAPSTONE_HAS_MIPS',
'-DCAPSTONE_HAS_POWERPC',
'-DCAPSTONE_HAS_SPARC',
'-DCAPSTONE_HAS_SYSZ',
'-DCAPSTONE_HAS_SYSTEMZ',
'-DCAPSTONE_HAS_X86',
'-DCAPSTONE_HAS_XCORE',
'-DCAPSTONE_HAS_TMS320C64X',

4
test/db/analysis/arm64
View file

@ -108,7 +108,7 @@ pseudo: asm("irg x8, sp, x8")
mnemonic: irg
mask: ffffffff
prefix: 0
id: 455
id: 495
bytes: e813c89a
refptr: 0
size: 4
@ -190,7 +190,7 @@ pseudo: asm("irg x8, sp, x8")
mnemonic: irg
mask: ffffffff
prefix: 0
id: 455
id: 495
bytes: 9ac813e8
refptr: 0
size: 4

14
test/db/analysis/mips
View file

@ -12,6 +12,7 @@ RUN
NAME=mozi aae functions
FILE=bins/elf/mips-mozi
BROKEN=1
CMDS=<<EOF
aae
aflc
@ -23,6 +24,7 @@ RUN
NAME=mips hello ref anal
FILE=bins/elf/analysis/mips.elf
BROKEN=1
ARGS=-e bin.strings=false -e analysis.strings=true
CMDS=<<EOF
e asm.bytes=true
@ -55,6 +57,7 @@ RUN
NAME=Calculate GP
FILE=bins/elf/analysis/mips64r2-ld-2.28.so
BROKEN=1
CMDS=<<EOF
s 0x000023f0
e asm.bytes=true
@ -70,6 +73,7 @@ RUN
NAME=mips ld(load doubleword) instruction
FILE=bins/elf/analysis/mips64r2-busybox-loongson
BROKEN=1
CMDS=<<EOF
s 0x120004460
e asm.bytes=true
@ -152,6 +156,7 @@ RUN
NAME=mips pseudo sw + 0
FILE=malloc://32
BROKEN=1
ARGS=-a mips -m 0x80100000
CMDS=<<EOF
e io.va=true
@ -169,6 +174,7 @@ RUN
NAME=mips LE anal
FILE=malloc://32
BROKEN=1
CMDS=<<EOF
wx 01001104
e asm.arch=mips
@ -443,6 +449,7 @@ RUN
NAME=mips branch delay function detection #1.
FILE=malloc://160
BROKEN=1
ARGS=-m 0x8060b4f8
CMDS=<<EOF
e io.va=true
@ -576,6 +583,7 @@ RUN
NAME=capstone: mips branch delay function detection #1.
FILE=malloc://160
BROKEN=1
ARGS=-m 0x8060b4f8
CMDS=<<EOF
e io.va=true
@ -646,6 +654,7 @@ RUN
NAME=capstone: mips branch delay function detection #2.
FILE=malloc://160
BROKEN=1
ARGS=-m 0x8060b4f8
CMDS=<<EOF
e io.va=true
@ -716,6 +725,7 @@ RUN
NAME=mips big endian strings, calls, etc. analysis
FILE=bins/elf/analysis/mipsbe-ip
BROKEN=1
CMDS=<<EOF
s 0x00402088
e asm.bytes=true
@ -736,7 +746,8 @@ EOF
RUN
NAME=mips.gnu regs
FILE=
FILE==
BROKEN=1
CMDS=<<EOF
e asm.arch=mips.gnu
ar
@ -780,6 +791,7 @@ RUN
NAME=mips sp/bp tracking
FILE=bins/elf/vars-mips-bp
BROKEN=1
ARGS=-e bin.dbginfo=0
CMDS=<<EOF
s sym.varfunc

111
test/db/analysis/sparc
View file

@ -157,104 +157,27 @@ RUN
NAME=analysis.fcnprefix sparc
FILE=bins/elf/elf-solaris-sparc-ls
CMDS=<<EOF
# The test before showed not a single function with a 'root' prefix.
# No idea if those discovered functions are actual functions.
# But at least they are named 'root.xxxxxx'.
s 0x00018c08
e analysis.fcnprefix=root
af
afl
aac
afl~root
EOF
EXPECT=<<EOF
0x00013620 12 240 sym.dired_dump_obstack
0x00013774 1 16 sym.dev_ino_free
0x00013784 1 32 sym.free_pending_ent
0x000137a4 9 132 sym.is_colored
0x0001386c 5 180 sym.clear_files
0x00013920 1 40 sym.add_ignore_pattern
0x00013948 1 64 sym.get_funky_string
0x00013c38 5 104 sym.queue_directory
0x00013cd8 1 52 sym.file_failure
0x00013d0c 6 72 sym.patterns_match
0x00013d80 22 476 -> 344 sym.extract_dirs_from_files
0x00015c2c 13 396 -> 364 sym.sort_files
0x00015f6c 129 2740 -> 2472 sym.gobble_file
0x00016a20 31 748 -> 504 sym.quote_name
0x00016da0 31 420 sym.restore_default_color
0x00017b7c 3 3544 -> 56 sym.print_current_files
0x00018954 4 692 sym.usage
0x00018c08 344 8388 -> 7256 main
0x0001b334 7 136 sym.set_program_name
0x0001b3e4 16 324 -> 316 sym.version_etc_va
0x0001b528 1 48 sym.version_etc
0x0001b558 1 44 sym.xalloc_die
0x0001b59c 14 248 sym.argmatch
0x0001b694 3 88 sym.argmatch_invalid
0x0001b6ec 9 248 sym.argmatch_valid
0x0001b7e4 3 88 sym.__xargmatch_internal
0x0001ba88 1 8 sym.dirfd
0x0001bb8c 4 120 sym.error
0x0001caf4 198 2792 -> 2720 sym.internal_fnmatch
0x0001e84c 3 552 -> 76 sym.gnu_fnmatch
0x0001eb64 181 3004 sym._getopt_internal_r
0x0001f720 1 116 sym._getopt_internal
0x0001f7c4 1 44 sym.rpl_getopt_long
0x0001f8d0 10 184 sym.hard_locale
0x0001f998 1 8 sym.hash_get_n_entries
0x0001ff34 27 480 sym.hash_initialize
0x000201f0 26 324 sym.hash_free
0x00021a50 26 416 -> 396 sym.human_options
0x00022250 8 224 sym._obstack_begin
0x00022414 23 408 sym._obstack_newchunk
0x00022768 1 700 sym.quote
0x00022a24 2 56 sym.clone_quoting_options
0x00022a5c 2 24 sym.get_quoting_style
0x00022a74 2 24 sym.set_quoting_style
0x00022a8c 2 80 sym.set_char_quoting
0x00022afc 1 12 sym.quoting_options_from_style
0x00023634 15 372 sym.quotearg_n_options
0x000237a8 1 28 sym.quotearg_n
0x000237c4 1 24 sym.quotearg_n_mem
0x000237dc 1 108 sym.quotearg
0x0002396c 3 588 sym.quotearg_colon
0x000255f0 3 56 sym.xmalloc
0x00025720 1 32 sym.xmemdup
0x00025740 1 24 sym.xstrdup
0x00025758 14 436 sym.xstrtol_fatal
0x00025948 53 796 sym.xstrtoul
0x0003f98c 2 56 sym.imp.atexit
0x0003f998 1 8 sym.imp.exit
0x0003f9d4 1 8 sym.imp.fputs
0x0003f9e0 1 8 sym.imp.printf
0x0003f9ec 1 8 sym.imp.__flsbuf
0x0003f9f8 1 8 sym.imp.free
0x0003fa04 1 8 sym.imp.strncmp
0x0003fa28 1 8 sym.imp.strcmp
0x0003fa40 1 8 sym.imp..udiv
0x0003fa4c 1 8 sym.imp..umul
0x0003fa64 1 8 sym.imp.__assert_c99
0x0003fa70 1 8 sym.imp.strlen
0x0003faa0 1 8 sym.imp.stat64
0x0003fb00 1 8 sym.imp.fwrite
0x0003fb0c 1 8 sym.imp.memcpy
0x0003fb18 1 8 sym.imp.fflush
0x0003fb30 1 8 sym.imp.raise
0x0003fb3c 1 8 sym.imp.signal
0x0003fb60 1 8 sym.imp.abort
0x0003fb6c 1 8 sym.imp.fprintf
0x0003fb78 1 8 sym.imp.setlocale
0x0003fb84 1 8 sym.imp.getenv
0x0003fb90 1 8 sym.imp.ioctl
0x0003fb9c 1 8 sym.imp.opendir
0x0003fba8 1 8 sym.imp.fstat64
0x0003fbb4 1 8 sym.imp.readdir64
0x0003fbc0 1 8 sym.imp.closedir
0x0003fbcc 1 8 sym.imp.sigismember
0x0003fbd8 1 8 sym.imp.isatty
0x0003fbe4 1 8 sym.imp.strchr
0x0003fbf0 1 8 sym.imp.tcgetpgrp
0x0003fbfc 1 8 sym.imp.sigemptyset
0x0003fc08 1 8 sym.imp.sigaction
0x0003fc14 1 8 sym.imp.sigaddset
0x0003fc20 1 8 sym.imp.malloc
0x0003fc2c 1 8 sym.imp.acl_trivial
0x00012d9c 1 8 root.00012d9c
0x00020110 17 224 root.00020110
0x0002b180 1 8 root.0002b180
0x0002b538 1 8 root.0002b538
0x0002b938 1 8 root.0002b938
0x0002bca4 1 8 root.0002bca4
0x0002c05c 1 8 root.0002c05c
0x0002c880 1 16 root.0002c880
0x0003f9b0 1 8 root.0003f9b0
0x0003f9bc 1 8 root.0003f9bc
0x0003f9c8 1 8 root.0003f9c8
EOF
RUN
@ -584,7 +507,7 @@ EXPECT=<<EOF
0x0001bc98 0x0001bca8 00:0000 16 j 0x0001bcf8 f 0x0001bca8
0x0001bca8 0x0001bcbc 00:0000 20 j 0x0001bcf8 f 0x0001bcbc
0x0001bcbc 0x0001bcc4 00:0000 8 j 0x0001bc34 f 0x0001bcc4
0x0001bcc4 0x0001bcec 00:0000 40 f 0x0001bcec
0x0001bcc4 0x0001bcec 00:0000 40 j 0x0001bc70 f 0x0001bcec
0x0001bcec 0x0001bcf8 00:0000 12 j 0x0001bc70 f 0x0001bcf8
0x0001bcf8 0x0001bd00 00:0000 8
EOF

4
test/db/analysis/sysz
View file

@ -21,11 +21,11 @@ EXPECT=<<EOF
"operands": [
{
"type": "reg",
"value": "4"
"value": "r4"
},
{
"type": "mem",
"base": "15",
"base": "r15",
"disp": 8
}
]

3
test/db/analysis/tricore
View file

@ -365,6 +365,8 @@ pdf
EOF
EXPECT=<<EOF
0x80080020 1 10 entry0
0x8008245a 1 6 fcn.8008245a
0x80082564 1 12 fcn.80082564
0x80082d14 1 206 fcn.80082d14
0x80082de2 1 84 fcn.80082de2
0x800830d8 42 3622 fcn.800830d8
@ -469,6 +471,7 @@ EXPECT=<<EOF
0x8008a77a 4 38 -> 24 fcn.8008a77a
0x8008a78c 1 4 fcn.8008a78c
0x8008a790 1 10 fcn.8008a790
0xc0000000 4 28 fcn.c0000000
;-- section..start_tc0:
;-- segment.LOAD6:
/ entry0();

4
test/db/asm/arm_64
View file

@ -538,8 +538,8 @@ d "ldr x1, [x2, 0x18]!" 418c41f8 0x0 (seq (set x1 (loadw 0 64 (+ (var x2) (bv 64
d "ldr x1, [x2, -0x18]!" 418c5ef8 0x0 (seq (set x1 (loadw 0 64 (- (var x2) (bv 64 0x18)))) (set x2 (- (var x2) (bv 64 0x18))))
d "ldr x1, [x2], 0x18" 418441f8 0x0 (seq (set x1 (loadw 0 64 (var x2))) (set x2 (+ (var x2) (bv 64 0x18))))
d "ldr x1, [x2], -0x18" 41845ef8 0x0 (seq (set x1 (loadw 0 64 (var x2))) (set x2 (- (var x2) (bv 64 0x18))))
d "ldr x1, 0x1028" 41010058 0x1000 (set x1 (loadw 0 64 (bv 64 0x1028)))
d "ldr w1, 0x1044" 21020018 0x1000 (set x1 (cast 64 false (loadw 0 32 (bv 64 0x1044))))
d "ldr x1, 0x1028" 41010058 0x1000 (set x1 (loadw 0 64 (+ (bv 64 0x0) (bv 64 0x1028))))
d "ldr w1, 0x1044" 21020018 0x1000 (set x1 (cast 64 false (loadw 0 32 (+ (bv 64 0x0) (bv 64 0x1044)))))
d "ldrb w1, [x2]" 41004039 0x0 (set x1 (cast 64 false (load 0 (var x2))))
d "ldrh w1, [x2]" 41004079 0x0 (set x1 (cast 64 false (loadw 0 16 (var x2))))
d "ldrb w1, [x2], 3" 41344038 0x0 (seq (set x1 (cast 64 false (load 0 (var x2)))) (set x2 (+ (var x2) (bv 64 0x3))))

64
test/db/asm/mips_64
View file

@ -4,10 +4,10 @@ d "addiu zero, t0, -0x19" e7ff0025 0x4
d "addiu zero, t0, 0" 00000025 0x4
d "andi zero, zero, 0" 00000030 0x4
d "b 8" 00000010 0x4
d "bc0f 8" 00000041 0x4
dB "bc0f 8" 00000041 0x4
d "bc1f 8" 00000045 0x4
d "bc2f 8" 00000049 0x4
d "bc3f 8" 0000004d 0x4
dB "bc2f 8" 00000049 0x4
dB "bc3f 8" 0000004d 0x4
d "beq t0, s0, 0x444c" 11111011 0x4
d "beql sp, t8, 0x14008" 0050b853 0x4
d "beqz t0, 8" 00000011 0x4
@ -24,48 +24,48 @@ d "bltzl s6, 0x118" 4400c206 0x4
d "bne t0, s0, 0x440c" 01111015 0x4
d "bnel s0, s0, -0xbff8" 00d01056 0x4
d "bnez zero, 8" 00000014 0x4
d "cache 0, (zero)" 000000bc 0x4
dB "cache 0, (zero)" 000000bc 0x4
d "daddi zero, zero, 0" 00000060 0x4
d "daddiu zero, zero, 0" 00000064 0x4
d "j 0" 00000008 0x4
d "jal 0" 0000000c 0x4
d "jalx 0" 00000074 0x4
d "jalx 4" 01000074 0x4
d "lb zero, (zero)" 00000080 0x4
d "lbu zero, (zero)" 00000090 0x4
d "ldc1 f0, (zero)" 000000d4 0x4
d "ldl zero, (zero)" 00000068 0x4
d "ldr zero, (zero)" 0000006c 0x4
d "lh zero, (zero)" 00000084 0x4
d "lhu zero, (zero)" 00000094 0x4
d "ll zero, (zero)" 000000c0 0x4
d "lld zero, (zero)" 000000d0 0x4
dB "lb zero, (zero)" 00000080 0x4
dB "lbu zero, (zero)" 00000090 0x4
dB "ldc1 f0, (zero)" 000000d4 0x4
dB "ldl zero, (zero)" 00000068 0x4
dB "ldr zero, (zero)" 0000006c 0x4
dB "lh zero, (zero)" 00000084 0x4
dB "lhu zero, (zero)" 00000094 0x4
dB "ll zero, (zero)" 000000c0 0x4
dB "lld zero, (zero)" 000000d0 0x4
d "lui zero, 0" 0000003c 0x4
d "lw zero, (zero)" 0000008c 0x4
d "lwc1 f0, (zero)" 000000c4 0x4
d "lwl zero, (zero)" 00000088 0x4
d "lwr zero, (zero)" 00000098 0x4
d "lwu zero, (zero)" 0000009c 0x4
dB "lw zero, (zero)" 0000008c 0x4
dB "lwc1 f0, (zero)" 000000c4 0x4
dB "lwl zero, (zero)" 00000088 0x4
dB "lwr zero, (zero)" 00000098 0x4
dB "lwu zero, (zero)" 0000009c 0x4
d "lwxc1 f0, zero(zero)" 0000004c 0x4
d "mfc0 zero, zero, 0" 00000040 0x4
dB "mfc0 zero, zero, 0" 00000040 0x4
d "mfc1 zero, f0" 00000044 0x4
d "mfc2 zero, zero, 0" 00000048 0x4
dB "mfc2 zero, zero, 0" 00000048 0x4
d "nop" 00000000 0x4
d "ori zero, t0, 0" 00000035 0x4
d "sb zero, (zero)" 000000a0 0x4
d "sc zero, (zero)" 000000e0 0x4
d "scd zero, (zero)" 000000f0 0x4
d "sd zero, (zero)" 000000fc 0x4
d "sdc1 f0, (zero)" 000000f4 0x4
d "sdl zero, (zero)" 000000b0 0x4
d "sdr zero, (zero)" 000000b4 0x4
d "sh zero, (zero)" 000000a4 0x4
dB "sb zero, (zero)" 000000a0 0x4
dB "sc zero, (zero)" 000000e0 0x4
dB "scd zero, (zero)" 000000f0 0x4
dB "sd zero, (zero)" 000000fc 0x4
dB "sdc1 f0, (zero)" 000000f4 0x4
dB "sdl zero, (zero)" 000000b0 0x4
dB "sdr zero, (zero)" 000000b4 0x4
dB "sh zero, (zero)" 000000a4 0x4
d "slti zero, zero, 0" 00000028 0x4
d "sltiu zero, zero, 0" 0000002c 0x4
d "sw zero, (zero)" 000000ac 0x4
d "swc1 f0, (zero)" 000000e4 0x4
d "swl zero, (zero)" 000000a8 0x4
d "swr zero, (zero)" 000000b8 0x4
dB "sw zero, (zero)" 000000ac 0x4
dB "swc1 f0, (zero)" 000000e4 0x4
dB "swl zero, (zero)" 000000a8 0x4
dB "swr zero, (zero)" 000000b8 0x4
d "xori zero, zero, 0" 00000038 0x4
dB "beqzl zero, 8" 00000050 0x4
dB "bnezl t0, 8" 00000055 0x4

4
test/db/asm/mips_v2_64
View file

@ -1,2 +1,2 @@
d "lwc3 0, (zero)" 000000cc
d "swc3 0, (zero)" 000000ec
dB "lwc3 0, (zero)" 000000cc
dB "swc3 0, (zero)" 000000ec

50
test/db/asm/tricore
View file

@ -265,16 +265,16 @@ d "caddn d1, d8, d4, #0xf0" ab042f18 0x000000 (seq (set condition (is_zero (var
d "caddn d15, d14, d4, #-0x59" ab743afe 0x000000 (seq (set condition (is_zero (var d14))) (set result (ite (var condition) (+ (var d4) (bv 32 0xffffffa7)) (var d4))) (set d15 (var result)) (set overflow (|| (! (sle (var result) (bv 32 0x7fffffff))) (&& (sle (var result) (bv 32 0xfb3b4c00)) (! (== (var result) (bv 32 0xfb3b4c00)))))) (branch (var condition) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (ite (var overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (branch (&& (var condition) (var overflow)) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set advanced_overflow (^^ (! (is_zero (& (>> (var result) (bv 32 0x1e) false) (bv 32 0x1)))) (! (is_zero (& (>> (var result) (bv 32 0x1f) false) (bv 32 0x1)))))) (branch (var condition) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (ite (var advanced_overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1c) false))) nop) (branch (&& (var condition) (var advanced_overflow)) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop))
d "caddn d10, d12, d0, #0x26" ab6022ac 0x000000 (seq (set condition (is_zero (var d12))) (set result (ite (var condition) (+ (var d0) (bv 32 0x26)) (var d0))) (set d10 (var result)) (set overflow (|| (! (sle (var result) (bv 32 0x7fffffff))) (&& (sle (var result) (bv 32 0xfb3b4c00)) (! (== (var result) (bv 32 0xfb3b4c00)))))) (branch (var condition) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (ite (var overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (branch (&& (var condition) (var overflow)) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set advanced_overflow (^^ (! (is_zero (& (>> (var result) (bv 32 0x1e) false) (bv 32 0x1)))) (! (is_zero (& (>> (var result) (bv 32 0x1f) false) (bv 32 0x1)))))) (branch (var condition) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (ite (var advanced_overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1c) false))) nop) (branch (&& (var condition) (var advanced_overflow)) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop))
d "caddn d10, d15, #6" ca6a 0x000000 (seq (set condition (is_zero (var d15))) (set result (ite (var condition) (+ (var d10) (bv 32 0x6)) (var d10))) (set d10 (var result)) (set overflow (|| (! (sle (var result) (bv 32 0x7fffffff))) (&& (sle (var result) (bv 32 0xfb3b4c00)) (! (== (var result) (bv 32 0xfb3b4c00)))))) (branch (var condition) (set PSW (| (& (var PSW) (bv 32 0xbfffffff)) (<< (& (ite (var overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1e) false))) nop) (branch (&& (var condition) (var overflow)) (set PSW (| (& (var PSW) (bv 32 0xdfffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1d) false))) nop) (set advanced_overflow (^^ (! (is_zero (& (>> (var result) (bv 32 0x1e) false) (bv 32 0x1)))) (! (is_zero (& (>> (var result) (bv 32 0x1f) false) (bv 32 0x1)))))) (branch (var condition) (set PSW (| (& (var PSW) (bv 32 0xefffffff)) (<< (& (ite (var advanced_overflow) (bv 32 0x1) (bv 32 0x0)) (bv 32 0x1)) (bv 32 0x1c) false))) nop) (branch (&& (var condition) (var advanced_overflow)) (set PSW (| (& (var PSW) (bv 32 0xf7ffffff)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x1b) false))) nop))
d "call #0" 5ccd 0x000000 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x2)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0x0)))))
d "call #0" 5c97 0x000000 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x2)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0x0)))))
d "call #0" 5cc4 0x000000 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x2)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0x0)))))
d "call #0xffca2984" 6d65c214 0x000000 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0xffca2984)))))
d "call #0x6f75c0" 6db7e0ba 0x000000 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0x6f75c0)))))
d "call #0x211d4e" 6d90a78e 0x000000 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0x211d4e)))))
d "call #0" 5c56 0x000000 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x2)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0x0)))))
d "calla #0x3ee66" eda133f7 0x000000 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0x3ee66)))))
d "calla #0x66fee" ed23f737 0x000000 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0x66fee)))))
d "calla #0x1963c6" edece3b1 0x000000 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0x1963c6)))))
d "call #0xffffff9a" 5ccd 0x0 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x2)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0xffffff9a)))))
d "call #0xffffff2e" 5c97 0x0 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x2)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0xffffff2e)))))
d "call #0xffffff88" 5cc4 0x0 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x2)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0xffffff88)))))
d "call #0xca2984" 6d65c214 0x0 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0xca2984)))))
d "call #0xff6f75c0" 6db7e0ba 0x0 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0xff6f75c0)))))
d "call #0xff211d4e" 6d90a78e 0x0 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0xff211d4e)))))
d "call #0xac" 5c56 0x0 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x2)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0xac)))))
d "calla #0xa003ee66" eda133f7 0x0 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0xa003ee66)))))
d "calla #0x20066fee" ed23f737 0x0 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0x20066fee)))))
d "calla #0xe01963c6" edece3b1 0x0 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (bv 32 0xe01963c6)))))
d "calli a7" 2d070000 0x000000 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (var a7)))))
d "calli a5" 2d050000 0x000000 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (var a5)))))
d "calli a8" 2d080000 0x000000 (branch (is_zero (var FCX)) nop (seq (branch (! (is_zero (& (>> (var PSW) (bv 32 0x7) false) (bv 32 0x1)))) (seq (set _psw_cdc (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (branch (== (var _psw_cdc) (bv 32 0x7f)) (seq (set CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f))) (set CDC_COUNT (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3f)) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1f)) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0xf)) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x7)) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x3)) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (& (>> (var CDC) (bv 32 0x0) false) (bv 32 0x1)) (bv 32 0x0))))))))) (set CDC_i (let CDC (& (>> (var PSW) (bv 32 0x0) false) (bv 32 0x7f)) (ite (== (& (>> (var CDC) (bv 32 0x6) false) (bv 32 0x1)) (bv 32 0x0)) (bv 32 0x6) (ite (== (& (>> (var CDC) (bv 32 0x5) false) (bv 32 0x3)) (bv 32 0x2)) (bv 32 0x5) (ite (== (& (>> (var CDC) (bv 32 0x4) false) (bv 32 0x7)) (bv 32 0x6)) (bv 32 0x4) (ite (== (& (>> (var CDC) (bv 32 0x3) false) (bv 32 0xf)) (bv 32 0xe)) (bv 32 0x3) (ite (== (& (>> (var CDC) (bv 32 0x2) false) (bv 32 0x1f)) (bv 32 0x1e)) (bv 32 0x2) (ite (== (& (>> (var CDC) (bv 32 0x1) false) (bv 32 0x3f)) (bv 32 0x3e)) (bv 32 0x1) (bv 32 0x0))))))))) (set PSW (| (& (var PSW) (~ (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false))) (& (<< (+ (var _psw_cdc) (bv 32 0x1)) (bv 32 0x0) false) (<< (>> (bv 32 0xffffffff) (- (bv 32 0x20) (var CDC_i)) false) (bv 32 0x0) false)))) (branch (== (var CDC_COUNT) (- (<< (bv 32 0x1) (var CDC_i) false) (bv 32 0x1))) nop nop)) nop)) nop) (set PSW (| (& (var PSW) (bv 32 0xffffff7f)) (<< (& (bv 32 0x1) (bv 32 0x1)) (bv 32 0x7) false))) (set tmp_FCX (var FCX)) (set EA (| (<< (& (>> (var FCX) (bv 32 0x10) false) (bv 32 0xf)) (bv 32 0x1c) false) (<< (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0x7fff)) (bv 32 0x6) false))) (set new_FCX (loadw 0 32 (var EA))) (storew 0 (var EA) (var d15)) (storew 0 (+ (var EA) (bv 32 0x4)) (var d14)) (storew 0 (+ (var EA) (bv 32 0x8)) (var d13)) (storew 0 (+ (var EA) (bv 32 0xc)) (var d12)) (storew 0 (+ (var EA) (bv 32 0x10)) (var a15)) (storew 0 (+ (var EA) (bv 32 0x14)) (var a14)) (storew 0 (+ (var EA) (bv 32 0x18)) (var a13)) (storew 0 (+ (var EA) (bv 32 0x1c)) (var a12)) (storew 0 (+ (var EA) (bv 32 0x20)) (var d11)) (storew 0 (+ (var EA) (bv 32 0x24)) (var d10)) (storew 0 (+ (var EA) (bv 32 0x28)) (var d9)) (storew 0 (+ (var EA) (bv 32 0x2c)) (var d8)) (storew 0 (+ (var EA) (bv 32 0x30)) (var a11)) (storew 0 (+ (var EA) (bv 32 0x34)) (var a10)) (storew 0 (+ (var EA) (bv 32 0x38)) (var PSW)) (storew 0 (+ (var EA) (bv 32 0x3c)) (var PCXI)) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x0) false) (bv 32 0xff)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (& (>> (var ICR) (bv 32 0x8) false) (bv 32 0x1)) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xc03fffff)) (<< (& (bv 32 0x1) (bv 32 0xff)) (bv 32 0x16) false))) (set PCXI (| (& (var PCXI) (bv 32 0xfff00000)) (<< (& (& (>> (var FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set FCX (| (& (var FCX) (bv 32 0xfff00000)) (<< (& (& (>> (var new_FCX) (bv 32 0x0) false) (bv 32 0xfffff)) (bv 32 0xfffff)) (bv 32 0x0) false))) (set a11 (bv 32 0x4)) (branch (== (var new_FCX) (var LCX)) nop (jmp (var a8)))))
@ -451,12 +451,12 @@ d "extr.u d11, d0, d1, #0x19" 570079b1 0x000000 (set d11 (& (>> (>> (var d0) (&
d "extr.u d5, d10, d0, #0xf" 570a6f50 0x000000 (set d5 (& (>> (>> (var d10) (& (>> (var d0) (bv 32 0x0) false) (bv 32 0x1f)) false) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0xf)) false)))
d "extr.u d7, d6, d4, #6" 57066674 0x000000 (set d7 (& (>> (>> (var d6) (& (>> (var d4) (bv 32 0x0) false) (bv 32 0x1f)) false) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x6)) false)))
d "extr.u d6, d15, #0x18, #0x17" 37bf776c 0x000000 (set d6 (& (>> (>> (var d15) (bv 32 0x18) false) (bv 32 0x0) false) (bv 32 0x7fffff)))
d "fcall #0xffa5b39e" 6152cfd9 0x000000 (seq (set EA (- (var a10) (bv 32 0x4))) (storew 0 (var EA) (var a11)) (set a11 (bv 32 0x4)) (set a10 (var EA)) (jmp (bv 32 0xffa5b39e)))
d "fcall #0xa5b39e" 6152cfd9 0x0 (seq (set EA (- (var a10) (bv 32 0x4))) (storew 0 (var EA) (var a11)) (set a11 (bv 32 0x4)) (set a10 (var EA)) (jmp (bv 32 0xa5b39e)))
d "fcall #0x484984" 6124c224 0x000000 (seq (set EA (- (var a10) (bv 32 0x4))) (storew 0 (var EA) (var a11)) (set a11 (bv 32 0x4)) (set a10 (var EA)) (jmp (bv 32 0x484984)))
d "fcall #0xff9d43ba" 614edda1 0x000000 (seq (set EA (- (var a10) (bv 32 0x4))) (storew 0 (var EA) (var a11)) (set a11 (bv 32 0x4)) (set a10 (var EA)) (jmp (bv 32 0xff9d43ba)))
d "fcall #0x9d43ba" 614edda1 0x0 (seq (set EA (- (var a10) (bv 32 0x4))) (storew 0 (var EA) (var a11)) (set a11 (bv 32 0x4)) (set a10 (var EA)) (jmp (bv 32 0x9d43ba)))
d "fcalla #0x1b1386" e10dc389 0x000000 (seq (set EA (- (var a10) (bv 32 0x4))) (storew 0 (var EA) (var a11)) (set a11 (bv 32 0x4)) (set a10 (var EA)) (jmp (bv 32 0x1b1386)))
d "fcalla #0xb8ff0" e145f8c7 0x000000 (seq (set EA (- (var a10) (bv 32 0x4))) (storew 0 (var EA) (var a11)) (set a11 (bv 32 0x4)) (set a10 (var EA)) (jmp (bv 32 0xb8ff0)))
d "fcalla #0x293e0" e1b1f049 0x000000 (seq (set EA (- (var a10) (bv 32 0x4))) (storew 0 (var EA) (var a11)) (set a11 (bv 32 0x4)) (set a10 (var EA)) (jmp (bv 32 0x293e0)))
d "fcalla #0x400b8ff0" e145f8c7 0x0 (seq (set EA (- (var a10) (bv 32 0x4))) (storew 0 (var EA) (var a11)) (set a11 (bv 32 0x4)) (set a10 (var EA)) (jmp (bv 32 0x400b8ff0)))
d "fcalla #0xb00293e0" e1b1f049 0x0 (seq (set EA (- (var a10) (bv 32 0x4))) (storew 0 (var EA) (var a11)) (set a11 (bv 32 0x4)) (set a10 (var EA)) (jmp (bv 32 0xb00293e0)))
d "fcalli a3" 2d031000 0x000000 (seq (set EA (- (var a10) (bv 32 0x4))) (storew 0 (var EA) (var a11)) (set a11 (bv 32 0x4)) (set a10 (var EA)) (jmp (var a3)))
d "fcalli a11" 2d0b1000 0x000000 (seq (set EA (- (var a10) (bv 32 0x4))) (storew 0 (var EA) (var a11)) (set a11 (bv 32 0x4)) (set a10 (var EA)) (jmp (var a11)))
d "fcalli a9" 2d091000 0x000000 (seq (set EA (- (var a10) (bv 32 0x4))) (storew 0 (var EA) (var a11)) (set a11 (bv 32 0x4)) (set a10 (var EA)) (jmp (var a9)))
@ -563,9 +563,9 @@ d "j #0xff9ae1aa" 1dcdd570 0x000000 (jmp (bv 32 0xff9ae1aa))
d "j #0xff8a2c4c" 1dc52616 0x000000 (jmp (bv 32 0xff8a2c4c))
d "j #0xb2" 3c59 0x000000 (jmp (bv 32 0xb2))
d "j #0x86" 3c43 0x000000 (jmp (bv 32 0x86))
d "ja #0x1c06e2" 9dce7103 0x000000 (jmp (bv 32 0x180dc4))
d "ja #0xc099c" 9d56ce04 0x000000 (jmp (bv 32 0x181338))
d "ja #0x168402" 9dcb0142 0x000000 (jmp (bv 32 0xd0804))
d "ja #0xc01c06e2" 9dce7103 0x0 (jmp (bv 32 0x180dc4))
d "ja #0x500c099c" 9d56ce04 0x0 (jmp (bv 32 0x181338))
d "ja #0xc0168402" 9dcb0142 0x0 (jmp (bv 32 0xd0804))
d "jeq d15, d11, #0x38" bebc 0x000000 (branch (== (var d15) (var d11)) (jmp (bv 32 0x38)) nop)
d "jeq d15, d12, #0x32" bec9 0x000000 (branch (== (var d15) (var d12)) (jmp (bv 32 0x32)) nop)
d "jeq d15, d0, #0x38" be0c 0x000000 (branch (== (var d15) (var d0)) (jmp (bv 32 0x38)) nop)
@ -628,9 +628,9 @@ d "ji a11" 2d0b3000 0x000000 (jmp (& (var a11) (bv 32 0xfffffffe)))
d "jl #0xff5172aa" 5da855b9 0x000000 (seq (set a11 (bv 32 0x4)) (jmp (bv 32 0xff5172aa)))
d "jl #0xaac39c" 5d55ce61 0x000000 (seq (set a11 (bv 32 0x4)) (jmp (bv 32 0xaac39c)))
d "jl #0xd88610" 5d6c0843 0x000000 (seq (set a11 (bv 32 0x4)) (jmp (bv 32 0xd88610)))
d "jla #0xd0a9a" ddd64d85 0x000000 (seq (set a11 (bv 32 0x4)) (jmp (bv 32 0x1a1534)))
d "jla #0xf287c" dd973e94 0x000000 (seq (set a11 (bv 32 0x4)) (jmp (bv 32 0x1e50f8)))
d "jla #0x14a656" dd8a2b53 0x000000 (seq (set a11 (bv 32 0x4)) (jmp (bv 32 0x94cac)))
d "jla #0xd00d0a9a" ddd64d85 0x0 (seq (set a11 (bv 32 0x4)) (jmp (bv 32 0x1a1534)))
d "jla #0x900f287c" dd973e94 0x0 (seq (set a11 (bv 32 0x4)) (jmp (bv 32 0x1e50f8)))
d "jla #0x8014a656" dd8a2b53 0x0 (seq (set a11 (bv 32 0x4)) (jmp (bv 32 0x94cac)))
d "jlez d11, #2" 8eb1 0x000000 (branch (sle (var d11) (bv 32 0x0)) (jmp (bv 32 0x2)) nop)
d "jlez d13, #0x1a" 8edd 0x000000 (branch (sle (var d13) (bv 32 0x0)) (jmp (bv 32 0x1a)) nop)
d "jlez d10, #2" 8ea1 0x000000 (branch (sle (var d10) (bv 32 0x0)) (jmp (bv 32 0x2)) nop)
@ -903,14 +903,14 @@ d "lea a13, [a1]#-0xa8" 491d18da 0x000000 (seq (set EA (+ (var a1) (bv 32 0xffff
d "loop a0, #0xfffffffc" fc0e 0x000000 (seq (set PC (ite (! (is_zero (var a0))) (bv 32 0xfffffffc) (bv 32 0x2))) (set a0 (- (var a0) (bv 32 0x1))) (jmp (var PC)))
d "loop a7, #0xffffffe8" fc74 0x000000 (seq (set PC (ite (! (is_zero (var a7))) (bv 32 0xffffffe8) (bv 32 0x2))) (set a7 (- (var a7) (bv 32 0x1))) (jmp (var PC)))
d "loop a5, #0xfffffff8" fc5c 0x000000 (seq (set PC (ite (! (is_zero (var a5))) (bv 32 0xfffffff8) (bv 32 0x2))) (set a5 (- (var a5) (bv 32 0x1))) (jmp (var PC)))
d "loop a0, #0xfffff0ea" fd007538 0x000000 (seq (set PC (ite (! (is_zero (var a0))) (bv 32 0xfffff0ea) (bv 32 0x4))) (set a0 (- (var a0) (bv 32 0x1))) (jmp (var PC)))
d "loop a5, #0xffffd610" fd50082b 0x000000 (seq (set PC (ite (! (is_zero (var a5))) (bv 32 0xffffd610) (bv 32 0x4))) (set a5 (- (var a5) (bv 32 0x1))) (jmp (var PC)))
d "loop a12, #0x11c4" fdc0e248 0x000000 (seq (set PC (ite (! (is_zero (var a12))) (bv 32 0x11c4) (bv 32 0x4))) (set a12 (- (var a12) (bv 32 0x1))) (jmp (var PC)))
d "loop a0, #0x70ea" fd007538 0x0 (seq (set PC (ite (! (is_zero (var a0))) (bv 32 0x70ea) (bv 32 0x4))) (set a0 (- (var a0) (bv 32 0x1))) (jmp (var PC)))
d "loop a5, #0x5610" fd50082b 0x0 (seq (set PC (ite (! (is_zero (var a5))) (bv 32 0x5610) (bv 32 0x4))) (set a5 (- (var a5) (bv 32 0x1))) (jmp (var PC)))
d "loop a12, #0xffff91c4" fdc0e248 0x0 (seq (set PC (ite (! (is_zero (var a12))) (bv 32 0xffff91c4) (bv 32 0x4))) (set a12 (- (var a12) (bv 32 0x1))) (jmp (var PC)))
d "loop a4, #0xfffffff8" fc4c 0x000000 (seq (set PC (ite (! (is_zero (var a4))) (bv 32 0xfffffff8) (bv 32 0x2))) (set a4 (- (var a4) (bv 32 0x1))) (jmp (var PC)))
d "loop a4, #0xffffffe6" fc43 0x000000 (seq (set PC (ite (! (is_zero (var a4))) (bv 32 0xffffffe6) (bv 32 0x2))) (set a4 (- (var a4) (bv 32 0x1))) (jmp (var PC)))
d "loopu #0xffffcbe8" fd00f4e5 0x000000 (jmp (bv 32 0xffffcbe8))
d "loopu #0xf0a" fd0085c7 0x000000 (jmp (bv 32 0xf0a))
d "loopu #0xfffff714" fd008abb 0x000000 (jmp (bv 32 0xfffff714))
d "loopu #0xffff8f0a" fd0085c7 0x0 (jmp (bv 32 0xffff8f0a))
d "loopu #0x7714" fd008abb 0x0 (jmp (bv 32 0x7714))
d "lt d15, d12, d11" 7abc 0x000000 (set d15 (ite (&& (sle (var d12) (var d11)) (! (== (var d12) (var d11)))) (bv 32 0x1) (bv 32 0x0)))
d "lt d15, d1, d1" 7a11 0x000000 (set d15 (ite (&& (sle (var d1) (var d1)) (! (== (var d1) (var d1)))) (bv 32 0x1) (bv 32 0x0)))
d "lt d15, d7, d7" 7a77 0x000000 (set d15 (ite (&& (sle (var d7) (var d7)) (! (== (var d7) (var d7)))) (bv 32 0x1) (bv 32 0x0)))

1
test/db/cmd/cmd_pd
View file

@ -2709,6 +2709,7 @@ EXPECT=<<EOF
| 0x00000804 return
\ 0x00000808
EOF
BROKEN=1
RUN
NAME=Check output pdr and pdrj to be the same

1
test/db/cmd/cmd_pde
View file

@ -89,6 +89,7 @@ EXPECT=<<EOF
0x00080518 addiu gp, gp, -0x753c
0x0008051c addu gp, gp, t9
EOF
BROKEN=1
RUN
NAME=pde ppc

15
test/db/esil/mips_32
View file

@ -1222,6 +1222,7 @@ RUN
NAME=bnez s4, 0xc (taken)
FILE=malloc://0x200
BROKEN=1
CMDS=<<EOF
e asm.arch=mips
e asm.bits=32
@ -1238,6 +1239,7 @@ RUN
NAME=blez v0, 0x3c (not taken)
FILE=malloc://0x200
BROKEN=1
CMDS=<<EOF
e asm.arch=mips
e asm.bits=32
@ -1254,6 +1256,7 @@ RUN
NAME=blez v0, 0x3c (taken)
FILE=malloc://0x200
BROKEN=1
CMDS=<<EOF
e asm.arch=mips
e asm.bits=32
@ -1443,6 +1446,7 @@ RUN
NAME=jalr t9
FILE=malloc://0x200
BROKEN=1
CMDS=<<EOF
e asm.arch=mips
e asm.bits=32
@ -1461,6 +1465,7 @@ RUN
NAME=jalr t4, t9
FILE=malloc://0x200
BROKEN=1
CMDS=<<EOF
e asm.arch=mips
e asm.bits=32
@ -1479,6 +1484,7 @@ RUN
NAME=jalr t4, t9 (invalid delay instruction)
FILE=malloc://8
BROKEN=1
CMDS=<<EOF
e asm.arch=mips
e asm.bits=32
@ -1497,6 +1503,7 @@ RUN
NAME=slt s0, v0, v1 (1<2=1)
FILE=malloc://0x200
BROKEN=1
CMDS=<<EOF
e asm.arch=mips
e asm.bits=32
@ -1514,6 +1521,7 @@ RUN
NAME=slt s0, v0, v1 (0<0=0)
FILE=malloc://0x200
BROKEN=1
CMDS=<<EOF
e asm.arch=mips
e asm.bits=32
@ -1599,6 +1607,7 @@ RUN
NAME=negu v1, v0 (neg -1 = 1)
FILE=malloc://0x200
BROKEN=1
CMDS=<<EOF
e asm.arch=mips
e asm.bits=32
@ -1616,6 +1625,7 @@ RUN
NAME=negu v1, v0 (neg 1 = -1)
FILE=malloc://0x200
BROKEN=1
CMDS=<<EOF
e asm.arch=mips
e asm.bits=32
@ -1633,6 +1643,7 @@ RUN
NAME=negu v1, v0 (neg 3497 = -3497)
FILE=malloc://0x200
BROKEN=1
CMDS=<<EOF
e asm.arch=mips
e asm.bits=32
@ -1650,6 +1661,7 @@ RUN
NAME=negative mem reference
FILE=malloc://0x200
BROKEN=1
ARGS=-m 0x410984
CMDS=<<EOF
e io.va=true
@ -1673,6 +1685,7 @@ t9 = 0x11223344
EOF
RUN
BROKEN=1
NAME=complex function
FILE=malloc://0x800
ARGS=-m 0x0040092c
@ -1698,6 +1711,7 @@ SLOWDOWNWOMAN
EOF
RUN
BROKEN=1
NAME=complex function 2
FILE=malloc://0x800
ARGS=-m 0x0040092c
@ -1724,6 +1738,7 @@ EOF
RUN
NAME=complex function 3
BROKEN=1
FILE=malloc://0x800
ARGS=-m 0x00400ac0
CMDS=<<EOF

9
test/db/formats/elf/m68k
View file

@ -1,6 +1,15 @@
NAME=ELF: m68k.elf
BROKEN=1
FILE=bins/elf/analysis/busybox.m68k
CMDS=<<EOF
# This test is broken. The reason is that Rizin can't distinguish
# CPU models. Each M68k model has a different address mask (32-24 bits).
# It defaults to one which has only 24bits.
# Hence, the subi.l instruction decodes to
# `subi.l 0x15b119, d0` instead of `subi.l 0x8015b119, d0`
# Should be fixable with RzArch (if anyone is still intereses).
# See: https://github.com/rizinorg/rizin/issues/4334
# And https://github.com/rizinorg/rizin/issues/4681
f sym.init @ 0x80001a30
f sym.fini @ 0x800019b0
f sub.exit @ 0x80001450

3
test/db/formats/elf/mips
View file

@ -34,10 +34,12 @@ sw v0, 0x14(sp)
jal sym.imp.__uClibc_main
sw sp, 0x18(sp)
EOF
BROKEN=1
RUN
NAME=ELF: mipsbe-busybox
FILE=bins/elf/analysis/mipsbe-busybox
BROKEN=1
CMDS=<<EOF
af
e asm.sub.var=false
@ -64,3 +66,4 @@ jal sym.imp.__uClibc_main
sw sp, 0x18(sp)
EOF
RUN
BROKEN=1