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Fix tricore RzIL ADDSC.A (#4112)

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billow 2024-01-16 07:07:39 +08:00 committed by GitHub
parent 09692c01d3
commit fc6e9019f2
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2 changed files with 9 additions and 2 deletions
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8
librz/analysis/arch/tricore/tricore_il.c
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@ -3617,9 +3617,13 @@ RZ_IPI RzAnalysisLiftedILOp tricore_il_op(RzAsmTriCoreContext *ctx, RzAnalysis *
case /*MOV.D SRR*/ 0x80: return SETG(R(0), VARG(R(1)));
case /*ADD.A SRC*/ 0xb0: return SETG(R(0), ADD(VARG(R(0)), U32(I(1))));
case /*ADD.A SRR*/ 0x30: return SETG(R(0), ADD(VARG(R(0)), VARG(R(1))));
case /*ADDSC.A SRRS*/ 0x10: return SETG(R(0), ADD(VARG(R(1)), SHL0(VARG("d15"), I(2))));
case /*SUB.A SC*/ 0x20: return SETG("a10", SUB(VARG("a10"), U32(I(0))));
default: break;
default:
if (extract32(ctx->word, 0, 6) == 0x10) {
/*ADDSC.A SRRS*/
return SETG(R(0), ADD(VARG(R(1)), SHL0(VARG("d15"), I(2))));
}
break;
}
rz_warn_if_reached();
return NULL;

3
test/db/asm/tricore
View file

@ -110,6 +110,9 @@ d "ge.a d0, a0, a0" 01003004 0x0 (set d0 (ite (|| (! (ule (var a0) (var a0))) (=
d "eq.a d0, a0, a0" 01000004 0x0 (set d0 (ite (== (var a0) (var a0)) (bv 32 0x1) (bv 32 0x0)))
d "eqz.a d0, a0" 01008004 0x0 (set d0 (ite (== (var a0) (bv 32 0x0)) (bv 32 0x1) (bv 32 0x0)))
d "addsc.a a0, a0, d15, #0" 1000 0x0 (set a0 (+ (var a0) (<< (var d15) (bv 32 0x0) false)))
d "addsc.a a0, a0, d15, #1" 5000 0x0 (set a0 (+ (var a0) (<< (var d15) (bv 32 0x1) false)))
d "addsc.a a0, a0, d15, #2" 9000 0x0 (set a0 (+ (var a0) (<< (var d15) (bv 32 0x2) false)))
d "addsc.a a0, a0, d15, #3" d000 0x0 (set a0 (+ (var a0) (<< (var d15) (bv 32 0x3) false)))
d "addsc.a a0, a0, d0, #0" 01000006 0x0 (set a0 (+ (var a0) (<< (var d0) (bv 32 0x0) false)))
d "addsc.at a0, a0, d0" 01002006 0x0 (set a0 (& (+ (var a0) (>> (var d0) (bv 32 0x3) false)) (bv 32 0xfffffffc)))
d "add.a a0, a0" 3000 0x0 (set a0 (+ (var a0) (var a0)))