* Add support for: v5-v68+HVX, System instructions/register; Change plugin design to monolithic; Basic ELF-reloc patching.
- Update instruction set to v5-v67 + HVX.
- Introduce monolithic plugin architecture to reverse opcodes in the same functions.
- Analysis and Asm functionality was previously seperated and let to inconsistensies and incorrectly reversed opcodes.
- Add missing system instructions and registers.
- Enable search for immediates.
- Mark packets of instructions.
- Set more analysis data in RzAnalysisOp.
- Add basic ELF-reloc patching.
- Fix several disassembly and analysis bugs.
- Jumps were not aligned to packet begin.
- Endloop packets were not marked as such.
- Rs.New registers were incorrectly disassembled.
- Calling convention was out of date.
- Add several formatting configs for the produced disassembly.
- Dis/Enable UTF-8.
- Print or omit # prefix of immediates.
- Print signed immediates as signed or unsigned integers.
