* Support ARM ELF THM_PC22 / THM_JUMP24 relocs
This revision adds proper support for the following ARM ELF relocations:
- RZ_ARM_THM_PC22
- RZ_ARM_THM_JUMP24
These require a rather special encoding as some bits of the relative
offset are encoded in a non-common fashion.
* Refactor sdb_foreach and related APIs
* Strengthen bounds check in sdb_dump_next()
* Switch to RzPVector
* Use length info in filter_noreturn()
* Fix cmp function
* Remove unused sdb_like() API
* Pass SdbKv to SdbForeachCallback
* Add sdbkv_dup_value() helper
* Fix memory leaks in debug path
* Fix memory leaks in mach and mdmp format
* Update the fix for mach
* Add support for aarch64 tcache parsing
* Test case fix
* Comment update
---------
Co-authored-by: Giridhar Prasath R <giridh1337@gmail.com>
- All `ht_*_new0()` are removed
- `freefn` field of HT options was renamed to `finiKV`
- `finiKV_user` fields was added to HT options
- Added `ht_*_new_opt_size` API
- `HtSP` and `HtUP` are created with `ValueFree` callback that allows to reduce extra LOC and prevent bugs
- `SetP` replaced with `SetS` (based on `HtSP`)
- `rz_th_ht_*_new0()` and `rz_th_ht_*_new_opt()` are replaced with `rz_th_ht_*_new(HtXX *)`
* Use local variables in methods using `EXEC_WITH_RMODE` instead of
`DUP`ing the values. Do the same for ST register stack popping.
This leads to lesser code in the IL since the same long expression
does not get repeated in the IL everytime (since we don't `DUP`
anymore).
The only place where this field was set to a non-zero value was the now
removed fb command, and it was never used for anything sensible. Thus it
is safe to remove.
The fb command can modify the offset of a flag, but does not update the
skiplist they are stored in, leading to a corrupted flag database. This
can be seen for example when executing
f test @ 0x4; fb 0x10 test; fl; pd 0x8 @ 0
* Increase timeout for OpenBSD
* Reset all members of a packet.
* Replace calloc with Rizin macros
* Add returns after fatal logs
* Init time structs with 0.
* Use monotonic clock to set last access timestamps.
Because instruction packets get pushed out of the buffer based in their last access,
using the real-time clock leads to problems. On Windows the real time clock seems to
not always give ascending values with multiple calls
(real-time clock = best bet of machine of current day time, which can fluctuate).
Using the monotonic clock will always give strictly ascending timestamps.
Due to the use of the real-clock, the instruction packets got
sometimes pushed out of the buffer non-deterministically.
Uplift Hexagon architecture to RzIL
The general structure is, that every (sub-)instruction has a getter for it's RzIL code.
Calling the getter will return the RzIL operation.
If RzIL for an instruction is requested, the plugin makes a decision. Because Hexagon only executes whole instruction packets. If the instruction is not the last instruction in a packet, it will simply return `EMPTY()`. If the RzIL for the last instruction in a packet is requested, it will get the RzIL operations for all instructions in the packet, shuffles them into the correct execution order (according to some rules) and returns the complete operation for the packet.
The RzIL code was entirely generated with the [rzil-compiler](https://github.com/Rot127/rzil-compiler/), using the semantic definition of the [QEMU Hexagon module](https://github.com/qemu/qemu/tree/master/target/hexagon).
Currently successful compile instructions (and tested):
```
[*] 1581/1733 standard instructions compiled.
[*] 431/643 HVX instructions compiled.
[*] In total: 2012/2376 instructions compiled.
```
It was tested with:
- (Semantic tests) `rz-tracetest` against the execution trace of the QEMU Hexagon test binaries.
- (Bug free and semi-semtantic test) Adding tests which simply execute the test binaries to ensure leak and segfault free execution. Also it is executed until a certain instruction is reached (end of `main` or `loc.pass` symbol), partially testing it executes correctly.
For the uplifting several changes and modernization had to be made:
- Enhance consistency of decoding
- Allow to disassemble an instruction without copying the result. This is used if the given buffer of instruction bytes is larger than one instruction width. In this case, as many instructions as the buffer can hold are disassembled and buffered for later.
- Generally enhance buffering of instructions.
- Allow to mark a packet as valid before it is completely decoded (in case we know it must be valid, e.g. if it is a jump target of a valid packet).
- Fix (hopefully) all memory leaks of the Hexagon plugin.
- Changes to register getters, because RzIL needs finer control to translate alias or explicit register names to their real register.
- Getter for register name is now done by table, so for future distinction between DSP version we can just select another table.
- Translation functions from register alias or explicit name to their real register.
- Each operand contains now it's variable ID (e.g. `d` for register `Rd`) as in the ISA (for mapping in the RzIL code).
- Ease debugging by tracking in more precision, if an instruction is added to a stale, active or new packet.
- Add registers `C20` - `C29` (not yet present in LLVM)
- Some renaming to make the code more readable.
- Add tcache heap heuristics
- Fetch glibc version from libc
- Add unit testcases for glibc version
Co-authored-by: Giridhar Prasath R <giridh1337@gmail.com>
