* Refactor sdb_foreach and related APIs
* Strengthen bounds check in sdb_dump_next()
* Switch to RzPVector
* Use length info in filter_noreturn()
* Fix cmp function
* Remove unused sdb_like() API
* Pass SdbKv to SdbForeachCallback
* Add sdbkv_dup_value() helper
- All `ht_*_new0()` are removed
- `freefn` field of HT options was renamed to `finiKV`
- `finiKV_user` fields was added to HT options
- Added `ht_*_new_opt_size` API
- `HtSP` and `HtUP` are created with `ValueFree` callback that allows to reduce extra LOC and prevent bugs
- `SetP` replaced with `SetS` (based on `HtSP`)
- `rz_th_ht_*_new0()` and `rz_th_ht_*_new_opt()` are replaced with `rz_th_ht_*_new(HtXX *)`
The only place where this field was set to a non-zero value was the now
removed fb command, and it was never used for anything sensible. Thus it
is safe to remove.
Uplift Hexagon architecture to RzIL
The general structure is, that every (sub-)instruction has a getter for it's RzIL code.
Calling the getter will return the RzIL operation.
If RzIL for an instruction is requested, the plugin makes a decision. Because Hexagon only executes whole instruction packets. If the instruction is not the last instruction in a packet, it will simply return `EMPTY()`. If the RzIL for the last instruction in a packet is requested, it will get the RzIL operations for all instructions in the packet, shuffles them into the correct execution order (according to some rules) and returns the complete operation for the packet.
The RzIL code was entirely generated with the [rzil-compiler](https://github.com/Rot127/rzil-compiler/), using the semantic definition of the [QEMU Hexagon module](https://github.com/qemu/qemu/tree/master/target/hexagon).
Currently successful compile instructions (and tested):
```
[*] 1581/1733 standard instructions compiled.
[*] 431/643 HVX instructions compiled.
[*] In total: 2012/2376 instructions compiled.
```
It was tested with:
- (Semantic tests) `rz-tracetest` against the execution trace of the QEMU Hexagon test binaries.
- (Bug free and semi-semtantic test) Adding tests which simply execute the test binaries to ensure leak and segfault free execution. Also it is executed until a certain instruction is reached (end of `main` or `loc.pass` symbol), partially testing it executes correctly.
For the uplifting several changes and modernization had to be made:
- Enhance consistency of decoding
- Allow to disassemble an instruction without copying the result. This is used if the given buffer of instruction bytes is larger than one instruction width. In this case, as many instructions as the buffer can hold are disassembled and buffered for later.
- Generally enhance buffering of instructions.
- Allow to mark a packet as valid before it is completely decoded (in case we know it must be valid, e.g. if it is a jump target of a valid packet).
- Fix (hopefully) all memory leaks of the Hexagon plugin.
- Changes to register getters, because RzIL needs finer control to translate alias or explicit register names to their real register.
- Getter for register name is now done by table, so for future distinction between DSP version we can just select another table.
- Translation functions from register alias or explicit name to their real register.
- Each operand contains now it's variable ID (e.g. `d` for register `Rd`) as in the ISA (for mapping in the RzIL code).
- Ease debugging by tracking in more precision, if an instruction is added to a stale, active or new packet.
- Add registers `C20` - `C29` (not yet present in LLVM)
- Some renaming to make the code more readable.
Unlike rz_vector_index_ptr, which is very important, there do not seem
to be any valid usages of rz_pvector_index_ptr in rizin, cutter or
rz-ghidra that could not be replaced by rz_pvector_at.
In case there will be a use-case for it in the future, it can also be
done by rz_pvector_data(...) + i.
OpenBSD/sparc64 uses 128-bit floats as long double by default while our
tests seeminly assumed either 64-bit or 80-bit, both of which produce
different results than 128 here. Since 80-bit is x86-specific, we check
only the bits we know will be identical between other architectures.
* Added a test in `test_float.c` for it
* It is kind of unfortunate to deal with the idiosyncrasy of 80-bit
float this way. There are cleaner ways, but they would require
more refactor, and are probably not worth it since we wouldn't be
modifying the float code that often.
* Read bytes at curr_op->fail/jump into buffer before decoding them.
* Add meta information of iCFG and CFG nodes to dot graph labels.
* Add subtype annotations to CFG and iCFG nodes.
* Test reading of buffer before node to RzAnalysisOp.jump/fail is added.
* Fix CFG tests by adding node type annotations.
* Add iCFG graph with 'alloc' annotations.
* Wrap ascii annotation symbols in brackets.
* Add doxygen to rz_str_append(f)
* Add different types of GraphNodeInfos.
This adds support for multiple graph node infos.
It removes the assumption that information of
a graph node must be some strings and an offset.
* Increase buffer for printing graph node body
* Don't hardcode maximum label size
* Add graph node info for icfg
* Add node type info to CFG.
* Access address members properly for iCFG and CFG nodes
* Update test. Function names are no longer saved.
* Fix reachable double free of label
* Split graph node type from its sub-type to make it less confusing.
* Add integration tests for iCFG nodes.
* Fix, add mising buffer read
* Recognize more calls
* Add test for iCFG generation and its node details.
* Replace OpenBSD regex library with PCRE2.
PCRE2 has way better performance than the OpenBSD
library (something around 20 times faster).
The following flags are enabled for every pattern:
- PCRE2_UTF
- PCRE2_MATCH_INVALID_UTF
- PCRE2_NO_UTF_CHECK
All the others are optional.
Changes made:
- Adds PCRE2 as subproject.
- Changes the API away from POSIX to PCRE2.
- Edits many regex patterns because:
- ' ' is skipped in patterns, if the EXTENDED flag is set for matching. '\s' must be set now.
- '.' doesn't match newlines by default.
- Changes the API so matches and their groups are bundled into PVectors.
- Moves the regex component to rz_util.
* Fix cross build - add copy of PCRE2 dependecy
Meson currently doesn't support subprojects to be native and non-native at the same time.
See: https://github.com/mesonbuild/meson/issues/10947
Unfortunately, sdb depends on rz_util which in turn depends on PCRE2.
Excluding PCRE2 from the native build makes linking of rz_util not possible anymore.
Adding it, will make Meson complain that the dependencies cannot be mixed.
Hence, we compile a copy of PCRE2 for the native build if required.
* Add extra bitvector operations defined in core theory basic extra part
* Add extra bitvector operations test
* Fix bv64 init const overflow in windows x64 test
* Add test case for bv_pred and bv_succ near 0
* Add a new helper to convert a `long double` to an 80-bit RzIL float
* New function: `rz_il_op_new_float_from_f80`
* New opbuilder: `F80`
* Add test for `rz_il_op_new_float_from_f80`
* Also add a float format check in `rz_il_sort_pure_eq`
* Add a few `includes` so that some types are visible
