Commit graph

18 commits

Author SHA1 Message Date
Heersin
48007b4ae0
Adding missing operation in bitvector lib and core theory (#4078)
* Add extra bitvector operations defined in core theory basic extra part

* Add extra bitvector operations test

* Fix bv64 init const overflow in windows x64 test

* Add test case for bv_pred and bv_succ near 0
2024-01-08 23:10:14 +08:00
Heersin
a9c59ce1dd
Add rz_bv_range_set and rz_bv_is_all_one to bitvector lib (#2891) 2022-08-10 08:20:16 +08:00
Rot127
b65ef05e96
Fix: Allow to setup big endian bitvectors with less than 8bit values. (#2571) 2022-04-29 16:03:42 +02:00
Heersin
2fdb8ac07e
Fix copied bit count in rz_copy_nbits and add unit test (#2547) 2022-04-18 18:47:08 +02:00
Florian Märkl
0549b2b5fb
Fix trailing bits in rz_bv_set_to_bytes_le() (#2348)
Any traling bits in the last byte that is to be written should be left
alone.
2022-02-21 23:05:50 +01:00
Florian Märkl
c9d299155c
Fix UB in rz_bv_set_all(..., 64) (#2345)
Shifting a 64-bit value by 64 bits is UB. Restructuring it like this is
fine because the bv len must never be 0.
2022-02-21 13:31:18 +00:00
Florian Märkl
76cec13591
Fix rz_bv_len_bytes() (#2334) 2022-02-18 18:11:33 +01:00
Florian Märkl
bdd9b20afe Fix rz_bv_div() and rz_bv_mod()
Problems fixed:
* Division by repeated addition is horribly slow, now it's classic
  shift+sub
* a / a = 1, not a
* rz_bv_set_all() was setting too many bits if len % 8 != 0
* Removed print on div by 0 because we define it to all 1s (like BAP)

mod just uses div and we use regular ut64 division when possible.
2022-02-13 17:57:17 +01:00
Florian Märkl
05f47d2397 Add ctz and clz ops to RzBitVector
These are typical "count trailing/leading zeroes" to be used in
division for example.
2022-02-13 17:57:17 +01:00
Florian Märkl
e2751e5c49 Make big bvs store in typical little endian
Previously, bits were stored in the big endian in reversed order, such
that bit 0 of byte 0 would contain the msb. This requires reversing them
for any calculation and becomes even more confusing when the size is not
a multiple of 8, so let's just store them in classic little endian with
bit 0 of byte 0 containing the lsb.
This also fixes rz_bv_as_hex_string() for bvs that have a size not
divisiable by 0.
2022-02-13 17:57:17 +01:00
Florian Märkl
9401c9d67e Fix rz_bv_as_hex_string() for big 0
This was printing `0x` instead of `0x0` for big vectors when padding was
disabled.
2022-02-13 17:57:17 +01:00
Florian Märkl
76e776907e
[RzIL] Add remaining comparison aliases and tests (#2295) 2022-02-08 17:29:35 +01:00
Florian Märkl
325ab7c2bb Extend bitvector and reg unit tests
Some additional tests for bitvector access of single-bit registers.
2022-02-05 21:50:48 +01:00
Florian Märkl
efa41b86d7 [RzIL] Refine events and add tests
* Removed nullability where not needed
* Made events take RzILVal instead of force-converting to RzILBitVector
  for variables
* Added more fine-grained tests for events from specific ops
2022-01-22 18:40:10 +01:00
Florian Märkl
c8a6359d83
Change IL string syntax to s-expressions (#2193)
Before:
	store(key:var(v:ptr), value:add(x:load(key:var(v:ptr), mem:0),
	    y:int(value:1, length:8)), mem:0)
After:
	(store 0 (var ptr) (+ (load 0 (var ptr)) (bv 8 0x1)))

S-Expressions like this are more concise and will be trivial to parse,
in case we want a parser for this later. It is also very similar to what
BAP uses, so it will be easier to compare.
2022-01-11 10:08:41 +01:00
Giovanni
5963da2bba
[RzIL] Add loadw/storew and bind memories against RzBuffer (#2105)
* [RzIL] Load/Store via RzIO and RzBuffer
* [RzIL] LoadW/StorWe via RzIO and RzBuffer
Co-authored-by: Florian Märkl <info@florianmaerkl.de>
2021-12-24 16:53:20 +01:00
Florian Märkl
4cb13c3183
Add rz_bv_set_from_bytes_le() (#2068)
Also make rz_bv_as_hex_string() always pad with the same number of 0s if
len % 4 != 0.
2021-12-06 12:28:26 +08:00
Dhruv Maroo
648c267bc7
Rename and refactor to use RzBitVector instead of RzILBitVector (#2048) 2021-12-01 14:28:04 +05:30