Commit graph

61 commits

Author SHA1 Message Date
Riccardo Schirone
9ba89d8116 core/cmd: rewrite rz_cmd_macro API 2022-08-26 07:53:43 +08:00
pluswave
68f6f71fd2
ARM esil32: ldr reg, [pc, reg] correct (#2826)
* ARM esil32: ldr reg, [pc, reg] correct
* Fix test for db/esil/apple
2022-07-22 09:23:40 +08:00
Anton Kochkov
c42dd5d4bb
Convert as commands to the rzshell (#2323) 2022-05-03 18:06:18 +08:00
Giovanni
d344d29a57
Moved rz_analysis_esil_dumpstack to rz_core_esil_dumpstack (#2460) 2022-03-28 19:55:46 +08:00
Giovanni
7b06001ed9
Remove cb_printf() from RzAnalysis (#2454)
* Moved `rz_analysis_var_list_show()` under rz_core as static function
* Removed `cb_printf()` from RzAnalysis and refactoring zignatures
* Removed newline from matches
* Use `stdout` for ESIL traps
* Converted commands to use RzCmdStateOutput
2022-03-28 08:22:19 +08:00
Giovanni
db580beb22
Refactoring for rz_print_2bpp_* and ps<cmd> (#2376)
* Moved rz_print_2bpp_* under rz_core
* Moved rz_print_string to rz_str_stringify_raw_buffer
* Added test for print urlencode and added pu0
* Removed RzCoreString and implemented utf32be/utf16be
2022-03-04 15:30:46 +01:00
Riccardo Schirone
dea0918afd
Convert wa commands to rzshell (#2293) 2022-02-09 18:49:11 +08:00
wargio
3cb17236e2 Wrong esil test 2022-02-06 12:08:16 +01:00
wargio
1b98f63b6c Fixed tests 2022-02-06 12:08:16 +01:00
Anton Kochkov
91b414708c Remove unused esil.debug config variable 2022-02-01 17:25:03 +08:00
Florian Märkl
96a85e573e Remove ESIL Pins (#2096)
ESIL Pins were an untested feature to run a command when emulation hit a
specific address. This can be solved in other ways, e.g. scripting.
Project version 7 has been introduced for this change.
2021-12-12 18:27:34 +01:00
Florian Märkl
3c2e4bf63a
Rewrite ar and dr with newshell (#2006)
* Show group-level details of commands

Details can be defined at either a group command or its subcommand of
the same name. If define on group-level it will also be shown in the
group help without needing ??.

* Fix > $ redirection for errored command and leak

* Rewrite ar and dr commands with newshell

Breaking changes:
ar* => arf, ar- => arf-, ar. => ar*
ar, => art, ar? => arq
ar0 => ara0, arb => arab, ars => araS
arC => arpC
arn => arR
art => arT
arf => arF
Removed: drm, aer
2021-12-06 19:02:43 +01:00
Florian Märkl
289536cc04
Unscramble Register Printing and Flags Logic (#1920)
* Added rz_analysis_get_address_bits() instead of arch-specific hacks in core
* flags are only set for address-sized registers
* dr/ar show registers of any size by default, but hiding registers that are entirely
  covered by others
2021-11-17 11:44:14 +01:00
Florian Märkl
fd8d84b475
Remove rX_rY Hacks in AVR ESIL (#1988) 2021-11-16 23:07:05 +01:00
Florian Märkl
86e4df8655
Remove r1_r0 Hack from AVR (#1985) 2021-11-16 02:52:10 +01:00
Florian Märkl
081ebe728f
Rewrite and fix AVR DES ESIL (#1975) 2021-11-14 15:43:03 +01:00
Khairul Azhar Kasmiran
58fd79be91
Fix first line of db/esil/x86_64 (#1958) 2021-11-10 23:03:26 +08:00
Riccardo Schirone
589ab9299c Fix tests after more rigid wx 2021-11-09 12:01:41 +01:00
Giovanni
4ca140a97b
[RzIL] implemented ao statement output (#1901)
* RzIL implemented il string and json representation
* Added json representation
* Fixed some memleaks on rz_il_free_op
* Implemented rz_il_op_stringify and rz_il_op_json
* RzIL Fixed memory leaks
2021-10-30 11:41:30 +08:00
Riccardo Schirone
1be3d02a36 Fix all db/esil tests 2021-10-27 09:31:50 +02:00
Heersin
e0d3d6bc66
New RZIL integration (#1663)
The new intermediate language is based on the BAP (Binary Analysis Platform) Core Theory.
It operates on SMT-like bitvectors and their arrays to represent values and memory.
Apart from that, it has also representation for the data and code side effects.
2021-10-09 18:14:44 +08:00
Azox
7cd9562832 Fix emulation for AARCH64 ldr,str,stp,ldp instructions ##esil
* Modified tests for LDP (preindex, no writeback)

Signed-off-by: Riccardo Schirone <sirmy15@gmail.com>
2021-08-19 12:50:06 +02:00
Simon Vareille
f167cae98e Fix emulation for ARM's ldrd ##esil
* Add arm32 tests for ldrd esil expressions
* Translate ldrd instructions into esil
* Handle pre and post indexed ldrd
* Add arm16 ldrd esil tests ##emu ##test
* Use ISPREINDEX64 and ISPOSTINDEX64 macros in ARM64 instructions

Signed-off-by: Riccardo Schirone <sirmy15@gmail.com>
2021-08-18 09:16:23 +02:00
Anton Kochkov
2c691b91e3
Disable unnecessary io.cache in tests (#1190) 2021-06-04 15:06:02 +02:00
seanachao
a2f8631b6c
Change -, --, = argument and = command meaning (#930)
* Swap = & - R (#615)&(#616)
* Fix R replace =
2021-04-21 16:20:24 +08:00
Florian Märkl
617bf0d49e
Make Tests use x86.as only on x86 Host (#618) 2021-02-18 11:14:12 +01:00
Liumeo
ff76c71984 Use pj in core ##refactor (#18267)
* Use pj in core ##refactor

* fix tests
2021-01-22 18:01:58 +08:00
Riccardo Schirone
144ba639dc
Convert s commands to newshell (#375)
* Rename `sj`/`s*` and move them under `sH`. Remove `s=`
* Rename `s-*` to `sH-`
* Use `sd` for "seek delta", which moves relative to the current offset
* Enforce <cmd> <arg> syntax. So no more `s+16` but `s +16`. Command
  `sHr` is for redo history, `sHu` for undo history. If one wants to move
  relative to the current address, they need to do `sd +10`/`sd -10`.
* Remove `ss` commands in favour of `cmd.seek.silent`. This was anyway
  used mainly for scripts, so no need to replicate all `s` commands
  under `ss`.

Change a bit rz_core_seek API to avoid dupped entries in seek history.
2021-01-20 10:30:20 +08:00
eagleoflqj
d5bba030c8 Support arm32 esil stmib/ldmib ##esil 2021-01-11 17:54:24 +08:00
Anton Kochkov
ad6a580a1c Fix tests 2021-01-05 23:33:32 -06:00
Itay Cohen
4ac005d489
Set asm.tabs to 6 and enable asm.tabs.once by default ##config (#290)
* Set asm.tabs to 6
* Enabl asm.tabs.once by default
2021-01-04 17:45:35 +02:00
Liumeo
e57329f736 Fix pseudo and esil of the TST instruction on ARM32 #18108 (#18110) 2020-12-30 23:20:41 -06:00
Sylvain Pelissier
c3eaed924f Update RISC-V ESIL with sign extention operator (#18109) ##esil 2020-12-30 23:20:41 -06:00
Sylvain Pelissier
981d54c7d4 Add sign extension assignment operator (#18092) ##esil 2020-12-25 18:58:25 +08:00
Sylvain Pelissier
3078579e72 Fix ESIL for RISC-V 64-bit load instruction (#18072) 2020-12-22 08:26:41 +08:00
Sylvain Pelissier
7f7067609a Fix RISC-V 64-bit for shift instructions and update register analysis (#18070) ##esil 2020-12-22 08:26:41 +08:00
Aswin C
d42cde8ca5
Disable asm.bytes by default ##cons (#155)
* Disable `asm.bytes` by default

* Fix tests by adding `e asm.bytes=true` (1/n)

* Fix tests by adding  (2/n)

* Fix tests by adding `e asm.bytes=true` (3/n)

* Fix tests by adding `asm.bytes=true` (4/n)

* Fix test by adding `asm.bytes=true` (5/n)

* Fix mostly all broken tests

* Attemp to fix the rzpipe test

* Attempt to fix the tests in `db/cmd/cmd_pipe`

* Fix tests again

* Fix cmd_pipe test

* Add a test where `asm.bytes` is false

Co-authored-by: Anton Kochkov <anton.kochkov@gmail.com>
2020-12-15 12:47:33 +01:00
Rene Laemmert
c7c19b41ec Add ESIL for x86 CMC instruction ##esil (#18032) 2020-12-14 11:23:54 +01:00
Florian Märkl
d53d1e3845
Final Analysis Renaming (#124)
* Rename missing Analysis Defines
* Rename analysis config vars and other lower case stuff
* Rename test/db/analysis
* Fix analysis tests

Co-authored-by: Anton Kochkov <anton.kochkov@gmail.com>
2020-12-08 15:05:24 +08:00
Liumeo
b1efb5bb9d Fix travis ppc64le db/esil/arm_16 (#17920) 2020-11-20 13:38:32 +08:00
Anton Kochkov
539f60a1a8
Rename radare to rizin (#68)
* Rename radare to rizin

- Rename REvent to RzEvent
- Rename RBreakpoint to RzBreakpoint
- Rename RRune to RzRune

* Remove unnecessary files
2020-11-04 18:56:27 +08:00
pancake
7eb70dbc7e Fix unexpected FPU exception in ESIL emulation ##esil (#17815)
* Fix unexpected FPU exception in ESIL emulation ##esil
* More fixes and add test
* Add comment

Co-authored-by: pancake <pancake@nopcode.org>
2020-10-30 10:44:38 +01:00
Fabian Freyer
588a244f7b Fix incorrect esil of RISC-V jalr insn ##emu (#17788)
* The emitted esil for jalr was incorrect in the case where `rd` and
  `rs1` are equal, since then `rs1` is written to as `rd` before adding
  the immediate.

  For example, `jalr ra ra 0x42` was lifted to the following esil:

      4,$$,+,ra,=,ra,66,+,pc,=

  While this does correctly set rd to the return address after the call,
  pc is not correctly set according to `pc <- ra + 0x42`, but instead
  `pc <- pc + 4 + 66`.

  This commit flips the order of setting `pc` and `rd`, so that `rd` is
  read from before it is written to.
2020-10-19 13:35:10 +08:00
pancake
18af675e05
Show ESIL execution cost information in ao and aoj ##anal (#17585) 2020-09-14 10:44:19 +02:00
Anisse Astier
50eac99601
Add minimal armv7 and aarch32 VFP and NEON support ##esil (#17462) 2020-09-14 09:57:05 +02:00
pancake
226517b516
Implement ?== operator to compare strings ##shell (#17612) 2020-09-09 15:51:11 +02:00
junchao-loongson
e51bf7a980
Improve mips.cs esil (fix mips32, update mthi) ##anal (#17595) 2020-09-08 11:59:57 +02:00
junchao-loongson
9c17df8df3
Fix ESIL sign extension operator bug ##esil (#17578) 2020-09-07 12:30:13 +02:00
VVS
992404ade9
Fix ESIL movi.n immediate value parsing ##emu (#17557)
Co-authored-by: BlackVS <vvs@coders.in.ua>
2020-09-03 11:33:23 +08:00
aemmitt-ns
ec173d40d6
ESIL signedness and other extensions ##esil (#17436)
* fix typo in anal_arm esil (does not affect esil execution)
* add af flag setting and sof op for sub overflow, change borrow
* remove the break that was 'breaking' everything, fix warning
* add new sign extension operator and use it to handle signedness in imul
* work on expressions for idiv, div, imul, mul, remove  and just modify sub/cmp
* add clz and reorder the sign extension arguments to be in line with all other ops
* add support for many arm64 instructions
* add sign extension to all ldr*s instructions
* make numerous changes to fix REV*, SXT*, LSL, LSR, ASR, SDIV, MOVN and others, to be detailed in PR
* add sxt* to shifted_register_append, use it to fix opcall and ldr / str
* remove unnecessary commented code
* add some comments
* add clz and reorder the sign extension arguments to be in line with all other ops
* add sign extension to all ldr*s instructions
* make numerous changes to fix REV*, SXT*, LSL, LSR, ASR, SDIV, MOVN and others, to be detailed in PR
* add sxt* to shifted_register_append, use it to fix opcall and ldr / str
* fix wrong type check in esil_signext
* change borrow flag back to the way it was
* add example comment to esil_signext
* unbreak movk
* format mask in sub, cmp, and movk as hex
* add test for esil signext operator
* use ULL instead of (ut64) cast in shifts
2020-09-02 00:03:24 +02:00