Commit graph

4 commits

Author SHA1 Message Date
Rot127
c009f8d7a3
Tokenize and colorize asm strings (#2417)
This introduces the ability to split asm strings into tokens and assign a type to them.

This means:
* Each asm strings is assigned a list of tokens. Each token points to a sub-string.
* A token has a type attached which describes it (e.g. register token, operator token, mnemonic token etc.)
* A generic parsing method is introduced which splits an asm string into tokens. The pattern it parses is `<mnem> <op> <op> ...`.
* Instead of the generic method, plugins can create the token strings on their own.
* An API method was introduced to help plugins implement their own parsing methods via regex patterns.
* Custom token strings are stored in `RzAsmOp.asm_toks`

Additionally the coloring of asm strings is now exclusively done via the token strings.
* For this a function was added to colorize tokenized asm strings according to their token types.
2022-07-27 08:52:01 -04:00
billow
40ca22202b
Refactor rz_core_print_disasm_json (#2746)
* Split `rz_core_print_disasm_json` as: `rz_core_print_disasm_json` and `rz_core_disasm`
* Use `rz_str_enc_string_as_type` in `ds_init`
* Refactor `rz_core_print_disasm` and `rz_core_handle_backwards_disasm`
* Add `rz_core_asm_bb_middle`
* Move global `disasm_texts` to `RzDisasmState`
* Rewrite `core_analysis_bytes_standard` with `rz_core_analysis_bytes`
* Add `test_rz_core_print_disasm` and `test_rz_core_analysis_bytes`
* Rewrite `rz_core_print_disasm` with `RzCmdStateOutput`
* `pdi` -> `pdq` in tests
* `pdi` -> `pDq` in tests
* `pid` -> `pdq` in tests
* `pId` -> `pDq` in tests
* `pij` -> `pdj` in tests
* `pIj` -> `pDj` in tests
* `pdeqq` -> `pdeQ` in tests
* Remove `pDJ` from `test/db/json/`
2022-07-09 08:10:06 +08:00
Giovanni
bda1e9cfca
Disable GPL code and Add RISC-V support via Capstone 5 (#2087)
* -Duse_gpl=false is supported by rizin and added riscv_cs for capstone v5
* Added GPL build workflow in CI
2021-12-11 13:30:01 +01:00
GustavoLCR
b84158fd3e
Fixes for value analysis (#1520)
* Fill `op->reg` for ARM64 `br`/`blr` analysis
* This fixes software single-stepping on `br`/`blr` instructions on ARM64
* Fill `op->reg` for ARM `bx`/`blx` analysis
* This fixes software single-stepping on `bx`/`blx` instructions on ARM
* Set `bx` as `RZ_ANALYSIS_OP_TYPE_RJMP`
* Fill `RzAnalysisValue->type`
* Use only `RzAnalysisValue` in `rz_core_link_stroff()`
* Fill `op->ireg/disp/scale` for ARM `ldr` analysis
* This fixes software single-stepping for `ldr pc` on ARM
* Fix riscv inverted src/dst values for store instructions
* Fix riscv analysis with buffer of size 2
* Add unit tests for `RzAnalysisOp` and `RzAnalysisValue`

Co-authored-by: Giovanni <561184+wargio@users.noreply.github.com>
2021-08-27 22:07:39 +08:00