Name Nr Rel Offset Size Type r0 0 0 0 4 uint32_t r1 1 1 4 4 uint32_t r2 2 2 8 4 uint32_t r3 3 3 12 4 uint32_t r4 4 4 16 4 uint32_t r5 5 5 20 4 uint32_t r6 6 6 24 4 uint32_t r7 7 7 28 4 uint32_t r8 8 8 32 4 uint32_t r9 9 9 36 4 uint32_t r10 10 10 40 4 uint32_t r11 11 11 44 4 uint32_t r12 12 12 48 4 uint32_t sp 13 13 52 4 *1 lr 14 14 56 4 long pc 15 15 60 4 *1 '' 16 16 64 0 int0_t '' 17 17 64 0 int0_t '' 18 18 64 0 int0_t '' 19 19 64 0 int0_t '' 20 20 64 0 int0_t '' 21 21 64 0 int0_t '' 22 22 64 0 int0_t '' 23 23 64 0 int0_t '' 24 24 64 0 int0_t cpsr 25 25 64 4 long '' 26 26 68 0 int0_t '' 27 27 68 0 int0_t '' 28 28 68 0 int0_t '' 29 29 68 0 int0_t '' 30 30 68 0 int0_t '' 31 31 68 0 int0_t '' 32 32 68 0 int0_t '' 33 33 68 0 int0_t '' 34 34 68 0 int0_t '' 35 35 68 0 int0_t '' 36 36 68 0 int0_t '' 37 37 68 0 int0_t '' 38 38 68 0 int0_t '' 39 39 68 0 int0_t '' 40 40 68 0 int0_t '' 41 41 68 0 int0_t '' 42 42 68 0 int0_t '' 43 43 68 0 int0_t '' 44 44 68 0 int0_t '' 45 45 68 0 int0_t '' 46 46 68 0 int0_t '' 47 47 68 0 int0_t '' 48 48 68 0 int0_t '' 49 49 68 0 int0_t '' 50 50 68 0 int0_t '' 51 51 68 0 int0_t '' 52 52 68 0 int0_t '' 53 53 68 0 int0_t '' 54 54 68 0 int0_t '' 55 55 68 0 int0_t '' 56 56 68 0 int0_t '' 57 57 68 0 int0_t d0 58 58 68 8 neon_d d1 59 59 76 8 neon_d d2 60 60 84 8 neon_d d3 61 61 92 8 neon_d d4 62 62 100 8 neon_d d5 63 63 108 8 neon_d d6 64 64 116 8 neon_d d7 65 65 124 8 neon_d d8 66 66 132 8 neon_d d9 67 67 140 8 neon_d d10 68 68 148 8 neon_d d11 69 69 156 8 neon_d d12 70 70 164 8 neon_d d13 71 71 172 8 neon_d d14 72 72 180 8 neon_d d15 73 73 188 8 neon_d d16 74 74 196 8 neon_d d17 75 75 204 8 neon_d d18 76 76 212 8 neon_d d19 77 77 220 8 neon_d d20 78 78 228 8 neon_d d21 79 79 236 8 neon_d d22 80 80 244 8 neon_d d23 81 81 252 8 neon_d d24 82 82 260 8 neon_d d25 83 83 268 8 neon_d d26 84 84 276 8 neon_d d27 85 85 284 8 neon_d d28 86 86 292 8 neon_d d29 87 87 300 8 neon_d d30 88 88 308 8 neon_d d31 89 89 316 8 neon_d fpscr 90 90 324 4 long s0 91 0 328 4 float s1 92 1 332 4 float s2 93 2 336 4 float s3 94 3 340 4 float s4 95 4 344 4 float s5 96 5 348 4 float s6 97 6 352 4 float s7 98 7 356 4 float s8 99 8 360 4 float s9 100 9 364 4 float s10 101 10 368 4 float s11 102 11 372 4 float s12 103 12 376 4 float s13 104 13 380 4 float s14 105 14 384 4 float s15 106 15 388 4 float s16 107 16 392 4 float s17 108 17 396 4 float s18 109 18 400 4 float s19 110 19 404 4 float s20 111 20 408 4 float s21 112 21 412 4 float s22 113 22 416 4 float s23 114 23 420 4 float s24 115 24 424 4 float s25 116 25 428 4 float s26 117 26 432 4 float s27 118 27 436 4 float s28 119 28 440 4 float s29 120 29 444 4 float s30 121 30 448 4 float s31 122 31 452 4 float q0 123 32 456 16 neon_q q1 124 33 472 16 neon_q q2 125 34 488 16 neon_q q3 126 35 504 16 neon_q q4 127 36 520 16 neon_q q5 128 37 536 16 neon_q q6 129 38 552 16 neon_q q7 130 39 568 16 neon_q q8 131 40 584 16 neon_q q9 132 41 600 16 neon_q q10 133 42 616 16 neon_q q11 134 43 632 16 neon_q q12 135 44 648 16 neon_q q13 136 45 664 16 neon_q q14 137 46 680 16 neon_q q15 138 47 696 16 neon_q *1: Register type's name NULL.