ab201a3843
Squash of rizinorg/rizin PR #6434 ("improve TMS320C55x+ analysis and RzIL") rebased onto dev, with the PR head's doubled c55plus_il.c (every symbol defined twice, failing to compile) de-duplicated to a single clean copy. Substantially extends the C55x/C55x+ RzIL lifter over the existing structured- operand helpers: mov/copy (immediate, register, memory load/store, half-register read-modify-write), the full addressing-mode set with post-modify side effects, control and system-register moves, 40-bit accumulator ALU with shifted sources, 16-bit and dual-memory add/sub, the ST0_55 status-flag model (cmp/cmpand/rol/ror, named-bit bset/bclr), a documented psh/pop stack model, address-unit amov/aadd/ asub and amar, and bcc/callcc control transfer. The multiply/MAC family and satr are lifted with explicit, documented integer-mode approximations (not verified DSP semantics); irreducibly multi-output primitives (bit counts, Viterbi, FIR, distance) are left correct-or-NULL. The register file covers ac0-7 and xar, found by validating on real Motorola Wrigley C55x+ firmware whose prologues save 40-bit accumulators as dbl(acN)+acN.g pairs. Adds RzIL-VM emulation tests (including the C55x and C55x+ _decrypt emulateme binaries), per-instruction IL assertions, and ~95% instruction-class disassembly coverage per corpus; pins little-endian in the VM tests for big-endian hosts; and regenerates the analysis expectations against current dev.
111 lines
4 KiB
Text
111 lines
4 KiB
Text
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NAME=arp TMS320 c55x
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FILE==
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CMDS=<<EOF
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e asm.arch=tms320
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e analysis.arch=tms320
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e analysis.cpu=c55x
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arp
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ar
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EOF
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EXPECT=<<EOF
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=PC pc
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=A0 ar0
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=A1 ar1
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=A2 ar2
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=A3 ar3
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=A4 ar4
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=R0 ar0
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ctr ac0 .40 496 0 # Accumulator 0
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ctr ac1 .40 501 0 # Accumulator 1
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ctr ac2 .40 506 0 # Accumulator 2
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ctr ac3 .40 511 0 # Accumulator 3
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gpr ar0 .16 516 0 # Auxiliary registers 0
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gpr ar1 .16 518 0 # Auxiliary registers 1
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gpr ar2 .16 520 0 # Auxiliary registers 2
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gpr ar3 .16 522 0 # Auxiliary registers 3
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gpr ar4 .16 524 0 # Auxiliary registers 4
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gpr ar5 .16 526 0 # Auxiliary registers 5
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gpr ar6 .16 528 0 # Auxiliary registers 6
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gpr ar7 .16 530 0 # Auxiliary registers 7
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gpr xar0 .23 532 0 # Extended auxiliary registers 0
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gpr xar1 .23 535 0 # Extended auxiliary registers 1
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gpr xar2 .23 538 0 # Extended auxiliary registers 2
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gpr xar3 .23 541 0 # Extended auxiliary registers 3
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gpr xar4 .23 544 0 # Extended auxiliary registers 4
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gpr xar5 .23 547 0 # Extended auxiliary registers 5
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gpr xar6 .23 550 0 # Extended auxiliary registers 6
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gpr xar7 .23 553 0 # Extended auxiliary registers 7
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ctr bk03 .16 556 0 # Circular buffer size registers
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ctr bk47 .16 558 0 # Circular buffer size registers
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ctr bkc .16 560 0 # Circular buffer size registers
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ctr brc0 .16 562 0 # Block-repeat counters 0
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ctr brc1 .16 564 0 # Block-repeat counters 1
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ctr brs1 .16 566 0 # BRC1 save register
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ctr bsa01 .16 568 0 # Circular buffer start address registers
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ctr bsa23 .16 570 0 # Circular buffer start address registers
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ctr bsa45 .16 572 0 # Circular buffer start address registers
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ctr bsa67 .16 574 0 # Circular buffer start address registers
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ctr bsac .16 576 0 # Circular buffer start address registers
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ctr cdp .16 578 0 # Coefficient data pointer (low part of XCDP)
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ctr cdph .7 580 0 # High part of XCDP
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ctr cfct .8 581 0 # Control-flow context register
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ctr csr .16 582 0 # Computed single-repeat register
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ctr dbier0 .16 584 0 # Debug interrupt enable registers 0
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ctr dbier1 .16 586 0 # Debug interrupt enable registers 1
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ctr dp .16 588 0 # Data page register (low part of XDP)
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ctr dph .7 590 0 # High part of XDP
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ctr ier0 .16 591 0 # Interrupt enable registers 0
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ctr ier1 .16 593 0 # Interrupt enable registers 1
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ctr ifr0 .16 595 0 # Interrupt flag registers 0
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ctr ifr1 .16 597 0 # Interrupt flag registers 1
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ctr ivpd .16 599 0 # Interrupt vector pointers
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ctr ivph .16 601 0 # Interrupt vector pointers
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ctr pc .24 603 0 # Program counter
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ctr pdp .9 606 0 # Peripheral data page register
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ctr rea0 .24 608 0 # Block-repeat end address registers 0
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ctr rea1 .24 611 0 # Block-repeat end address registers 1
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ctr reta .24 614 0 # Return address register
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ctr rptc .16 617 0 # Single-repeat counter
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ctr rsa0 .24 619 0 # Block-repeat start address registers 0
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ctr rsa1 .24 622 0 # Block-repeat start address registers 1
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ctr sp .16 625 0 # Data stack pointer (low part of XSP)
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ctr sph .7 627 0 # High part of XSP and XSSP
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ctr ssp .16 628 0 # System stack pointer (low part of XSSP)
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ctr st0_55 .16 630 0 # Status registers 0
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ctr st1_55 .16 632 0 # Status registers 1
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ctr st2_55 .16 634 0 # Status registers 2
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ctr st3_55 .16 636 0 # Status registers 3
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ctr t0 .16 638 0 # Temporary register 0
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ctr t1 .16 640 0 # Temporary register 1
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ctr t2 .16 642 0 # Temporary register 2
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ctr t3 .16 644 0 # Temporary register 3
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ctr trn0 .16 646 0 # Transition registers 1
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ctr trn1 .16 648 0 # Transition registers 1
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ctr xcdp .23 650 0 # Extended coefficient data pointer
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ctr xdp .23 653 0 # Extended data page register
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ctr xsp .23 656 0 # Extended data stack pointer
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ctr xssp .23 659 0 # Extended system stack pointer
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ctr ac4 .40 664 0 # Accumulator 4
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ctr ac5 .40 669 0 # Accumulator 5
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ctr ac6 .40 674 0 # Accumulator 6
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ctr ac7 .40 679 0 # Accumulator 7
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ar0 = 0x0000
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ar1 = 0x0000
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ar2 = 0x0000
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ar3 = 0x0000
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ar4 = 0x0000
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ar5 = 0x0000
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ar6 = 0x0000
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ar7 = 0x0000
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xar0 = 0x000000
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xar1 = 0x000000
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xar2 = 0x000000
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xar3 = 0x000000
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xar4 = 0x000000
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xar5 = 0x000000
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xar6 = 0x000000
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xar7 = 0x000000
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EOF
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RUN
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