141 lines
6 KiB
Text
141 lines
6 KiB
Text
Name Nr Rel Offset Size Type
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r0 0 0 0 4 uint32_t
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r1 1 1 4 4 uint32_t
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r2 2 2 8 4 uint32_t
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r3 3 3 12 4 uint32_t
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r4 4 4 16 4 uint32_t
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r5 5 5 20 4 uint32_t
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r6 6 6 24 4 uint32_t
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r7 7 7 28 4 uint32_t
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r8 8 8 32 4 uint32_t
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r9 9 9 36 4 uint32_t
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r10 10 10 40 4 uint32_t
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r11 11 11 44 4 uint32_t
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r12 12 12 48 4 uint32_t
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sp 13 13 52 4 *1
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lr 14 14 56 4 long
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pc 15 15 60 4 *1
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'' 16 16 64 0 int0_t
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'' 17 17 64 0 int0_t
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'' 18 18 64 0 int0_t
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'' 19 19 64 0 int0_t
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'' 20 20 64 0 int0_t
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'' 21 21 64 0 int0_t
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'' 22 22 64 0 int0_t
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'' 23 23 64 0 int0_t
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'' 24 24 64 0 int0_t
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cpsr 25 25 64 4 long
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'' 26 26 68 0 int0_t
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'' 27 27 68 0 int0_t
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'' 28 28 68 0 int0_t
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'' 29 29 68 0 int0_t
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'' 30 30 68 0 int0_t
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'' 31 31 68 0 int0_t
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'' 32 32 68 0 int0_t
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'' 33 33 68 0 int0_t
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'' 34 34 68 0 int0_t
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'' 35 35 68 0 int0_t
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'' 36 36 68 0 int0_t
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'' 37 37 68 0 int0_t
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'' 38 38 68 0 int0_t
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'' 39 39 68 0 int0_t
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'' 40 40 68 0 int0_t
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'' 41 41 68 0 int0_t
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'' 42 42 68 0 int0_t
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'' 43 43 68 0 int0_t
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'' 44 44 68 0 int0_t
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'' 45 45 68 0 int0_t
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'' 46 46 68 0 int0_t
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'' 47 47 68 0 int0_t
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'' 48 48 68 0 int0_t
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'' 49 49 68 0 int0_t
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'' 50 50 68 0 int0_t
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'' 51 51 68 0 int0_t
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'' 52 52 68 0 int0_t
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'' 53 53 68 0 int0_t
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'' 54 54 68 0 int0_t
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'' 55 55 68 0 int0_t
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'' 56 56 68 0 int0_t
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'' 57 57 68 0 int0_t
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d0 58 58 68 8 neon_d
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d1 59 59 76 8 neon_d
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d2 60 60 84 8 neon_d
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d3 61 61 92 8 neon_d
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d4 62 62 100 8 neon_d
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d5 63 63 108 8 neon_d
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d6 64 64 116 8 neon_d
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d7 65 65 124 8 neon_d
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d8 66 66 132 8 neon_d
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d9 67 67 140 8 neon_d
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d10 68 68 148 8 neon_d
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d11 69 69 156 8 neon_d
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d12 70 70 164 8 neon_d
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d13 71 71 172 8 neon_d
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d14 72 72 180 8 neon_d
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d15 73 73 188 8 neon_d
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d16 74 74 196 8 neon_d
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d17 75 75 204 8 neon_d
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d18 76 76 212 8 neon_d
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d19 77 77 220 8 neon_d
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d20 78 78 228 8 neon_d
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d21 79 79 236 8 neon_d
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d22 80 80 244 8 neon_d
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d23 81 81 252 8 neon_d
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d24 82 82 260 8 neon_d
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d25 83 83 268 8 neon_d
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d26 84 84 276 8 neon_d
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d27 85 85 284 8 neon_d
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d28 86 86 292 8 neon_d
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d29 87 87 300 8 neon_d
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d30 88 88 308 8 neon_d
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d31 89 89 316 8 neon_d
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fpscr 90 90 324 4 long
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s0 91 0 328 4 float
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s1 92 1 332 4 float
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s2 93 2 336 4 float
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s3 94 3 340 4 float
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s4 95 4 344 4 float
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s5 96 5 348 4 float
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s6 97 6 352 4 float
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s7 98 7 356 4 float
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s8 99 8 360 4 float
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s9 100 9 364 4 float
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s10 101 10 368 4 float
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s11 102 11 372 4 float
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s12 103 12 376 4 float
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s13 104 13 380 4 float
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s14 105 14 384 4 float
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s15 106 15 388 4 float
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s16 107 16 392 4 float
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s17 108 17 396 4 float
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s18 109 18 400 4 float
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s19 110 19 404 4 float
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s20 111 20 408 4 float
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s21 112 21 412 4 float
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s22 113 22 416 4 float
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s23 114 23 420 4 float
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s24 115 24 424 4 float
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s25 116 25 428 4 float
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s26 117 26 432 4 float
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s27 118 27 436 4 float
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s28 119 28 440 4 float
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s29 120 29 444 4 float
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s30 121 30 448 4 float
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s31 122 31 452 4 float
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q0 123 32 456 16 neon_q
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q1 124 33 472 16 neon_q
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q2 125 34 488 16 neon_q
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q3 126 35 504 16 neon_q
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q4 127 36 520 16 neon_q
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q5 128 37 536 16 neon_q
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q6 129 38 552 16 neon_q
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q7 130 39 568 16 neon_q
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q8 131 40 584 16 neon_q
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q9 132 41 600 16 neon_q
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q10 133 42 616 16 neon_q
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q11 134 43 632 16 neon_q
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q12 135 44 648 16 neon_q
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q13 136 45 664 16 neon_q
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q14 137 46 680 16 neon_q
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q15 138 47 696 16 neon_q
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*1: Register type's name NULL.
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