dd38e70964
* Add copyright and license to all librz/include/*.h files in dep5
* SPDX headers for most include files except bin/arch/debug
* Add SPDX headers in asm/arch/{8051,arm}
* Add SPDX header for shlr/gdb include files
* Add SPDX header for shlr/bochs include files
* Add SPDX header for librz/reg
* Add SPDX header for librz/debug/p/native/xnu
* Add SPDX header for librz/debug/p/native/windows
* Add SPDX header for librz/debug/p/native/reg include files
* Add SPDX header for librz/debug/p/native/maps include files
* Add SPDX header for librz/debug/p/native/linux include files
225 lines
5.4 KiB
C
225 lines
5.4 KiB
C
// SPDX-FileCopyrightText: 2015 pancake <pancake@nopcode.org>
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// SPDX-License-Identifier: LGPL-3.0-only
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// 64bit host debugging 64bit target
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return strdup(
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"=PC rip\n"
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"=SP rsp\n"
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"=BP rbp\n"
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"=R0 rax\n"
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"=A0 rdi\n"
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"=A1 rsi\n"
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"=A2 rdx\n"
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"=A3 rcx\n"
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"=A4 r8\n"
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"=A5 r9\n"
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"=SN orax\n"
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"# no profile defined for x86-64\n"
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"gpr rax .64 80 0\n"
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"gpr eax .32 80 0\n"
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"gpr ax .16 80 0\n"
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"gpr ah .8 81 0\n"
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"gpr al .8 80 0\n"
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"gpr rbx .64 40 0\n"
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"gpr ebx .32 40 0\n"
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"gpr bx .16 40 0\n"
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"gpr bh .8 41 0\n"
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"gpr bl .8 40 0\n"
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"gpr rcx .64 88 0\n"
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"gpr ecx .32 88 0\n"
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"gpr cx .16 88 0\n"
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"gpr ch .8 89 0\n"
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"gpr cl .8 88 0\n"
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"gpr rdx .64 96 0\n"
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"gpr edx .32 96 0\n"
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"gpr dx .16 96 0\n"
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"gpr dh .8 97 0\n"
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"gpr dl .8 96 0\n"
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"gpr r8 .64 72 0\n"
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"gpr r8d .32 72 0\n"
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"gpr r8w .16 72 0\n"
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"gpr r8b .8 72 0\n"
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"gpr r9 .64 64 0\n"
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"gpr r9d .32 64 0\n"
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"gpr r9w .16 64 0\n"
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"gpr r9b .8 64 0\n"
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"gpr r10 .64 56 0\n"
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"gpr r10d .32 56 0\n"
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"gpr r10w .16 56 0\n"
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"gpr r10b .8 56 0\n"
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"gpr r11 .64 48 0\n"
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"gpr r11d .32 48 0\n"
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"gpr r11w .16 48 0\n"
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"gpr r11b .8 48 0\n"
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"gpr r12 .64 24 0\n"
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"gpr r12d .32 24 0\n"
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"gpr r12w .16 24 0\n"
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"gpr r12b .8 24 0\n"
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"gpr r13 .64 16 0\n"
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"gpr r13d .32 16 0\n"
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"gpr r13w .16 16 0\n"
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"gpr r13b .8 16 0\n"
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"gpr r14 .64 8 0\n"
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"gpr r14d .32 8 0\n"
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"gpr r14w .16 8 0\n"
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"gpr r14b .8 8 0\n"
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"gpr r15 .64 0 0\n"
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"gpr r15d .32 0 0\n"
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"gpr r15w .16 0 0\n"
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"gpr r15b .8 0 0\n"
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"gpr rsi .64 104 0\n"
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"gpr esi .32 104 0\n"
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"gpr si .16 104 0\n"
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"gpr sil .8 104 0\n"
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"gpr rdi .64 112 0\n"
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"gpr edi .32 112 0\n"
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"gpr di .16 112 0\n"
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"gpr dil .8 112 0\n"
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"gpr rsp .64 152 0\n"
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"gpr esp .32 152 0\n"
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"gpr sp .16 152 0\n"
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"gpr spl .8 152 0\n"
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"gpr rbp .64 32 0\n"
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"gpr ebp .32 32 0\n"
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"gpr bp .16 32 0\n"
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"gpr bpl .8 32 0\n"
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"gpr rip .64 128 0\n"
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"seg@gpr cs .64 136 0\n"
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"flg rflags .64 144 0 c1p.a.zstido.n.rv\n"
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"flg eflags .32 144 0 c1p.a.zstido.n.rv\n"
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"flg cf .1 .1152 0 carry\n"
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"flg pf .1 .1154 0 parity\n"
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"flg af .1 .1156 0 adjust\n"
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"flg zf .1 .1158 0 zero\n"
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"flg sf .1 .1159 0 sign\n"
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"flg tf .1 .1160 0 trap\n"
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"flg if .1 .1161 0 interrupt\n"
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"flg df .1 .1162 0 direction\n"
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"flg of .1 .1163 0 overflow\n"
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"gpr orax .64 120 0\n"
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"seg@gpr ss .64 160 0\n"
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"seg@gpr fs .64 168 0\n"
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"seg@gpr gs .64 176 0\n"
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"seg@gpr ds .64 184 0\n"
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"seg@gpr es .64 192 0\n"
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"seg@gpr fs_base .64 200 0\n"
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"seg@gpr gs_base .64 208 0\n"
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"drx dr0 .64 0 0\n"
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"drx dr1 .64 8 0\n"
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"drx dr2 .64 16 0\n"
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"drx dr3 .64 24 0\n"
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// dr4 32
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// dr5 40
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"drx dr6 .64 48 0\n"
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"drx dr7 .64 56 0\n"
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/*0030 struct user_fpregs_struct
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0031 {
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0032 __uint16_t cwd;
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0033 __uint16_t swd;
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0034 __uint16_t ftw;
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0035 __uint16_t fop;
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0036 __uint64_t rip;
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0037 __uint64_t rdp;
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0038 __uint32_t mxcsr;
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0039 __uint32_t mxcr_mask;
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0040 __uint32_t st_space[32]; // 8*16 bytes for each FP-reg = 128 bytes
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0041 __uint32_t xmm_space[64]; // 16*16 bytes for each XMM-reg = 256 bytes
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0042 __uint32_t padding[24];
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0043 };
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*/
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"fpu cwd .16 0 0\n"
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"fpu swd .16 2 0\n"
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"fpu ftw .16 4 0\n"
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"fpu fop .16 6 0\n"
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"fpu frip .64 8 0\n"
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"fpu frdp .64 16 0\n"
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"fpu mxcsr .32 24 0\n"
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"fpu mxcr_mask .32 28 0\n"
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"fpu st0 .80 32 0\n"
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"fpu st1 .80 48 0\n"
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"fpu st2 .80 64 0\n"
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"fpu st3 .80 80 0\n"
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"fpu st4 .80 96 0\n"
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"fpu st5 .80 112 0\n"
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"fpu st6 .80 128 0\n"
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"fpu st7 .80 144 0\n"
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"mmx@fpu mm0 .64 32 8\n"
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"mmx@fpu mm1 .64 48 8\n"
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"mmx@fpu mm2 .64 64 8\n"
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"mmx@fpu mm3 .64 80 8\n"
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"mmx@fpu mm4 .64 96 8\n"
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"mmx@fpu mm5 .64 112 8\n"
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"mmx@fpu mm6 .64 128 8\n"
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"mmx@fpu mm7 .64 144 8\n"
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"xmm@fpu xmm0 .128 160 16\n"
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"fpu xmm0h .64 160 8\n"
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"fpu xmm0l .64 168 8\n"
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"xmm@fpu xmm1 .128 176 16\n"
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"fpu xmm1h .64 176 8\n"
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"fpu xmm1l .64 184 8\n"
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"xmm@fpu xmm2 .128 192 16\n"
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"fpu xmm2h .64 192 8\n"
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"fpu xmm2l .64 200 8\n"
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"xmm@fpu xmm3 .128 208 16\n"
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"fpu xmm3h .64 208 8\n"
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"fpu xmm3l .64 216 8\n"
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"xmm@fpu xmm4 .128 224 16\n"
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"fpu xmm4h .64 224 8\n"
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"fpu xmm4l .64 232 8\n"
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"xmm@fpu xmm5 .128 240 16\n"
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"fpu xmm5h .64 240 8\n"
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"fpu xmm5l .64 248 8\n"
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"xmm@fpu xmm6 .128 256 16\n"
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"fpu xmm6h .64 256 8\n"
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"fpu xmm6l .64 264 8\n"
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"xmm@fpu xmm7 .128 272 16\n"
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"fpu xmm7h .64 272 8\n"
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"fpu xmm7l .64 280 8\n"
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"xmm@fpu xmm8 .128 288 16\n"
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"fpu xmm8h .64 288 8\n"
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"fpu xmm8l .64 296 8\n"
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"xmm@fpu xmm9 .128 304 16\n"
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"fpu xmm9h .64 304 8\n"
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"fpu xmm9l .64 312 8\n"
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"xmm@fpu xmm10 .128 320 16\n"
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"fpu xmm10h .64 320 8\n"
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"fpu xmm10l .64 328 8\n"
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"xmm@fpu xmm11 .128 336 16\n"
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"fpu xmm11h .64 336 8\n"
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"fpu xmm11l .64 344 8\n"
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"xmm@fpu xmm12 .128 352 16\n"
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"fpu xmm12h .64 352 8\n"
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"fpu xmm12l .64 360 8\n"
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"xmm@fpu xmm13 .128 368 16\n"
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"fpu xmm13h .64 368 8\n"
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"fpu xmm13l .64 376 8\n"
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"xmm@fpu xmm14 .128 384 16\n"
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"fpu xmm14h .64 384 8\n"
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"fpu xmm14l .64 392 8\n"
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"xmm@fpu xmm15 .128 400 16\n"
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"fpu xmm15h .64 400 8\n"
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"fpu x64 .64 416 0\n"
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"ymm ymm0 .256 0 32\n"
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"ymm ymm1 .256 32 32\n"
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"ymm ymm2 .256 64 32\n"
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"ymm ymm3 .256 96 32\n"
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"ymm ymm4 .256 128 32\n"
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"ymm ymm5 .256 160 32\n"
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"ymm ymm6 .256 192 32\n"
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"ymm ymm7 .256 224 32\n"
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"ymm ymm8 .256 256 32\n"
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"ymm ymm9 .256 288 32\n"
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"ymm ymm10 .256 320 32\n"
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"ymm ymm11 .256 352 32\n"
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"ymm ymm12 .256 384 32\n"
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"ymm ymm13 .256 416 32\n"
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"ymm ymm14 .256 448 32\n"
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"ymm ymm15 .256 480 32\n"
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);
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