bda1e9cfca
* -Duse_gpl=false is supported by rizin and added riscv_cs for capstone v5 * Added GPL build workflow in CI
104 lines
4.9 KiB
C
104 lines
4.9 KiB
C
// SPDX-FileCopyrightText: 2021 GustavoLCR <gugulcr@gmail.com>
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// SPDX-License-Identifier: LGPL-3.0-only
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#include <rz_analysis.h>
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#include "minunit.h"
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#define SWITCH_TO_ARCH_BITS(arch, bits) \
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rz_analysis_use(analysis, arch); \
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rz_analysis_set_bits(analysis, bits);
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bool test_rz_analysis_op_val() {
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RzAnalysis *analysis = rz_analysis_new();
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RzAnalysisOp op;
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SWITCH_TO_ARCH_BITS("x86", 64);
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// mov rax, [rbx+rcx+4]
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int len = rz_analysis_op(analysis, &op, 0, (const ut8 *)"\x48\x8b\x44\x0b\x04", 5, RZ_ANALYSIS_OP_MASK_VAL);
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mu_assert_eq(len, 5, "Op is of size 5");
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mu_assert_eq(op.dst->type, RZ_ANALYSIS_VAL_REG, "Destination should be reg");
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mu_assert_streq(op.dst->reg->name, "rax", "Dst reg should be rax");
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mu_assert_eq(op.src[0]->type, RZ_ANALYSIS_VAL_MEM, "Source should be mem");
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mu_assert_streq(op.src[0]->reg->name, "rbx", "Source reg base should be rbx");
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mu_assert_streq(op.src[0]->regdelta->name, "rcx", "Source reg delta should be rcx");
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mu_assert_eq(op.src[0]->delta, 4, "Source delta should be 4");
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rz_analysis_op_fini(&op);
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len = rz_analysis_op(analysis, &op, 0, (const ut8 *)"\x48\xc7\xc0\x04\x00\x00\x00", 7, RZ_ANALYSIS_OP_MASK_VAL);
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mu_assert_eq(len, 7, "Op is of size 7");
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mu_assert_eq(op.dst->type, RZ_ANALYSIS_VAL_REG, "Destination should be reg");
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mu_assert_eq(op.src[0]->type, RZ_ANALYSIS_VAL_IMM, "Source should be imm");
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mu_assert_eq(op.src[0]->imm, 4, "Source imm should be 4");
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rz_analysis_op_fini(&op);
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SWITCH_TO_ARCH_BITS("arm", 64);
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// ldr x1, [x2, x3]
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len = rz_analysis_op(analysis, &op, 0, (const ut8 *)"\x41\x68\x63\xf8", 4, RZ_ANALYSIS_OP_MASK_VAL);
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mu_assert_eq(len, 4, "Op is of size 4");
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mu_assert_eq(op.dst->type, RZ_ANALYSIS_VAL_REG, "Destination should be reg");
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mu_assert_streq(op.dst->reg->name, "x1", "Dst reg should be x1");
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mu_assert_eq(op.src[0]->type, RZ_ANALYSIS_VAL_MEM, "Source should be mem");
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mu_assert_streq(op.src[0]->reg->name, "x2", "Source reg base should be x2");
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mu_assert_streq(op.src[0]->regdelta->name, "x3", "Source reg base should be x3");
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rz_analysis_op_fini(&op);
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// mov x1, 400
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len = rz_analysis_op(analysis, &op, 0, (const ut8 *)"\x01\x32\x80\xd2", 4, RZ_ANALYSIS_OP_MASK_VAL);
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mu_assert_eq(len, 4, "Op is of size 4");
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mu_assert_eq(op.dst->type, RZ_ANALYSIS_VAL_REG, "Destination should be reg");
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mu_assert_streq(op.dst->reg->name, "x1", "Dst reg should be x1");
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mu_assert_eq(op.src[0]->type, RZ_ANALYSIS_VAL_IMM, "Source should be imm");
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mu_assert_eq(op.src[0]->imm, 400, "Source imm should be 400");
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rz_analysis_op_fini(&op);
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SWITCH_TO_ARCH_BITS("arm", 32);
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// ldr r1, [ r2, r3 ]
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len = rz_analysis_op(analysis, &op, 0, (const ut8 *)"\x03\x10\x92\xe7", 4, RZ_ANALYSIS_OP_MASK_VAL);
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mu_assert_eq(len, 4, "Op is of size 4");
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mu_assert_eq(op.dst->type, RZ_ANALYSIS_VAL_REG, "Destination should be reg");
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mu_assert_streq(op.dst->reg->name, "r1", "Dst reg should be r1");
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mu_assert_eq(op.src[0]->type, RZ_ANALYSIS_VAL_MEM, "Source should be mem");
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mu_assert_streq(op.src[0]->reg->name, "r2", "Source reg base should be r2");
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mu_assert_streq(op.src[0]->regdelta->name, "r3", "Source reg base should be r3");
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rz_analysis_op_fini(&op);
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SWITCH_TO_ARCH_BITS("arm", 16);
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// ldr r1, [ r2, r3 ]
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len = rz_analysis_op(analysis, &op, 0, (const ut8 *)"\xd1\x58", 2, RZ_ANALYSIS_OP_MASK_VAL);
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mu_assert_eq(len, 2, "Op is of size 2");
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mu_assert_eq(op.dst->type, RZ_ANALYSIS_VAL_REG, "Destination should be reg");
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mu_assert_streq(op.dst->reg->name, "r1", "Dst reg should be r1");
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mu_assert_eq(op.src[0]->type, RZ_ANALYSIS_VAL_MEM, "Source should be mem");
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mu_assert_streq(op.src[0]->reg->name, "r2", "Source reg base should be r2");
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mu_assert_streq(op.src[0]->regdelta->name, "r3", "Source reg base should be r3");
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rz_analysis_op_fini(&op);
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#if WITH_GPL
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SWITCH_TO_ARCH_BITS("riscv", 32);
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// lw s10, 64(sp)
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len = rz_analysis_op(analysis, &op, 0, (const ut8 *)"\x06\x4d", 2, RZ_ANALYSIS_OP_MASK_VAL);
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mu_assert_eq(len, 2, "Op is of size 2");
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mu_assert_eq(op.dst->type, RZ_ANALYSIS_VAL_REG, "Destination should be reg");
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mu_assert_streq(op.dst->reg->name, "s10", "Dst reg should be s10");
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mu_assert_eq(op.src[0]->type, RZ_ANALYSIS_VAL_MEM, "Source should be mem");
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mu_assert_streq(op.src[0]->reg->name, "sp", "Source reg base should be sp");
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mu_assert_eq(op.src[0]->delta, 64, "Source delta should be 64");
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rz_analysis_op_fini(&op);
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// sw s0, 136(sp)
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len = rz_analysis_op(analysis, &op, 0, (const ut8 *)"\x22\xc5", 2, RZ_ANALYSIS_OP_MASK_VAL);
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mu_assert_eq(len, 2, "Op is of size 2");
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mu_assert_eq(op.dst->type, RZ_ANALYSIS_VAL_MEM, "Destination should be reg");
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mu_assert_streq(op.dst->reg->name, "sp", "Dst reg should be s10");
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mu_assert_eq(op.dst->delta, 136, "Source delta should be 64");
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mu_assert_eq(op.src[0]->type, RZ_ANALYSIS_VAL_REG, "Source should be reg");
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mu_assert_streq(op.src[0]->reg->name, "s0", "Source reg base should be s0");
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rz_analysis_op_fini(&op);
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#endif
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rz_analysis_free(analysis);
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mu_end;
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}
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int all_tests() {
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mu_run_test(test_rz_analysis_op_val);
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return tests_passed != tests_run;
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}
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mu_main(all_tests)
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