144b47d455
- Move trap/sw breakpoint into RzArch - Remove RzBreakpointPlugin & RzBreakpointArch - Add get_sw_breakpoint_at/get_sw_breakpoint_size_at binds - Remove `dbh-` - Change `dbh` to just list supported archs for sw breakpoints - Implement correct PPC traps - Add missing x86 breakpoint callback
55 lines
1.4 KiB
C
55 lines
1.4 KiB
C
// SPDX-FileCopyrightText: 2024 billow <billow.fun@gmail.com>
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// SPDX-License-Identifier: LGPL-3.0-only
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#include <rz_types.h>
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#include <rz_asm.h>
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#include <xtensa/xtensa.h>
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static int asm_xtensa_disassemble(RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) {
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XtensaContext *ctx = a->plugin_data;
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if (!xtensa_open(ctx, a->cpu, a->big_endian)) {
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goto beach;
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}
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if (!xtensa_disassemble(ctx, buf, len, a->pc)) {
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goto beach;
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}
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rz_asm_op_setf_asm(op,
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"%s%s%s",
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ctx->insn->mnemonic,
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ctx->insn->op_str[0] ? " " : "",
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ctx->insn->op_str);
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op->size = ctx->insn->size;
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xtensa_disassemble_fini(ctx);
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return op->size;
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beach:
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rz_asm_op_set_asm(op, "illegal");
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xtensa_disassemble_fini(ctx);
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return -1;
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}
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static char **xtensa_cpu_descriptions() {
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static char *cpu_desc[] = {
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"esp32", "Xtensa microcontroller with Wi-Fi and Bluetooth capabilities",
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"esp32s2", "Xtensa microcontroller with Wi-Fi and USB OTG support",
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"esp8266", "Xtensa microcontroller with Wi-Fi support",
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NULL
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};
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return cpu_desc;
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}
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RzAsmPlugin rz_asm_plugin_xtensa_cs = {
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.name = "xtensa",
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.license = "LGPL3",
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.desc = "Tensilica Xtensa Capstone-based disassembler",
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.author = "billow",
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.arch = "xtensa",
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.cpus = "esp32,esp32s2,esp8266",
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.bits = 32,
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.endian = RZ_SYS_ENDIAN_LITTLE | RZ_SYS_ENDIAN_BIG,
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.disassemble = asm_xtensa_disassemble,
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.init = &xtensa_init,
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.fini = &xtensa_fini,
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.get_cpu_desc = xtensa_cpu_descriptions,
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};
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