155ead6822
rz_reg_profile_to_cc() only emitted the first four argument registers (A0-A3), so architectures that pass more arguments in registers -- the C6000 EABI uses ten, and x86-64/riscv/ppc all declare more than four -- got a truncated convention. Walk the whole A0-A9 role range, stopping at the first role the profile leaves undefined, and build the cc string with RzStrBuf. Covered by a new test_reg unit test. Co-authored-by agent: Claude/claude-opus-4-8 Co-authored-by: Anton Kochkov <anton.kochkov@gmail.com>
106 lines
950 B
Text
106 lines
950 B
Text
NAME=ara swap
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FILE==
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CMDS=<<EOF
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e asm.arch=x86
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e asm.bits=64
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ara+
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ar rax=33
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ar rax
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aras
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ar rax
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EOF
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EXPECT=<<EOF
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rax = 0x0000000000000021
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rax = 0x0000000000000000
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EOF
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RUN
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NAME=ara swap 2
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FILE==
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CMDS=<<EOF
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e asm.arch=x86
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e asm.bits=64
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ara+
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ar rax=33
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ar rax
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aras
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ar rax
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aras
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ar rax
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EOF
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EXPECT=<<EOF
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rax = 0x0000000000000021
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rax = 0x0000000000000000
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rax = 0x0000000000000021
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EOF
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RUN
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NAME=ara push
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FILE==
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CMDS=<<EOF
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e asm.arch=x86
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e asm.bits=64
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ara~?
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ara+
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ara~?
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EOF
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EXPECT=<<EOF
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26
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39
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EOF
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RUN
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NAME=ara pop
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FILE==
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CMDS=<<EOF
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e asm.arch=x86
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e asm.bits=64
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ara~?
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ara+
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ara~?
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ara-
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ara~?
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ara-
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ara~?
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ara-
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ara~?
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EOF
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EXPECT=<<EOF
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26
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39
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26
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13
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13
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EOF
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RUN
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NAME=arcc+tcc
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FILE==
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CMDS=<<EOF
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e asm.arch=x86
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e asm.bits=64
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afcl
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e asm.arch=arm
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e asm.bits=32
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arcc
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e asm.arch=x86
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e asm.bits=64
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arcc
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tcc `arcc`
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afcl
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EOF
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EXPECT=<<EOF
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amd64
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amd64syscall
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ms
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reg
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swift
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r0 reg(r0, r1, r2, r3)
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rdi reg(rdi, rsi, rdx, rcx, r8, r9, r10, r11)
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amd64
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amd64syscall
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ms
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reg
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swift
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EOF
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RUN
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