29b04fa460
* added breakpoints and stepping * add link register to allow single-stepping a ret instruction, fix stacktraces * refactor to avoid passing the IO layer structs to the breakpoint function * add tests, refine the stacktrace to not include non-function * add register information for core file parsing * core file generation for RISC-V * make tests run under riscv-64 * make tests run under riscv-32
101 lines
3.1 KiB
C
101 lines
3.1 KiB
C
// SPDX-FileCopyrightText: 2024-2026 moste00 <ubermenchun@gmail.com>
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// SPDX-FileCopyrightText: 2019 pancake <pancake@nopcode.org>
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// SPDX-License-Identifier: BSD-3-Clause
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#include <rz_asm.h>
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#include "asm_private.h"
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#include <rz_lib.h>
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#include <capstone/capstone.h>
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#include "cs_helper.h"
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CAPSTONE_DEFINE_PLUGIN_FUNCTIONS(riscv_asm);
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static int riscv_disassemble(const RzAsm *a, RzAsmOp *op, const ut8 *buf, int len) {
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CapstoneContext *ctx = (CapstoneContext *)a->plugin_data;
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int ret = -1;
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cs_insn *insn;
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cs_mode mode = (a->bits == 64) ? CS_MODE_RISCV64 : CS_MODE_RISCV32;
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mode |= mode_from_arch_string(a->cpu);
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mode |= resolve_features_from_list(a->features);
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op->size = 4;
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if (ctx->omode != mode) {
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cs_close(&ctx->handle);
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ctx->omode = -1;
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}
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if (!ctx->handle) {
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ret = cs_open(CS_ARCH_RISCV, mode, &ctx->handle);
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if (ret) {
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goto fin;
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}
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ctx->omode = mode;
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// cs_option (ctx->handle, CS_OPT_DETAIL, CS_OPT_OFF);
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}
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int n = cs_disasm(ctx->handle, (ut8 *)buf, len, a->pc, 1, &insn);
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if (n < 1) {
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rz_asm_op_set_asm(op, "invalid");
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op->size = 2;
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goto fin;
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}
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if (insn->size < 1) {
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goto fin;
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}
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op->size = insn->size;
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rz_asm_op_setf_asm(op, "%s%s%s", insn->mnemonic, insn->op_str[0] ? " " : "", insn->op_str);
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char *str = rz_asm_op_get_asm(op);
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if (str) {
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// remove the '$'<registername> in the string
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rz_str_replace_char(str, '$', 0);
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}
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cs_free(insn, n);
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fin:
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return op->size;
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}
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/*
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* \brief Places a breakpoint instruction at addr depending on the size of the original instruction there
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* The returned instruction bytes are either (in big endian hex notation):
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* 0x00100073 → ebreak, or
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* 0x9002 → c.ebreak
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* \param a [in] The asm plugin.
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* \param addr [in] The address to place the breakpoint.
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* \param original [in] The original asm op at addr.
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* \param breakpoint [out] The asm op to store the breakpoint instruction.
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* \return true if the breakpoint was placed successfully, false otherwise.
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*/
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static bool riscv_sw_breakpoint(const RzAsm *a, ut64 addr, const RzAsmOp *original, RzAsmOp *breakpoint) {
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if (original->size == 2) {
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rz_asm_op_set_buf(breakpoint, a->big_endian ? (const ut8 *)"\x90\x02" : (const ut8 *)"\x02\x90", 2);
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} else if (original->size == 4) {
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rz_asm_op_set_buf(breakpoint, a->big_endian ? (const ut8 *)"\x00\x10\x00\x73" : (const ut8 *)"\x73\x00\x10\x00", 4);
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} else {
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RZ_LOG_ERROR("Can't set breakpoint at 0x%" PFMT64x " : bad size (%ld bytes) of the instruction there, RISC-V instructions are expected to either be 2 or 4 bytes\n", addr, original->buf.len);
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return false;
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}
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return true;
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}
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RzAsmPlugin rz_asm_plugin_riscv_cs = {
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.name = "riscv",
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.desc = "RISC-V Capstone-based disassembler",
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.license = "BSD",
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.arch = "riscv",
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.cpus = ARCH_RISCV_CPUS,
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.features = ARCH_RISCV_FEATURES,
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.bits = 32 | 64,
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.endian = RZ_SYS_ENDIAN_LITTLE | RZ_SYS_ENDIAN_BIG,
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.init = riscv_asm_init,
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.fini = riscv_asm_fini,
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.disassemble = &riscv_disassemble,
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.mnemonics = riscv_asm_mnemonics,
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.sw_breakpoint = riscv_sw_breakpoint,
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};
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#ifndef RZ_PLUGIN_INCORE
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RZ_API RzLibStruct rizin_plugin = {
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.type = RZ_LIB_TYPE_ASM,
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.data = &rz_asm_plugin_riscv_cs,
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.version = RZ_VERSION
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};
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#endif
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